A Multiplier-Free Residue to Weighted Converter. for the Moduli Set {3 n 2, 3 n 1, 3 n }

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1 Cotemporary Egeerg Sceces, Vol., 8, o., 7-8 A Multpler-Free Resdue to Weghted Coverter for the Modul Set {,, } Amr Sabbagh Molahosse ad Mehd Hossezadeh Islamc Azad Uversty, Scece ad Research Brach, Tehra, Ira amr.sabbagh@sr.au.ac.r, hossezadeh@sr.au.ac.r Keva Nav Faculty of Electrcal ad Computer Egeerg Shahd Behesht Uversty, Tehra, Ira av@sbu.ac.r Abstract The resdue umber system (RNS) s a carry-free umber system whch ca support hgh-speed ad parallel arthmetc. Oe of the major ssues effcet desg of RNS systems s the resdue to weghted coverso. I ths paper, we preset a effcet desg of resdue to weghted coverter for the ewly troduced modul set {,, }, based o mxed-radx coverso (MRC) algorthm. The proposed resdue to weghted coverter s adder-based ad memory-less whch ca results a hgh-performace hardware. The proposed resdue to weghted coverter has better performace ad also elmates the use of multpler, compared to the last work. Keywords: Computer arthmetc, Resdue umber system (RNS), Multple-valued logc (MVL), Resdue to weghted coverter Itroducto The resdue umber system (RNS) s a o-weghted umber system whch speed up arthmetc operatos by dvdg them to smaller parallel operatos. Sce the arthmetc operatos each modul are depedet of the others, there s o carry propagato amog them ad so RNS leads to carry-free addto, multplcato ad borrow-free subtracto []. Oe of the major ssues effcet desg of RNS systems s the resdue to weghted coverso. The algorthms of

2 7 A. Sabbagh Molahosse, M. Hossezadeh, K. Nav resdue to weghted coverso are maly based o chese remader theorem (CRT), mxed-radx coverso (MRC) [] ad ew chese remader theorems (New CRTs) []. I addto to these, ovel coverso algorthms [] whch are desged for some specal modul sets have bee proposed. Multple-valued logc (MVL) has bee proposed as a meas for reducg the power, mprovg the speed, ad creasg the packg desty of VLSI crcuts [4]. I MVL, the umber of dscrete sgal values or logc states exteds beyod two. Arthmetc uts mplemeted wth MVL acheve more effcet use of slco resource ad crcut tercoectos [5]. There s a clear mathematcal attracto of usg multple-valued umber represetato RNS. The modular arthmetc that s heret MVL ca be match wth modular arthmetc eeded RNS. The frst MVL-RNS system was troduced by Soderstrad et al. [6] to desg a hgh speed FIR dgtal flter. The resdue to weghted coverter proposed [6] s based o chese remader theorem (CRT) ad mplemeted wth read-oly memores (ROM's). ths coverter s practcal to mplemet small ad medum RNS dyamc rages ad t s ot approprate for large dyamc rages. I [7], ew RNS systems based o the modul of forms r a, r b ad r c + are preseted. Abdallah et al. [7] developed a systematc framework utlzg hgh-radx arthmetc for effcet MVL-RNS mplemetatos ad proposed may radx-r modul sets. Ths modul sets are ot clude parwse relatvely prme modul, ad ths resultg reduced dyamc rages ad ubalaced modul. The resdue to weghted coverter preseted [7] s based o CRT ad because of the scaledow factors whch are used for makg modul parwse relatvely prme, coverso delay ad cost are creased. Recetly, I [8] a ew resdue umber system based o the modul set {,, } was troduced. Ths modul set cludes parwse relatvely prme ad balaced modul that offers large dyamc rage ad smple realzato of related crcuts. The resdue to weghted coverter preseted [8] s based o CRT ad requres multplers ad large modulo adder, so ts area ad delay complextes have bee creased. I ths paper, we developed a two-level MRC algorthm for desgg a effcet resdue to weghted coverter for the modul set {,, }. The proposed hardware archtecture for resdue to weghted coverter s multplerfree ad memoryless. I comparso wth the resdue to weghted coverter proposed [8], our coverter has better performace terms of area ad delay. Backgroud A resdue umber system s defed terms of a relatvely-prme modul set {,,, } that s gcd(, j )= for j ad, j =,,...,. A weghted umber X ca be represeted as X=(x,x,,x ), x = X mod = X, x < () Such a represetato s uque for ay teger X the rage [,M-],

3 Multpler-free resdue to weghted coverter 7 M= s the dyamc rage of the modul set {,,, } [9]. Addto, subtracto ad multplcato o resdues ca be performed parallel wthout ay carry propagato amog the resdue dgts. Hece, by covertg the arthmetc of large umbers to a set of the parallel arthmetc of smaller umbers, the RNS represetato yelds sgfcat speed up. The algorthms of resdue to weghted coverso are based maly o chese remader theorem (CRT) ad mxed-radx coverso (MRC). Chese Remader Theorem: by CRT, the umber X s calculated from resdues by X = a X = x N M = M M = M ad N M () = s the multplcatve verse of M modulo. Mxed-Radx Coverso []: the weghted umber X ca be computed by a + a + a () = a s are called the mxed-radx coeffcets ad they ca be obtaed from the resdues by a ((( x a ) a ) a ) = (4) > ad a =x. For a smple -modul set {, }, the umber X ca bcoverted from ts resdue represetato (x,x ) by X = a + a = x + ( x x ) (5) s the multplcatve verse of modulo. The RNS wth Modul Set {,, }: I [8], a ew modul set {,, } was troduced for RNS. Ths modul set cotas parwse relatvely prme ad balaced modul whch ca offer large dyamc rage ad fast teral RNS processg. Because of usg of hgh radx (r=), ths RNS ca be smply realzed terary-valued logc (TVL). Addto crcuts for modul set {,, } ca be obtaed by usg the method of [8] as follow. If we cosder three umbers A, B ad C as the resdues respect of the modulo m, the addto of these umbers modulo m, ca be performed as A + B + C < m A + B + C (6) A + B + C m A + B + C m I other words, f the result s greater tha or equal to the modul, we add t to the complemet of the modul ad gore the carry out. For performg the addto operato the modulo, we add up two umbers ad as the carry out s a multple of, we smply gore the carry out. The correspodg crcut s llustrated Fg.. It should be oted that the full adder (FA) basc cell terary s a 4-put adder cell [7].

4 74 A. Sabbagh Molahosse, M. Hossezadeh, K. Nav A B C -dgt Adder Fg.. Modulo adder I modulo f the result s greater tha or equal to the the the result wll be added to the complemet of the modulo,.e. ( )=. By usg parallelsm, the result ad the same result plus oe are geerated smultaeously ad by usg a multplexer, the correct value wll be drected to the output. The correspodg crcut s preseted Fg.. A B C A B C -dgt Adder -dgt Adder MUX Fg.. Modulo adder I modulo, f the result of addto s greater tha or equal to the t wll be added to the complemet of the modulo whch s ( )=. A terestg property of TVL s the possblty of havg a carry geerated equal to two ( a adder the base, carry ca be betwee zero ad ). Fg. shows the crcut of ths modulo adder. A B C A B C -dgt Adder -dgt Adder MUX Fg.. Modulo adder

5 Multpler-free resdue to weghted coverter 75 Resdue to Weghted Coverso Algorthm We propose a two-level coverso algorthm for the resdue to weghted coverso of the modul set {,, }. I the frst level we use a MRC block for combg the two resdues. The secod level cossts of aother MRC block combg the result of the frst level wth the thrd resdue. Fg. 4 shows the block dagram of the proposed resdue to weghted coverter. x x x two-chael MRC usg modul set {, } two-chael MRC usg modul set { ( ), } X Fg. 4. Block dagram of the proposed coverter The followg propostos are eeded for the dervato of our algorthm. roposto : the multplcatve verse of modulo s k =( )/. roof: t s clear that =, so ( ) k ( ) = ( ) = = (7) roposto : the multplcatve verse of ( ) modulo s k =. roof: Sce ad =, we have k ( = = ) = = ( ) Cosder the three-modul set {,, } ad let the correspodg resdues of the teger X be (x,x,x ). Cosder the modul set {, }ad Z=(x,x ). Usg the MRC coverso algorthm (5), Z ca be calculated by Z = x + ( ) k ( x x (9) ) k ( ) () = Substtutg the value of k from proposto to (9) gves ( ) Z = x + ( ) ( x x ) () The above equato ca be rewrtte as (8)

6 76 A. Sabbagh Molahosse, M. Hossezadeh, K. Nav Z = x + ( ) T () T ( ) ( x x ) = () we kow that ( ) ( ) = Therefore, () ca be rewrtte as ( ) (4) T = ( ) ( x x ) ( ) ( ) = ( ) V = V + V V (5) V x x (6) V s (5) ca be obtaed by the dgt left shftg of V. Sce the fal result of the addto of V temrs must be reduced modulo, we oly eed to cosder the least sgfcat dgts of V terms, ad the other dgts are gored as they are multples of. The equato () ca be rewrtte as Z = x + T T (7) Now, cosder the modul set { ( ), }ad X=(Z,x ). Usg the dervato lke before, X ca be calculated by X = Z + ( ) k ( x Z ) (8) k ( ) = (9) By substtutg the value of k from proposto, we have X = Z + ( ) Z x () So, () ca be rewrtte as X = Z + D D = ( Z + D) + ( D D) () D = Z x () Sce Z s a -dgt umber, we ca wrte D = Z + Z x = Z + Z x () Z ad Z have dgt level represetato as = z z z ) (4) Z ( + Z ( z z ) = (5) z Example: Gve the modul set {,, } =. The resdue umber (,4,) coverted to ts equvalet weghted umber as follow For = the modul set s {7,8,9}. So, by substtutg values () ad () we have

7 Multpler-free resdue to weghted coverter 77 Z = = 9 9 X = = 9 8 To verfy the result, we have x = 9 7 = x = 9 8 = 4 x = 9 9 = Therefore, the weghted umber 9 has RNS represetato as (,4,) the RNS wth modul set {7,8,9}. 4 Hardware Implemetato The MRC block of the frst level are represeted by equatos (5) (7) as equatos () ad () represet the MRC block of the secod level. Detals o the frst-level ad secod-level are as follow. The Frst Level: Equato (6) ca be calculated by a regular -dgt terary adder. The, (5) s mplemeted by a -dgt terary multoperad adder whch s cossts of a -dgt terary carry save adder (CSA) tree followed by a regular -dgt terary adder. Fally, (7) ca be calculated by a -dgt regular terary adder. It should be oted that sce x s a -dgt umber, o extra hardware s eeded for computato of x + T. The desred result ca be obtaed by cocateatg x wth T. Fg. 4(a) shows the hardware mplemetato of the frst level of the resdue to weghted coverter. The Secod Level: Equato () ca be performed by a -dgt modulo( ) terary adder whch s show Fg.. calculato of () rely o a -dgt terary adder followed by a -dgt regular terary adder. Lke before, sce Z s a -dgt umber, o extra hardware s eeded for computato of Z+ D. Fg. 4(b) shows the hardware mplemetato of the secod level of the resdue to weghted coverter. As show fgures ad, the proposed resdue to weghted coverter for the modul set {,, } s multpler-free ad cossts of terary adders. The resdue to weghted coverter for the modul set {,, } whch s preseted [8], s based o drect mplemetato of the CRT algorthm ad requres -dgt terary multplers ad a modulo ( )( )( ) terary adder for fal reducto. So, as a result, the coverter of [8] acheve log coverso delay ad hgh hardware cost. But the larger modulo adder used our coverter s a modulo ( ) adder ad also the proposed desg elmates the use of multpler. Therefore, our proposed resdue to weghted coverter has better performace tha the resdue to weghted coverter of [8].

8 78 A. Sabbagh Molahosse, M. Hossezadeh, K. Nav x x V -dgt terary adder V V -dgt terary CSA tree C -dgt terary adder T x + T T T S V Z Z -dgt modulo ( ) terary adder D Z 44 + D D x D -dgt terary adder 4 4 ( D D) -dgt terary adder Z (a) -dgt terary adder X (b) Fg. 4 Hardware archtecture of the frst level (a) ad the secod level (b) of the coverter 5 Cocluso I ths paper a effcet desg of the resdue to weghted coverter for the modul set {,, } s preseted. The proposed hardware mplemetato of the resdue to weghted coverter s multpler-free ad memoryless, whch ca be effcetly mplemeted VLSI. I comparso wth the last resdue to weghted coverter for the modul set {,, }, the proposed desg has better performace. Refereces [] B. arham, Computer arthmetc: algorthms ad hardware desgs, Oxford Uversty ress,.

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