NECESSARY AND SUFFICIENT CONDITIONS FOR DEADLOCKS IN FLEXIBLE MANUFACTURING SYSTEMS BASED ON A DIGRAPH MODEL

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1 Asian Journal of Control, Vol. 6, No. 2, pp , June NECESSARY AND SUFFICIENT CONDITIONS FOR DEADLOCKS IN FLEXIBLE MANUFACTURING SYSTEMS BASED ON A DIGRAPH MODEL Wenle Zhang, Robert P. Judd, and Paul Deering ABSTRACT As typical discrete event systems, flexible manufacturing systems have been extensively studied in such aspects as modeling, control and performance analysis. One important topic in the study of such systems is the deadlock detection, prevention and avoidance. In the past decade, two major modeling formalisms, i.e., Petri nets and digraphs, have been adopted for developing deadlock control policies for flexible manufacturing systems. In this paper, the concepts of slack, knot, order and effective free space of circuits in the digraph are established and used to concisely and precisely quantify the sufficient conditions for a system state to be live. Necessary conditions for this liveness is quantified for a special class of system states called evaluation states. The significance of the result is that the conditions are true for avoiding both primary deadlocks and impending deadlocks that are arbitrary steps away from a primary one, whereas only second level deadlocks have been studied in the literature. Examples are provided to illustrate the method. KeyWords: Flexible manufacturing systems, deadlock avoidance, deadlock prevention, petri net, digraph. I. INTRODUCTION In modern flexible manufacturing systems (FMS), multiple types of parts are manufactured concurrently and multiple resources are shared among these parts. Such systems often run into deadlocks, a situation where parts being made cannot advance due to resource request conflict. In recent years, research on deadlock detection, prevention and avoidance for flexible manufacturing systems has been very active. Some of the significant work have adopted Petri net (PN) models [1,2,4,6,7, 12-14] as a formalism to describe the manufacturing system. Banaszak and Krogh [1] proposed a deadlock avoidance algorithm (DAA) that developed a restriction policy to guarantee that no circular wait situations will Manuscript received April 15, 2003; revised January 10, 2004; accepted February 18, Wenle Zhang and Robert P. Judd are with School of Electrical Engineering and Computer Science, Ohio University, Athens, OH Paul Deering is with Russ College of Engineering and Technology, Ohio University, Athens, OH occur. Viswanadham et al. [12] developed a deadlock avoidance algorithm which suggested using a recovery mechanism in case of system deadlock. Zhou [14] developed the sequential mutual exclusions (SME) and parallel mutual exclusions (PME) concepts and derived the sufficient conditions for a PN containing such structures to be bounded, live, and reversible. Structural properties of PNs such as siphons and traps are used in [2,4] to determine potential deadlock situations. Another formalism is to describe the manufacturing system using graphs [3,5,8-11]. In this approach the vertices represent resources and the edges represent product part flows between resources. Wysk et al. [11] developed a deadlock detection method based on a graph formalism of a FMS. They found a circuit in the graph is a necessary condition for system deadlock. To detect deadlock, they proposed to use a string manipulation algorithm to identify circuits in the graph. Cho et al. [3] developed the concept of bounded circuits with empty and non-empty shared resources to detect deadlock. Fanti et al. [5] developed a simple graph-theoretic method for deadlock detection and recovery in systems with multiple capacity resources. Judd and Faiz [8] de-

2 218 Asian Journal of Control, Vol. 6, No. 2, June 2004 rived a set of static linear inequalities that when they are satisfied deadlock is avoided. It has been challenging to find a solution to avoid impending deadlocks that is arbitrary steps away from a primary one. Fanti et al. [5] studied second level deadlock the impending deadlock one step away from primary deadlock. Barkaoui and Abdallah [2], in addition to control place augmentation, used a one step look-ahead controller, which cannot avoid impending deadlocks that are more than one step away. Lawley and Reveliotis [10] identified special classes of systems that present no impending deadlocks. The focus of this paper is to thoroughly analyze interactions among circuits of the digraph of a system, which will lead to deadlock avoidance policies that would allow more live states while avoid all deadlock states. Contribution of this paper includes establishing concepts such as the slack, knot, order and the effective free space of a circuit in the digraph, concise and precise quantifying the sufficient conditions for a system state to be live and deriving the liveness necessary and sufficient conditions for a special class of states called evaluation states. The significance of the result is that the conditions are true for avoiding both primary deadlocks and impending deadlocks that are arbitrary steps away from a primary one, whereas only second level deadlocks have been studied in the literature. Based on the sufficient conditions, two deadlock avoidance policies have been developed. Simulation results show that policy II is very promising and has a very high permissiveness. The rest of the paper is organized as follows. Section 2 describes the digraph model of a flexible manufacturing system and the related basic concepts. Section 3 presents the sufficient condition for a system state to be live. Section 4 presents the necessary and sufficient conditions for a system to be live in an evaluation state. Section 5 develops the two deadlock avoidance policies. Finally, section 6 provides some discussion and possible future research directions. II. THE SYSTEM MODEL AND DEADLOCKS A flexible manufacturing system consists of a set R of a finite number of resources (such as, NC machines, robots, buffers, etc.), R = {r 1, r 2,, r N }, a set P of a finite number of part types that the system can produce, P = {p 1, p 2,, p M }. Each part type p i P is assigned a process plan that defines a finite number of steps of operations need to be performed on parts of the type. We assume that each step be performed on exactly one resource. Thus a process plan p i can be simplified as a sequence of resources p i = r 1 r 2 r Li, L i is the length of process plan p i, where the last resource r Li is called the terminal step. Each resource r i R has a capacity, denoted as C i, which can be considered as a multiple of identical units. The capacity can be naturally extended to a set of resources, R 1 R, as C R1. Once the system is in operation, there will exist a set Q of parts in the system at any given time. Each part q Q belongs to a part type p P, denoted as P q = p. Each part has a unique current step, denoted as S q, which can be considered as the state of the part. When a new part q is first loaded into the system, S q = 1. A part q that has exited the system or is still waiting for being loaded has S q = 0. We often use p ij to represent a part of type p i at step j. The state of the system, denoted as n, is defined as a vector of C R elements corresponding to the current steps of all parts. An element of n has value 0 for an empty resource unit. As a typical industrial automation system, the detailed operation of a FMS would be controlled by networked multiple programmable controllers or other type of industrial computers and there would be numerous events. However, for our purpose, we are interested in analyzing the system for a relatively high level control. Thus, we consider that the system state can be changed by the following three types of system events: i) Load part event: A new part p i0 is introduced into the system, if there is a free unit in the resource that the part s first process step must visit. ii) Unload part event: A finished part p ili is leaving the system. This part can always leave the system after its last process step is finished. iii) Advance part event: A part p ij in the middle of its process plan is moving to its next process step, if the resource needed by its next step has free unit. We also assume that all events are controllable. 2.1 The digraph model of a FMS For the purpose of deadlock analysis, we define the wait relation graph (WRG) for a flexible manufacturing system as a directed graph G = (R, A) consisting of a set R of vertices that correspond to resources of the system and a set A of directed arcs that are determined by process plans of the system. Each vertex represents a resource, graphically represented as an oval, which can be filled with a part. A directed arc a is drawn from vertex r 1 to vertex r 2, if resource r 2 immediately follows resource r 1 in at least one process plan, denoted as a = r 1 r 2. A vertex (or resource) r is said to be converging if more than one arc enters the vertex. It is non-converging if only one arc enters the vertex. Example 2.1 Consider a simple manufacturing system that has 7 resources all with capacity one. Suppose the system make two types of parts, type a part has process plan p a = r 4 r 1 r 2 r 3 r 4 r 5, type b parts has p b = r 5 r 6 r 7 r 4 r 1. The

3 W. Zhang et al.: Necessary and Sufficient Conditions for Deadlocks in Flexible Manufacturing 219 r 2 r 1 r 5 r 6 a 2 a 3 c 1 a 1 r 3 r 4 b 3 c 2 b 1 Fig. 1. Digraph for example 2.1. WRG can be drawn as in Fig. 1. In the given state n, parts a 1, a 2 and a 3 are of type a, parts b 1, b 2 and b 3 are of type b. A subgraph G 1 = (R 1, A 1 ) of G consists of a subset of the vertices and a subset of arcs of G such that all the arcs in A 1 connect vertices in R 1. A circuit is a subgraph that is a strongly connected component of G, which can be represented as a sequence of vertices with the first and last vertex being the same, e.g., c 1 = r 1 r 2 r 3 r 4 r 1. A simple circuit is a circuit that does not contain any other circuit. The union (intersection) of two subgraphs, denoted by G 1 G 2 (G 1 G 2 ), is the union (intersection) of the two sets of vertices and the two sets of arcs of G 1 and G 2, respectively. Definition 2.1 A unit of the resource r 1 is said to be committed to arc a if it is processing a part q whose next resource is r 2, where a = r 1 r 2. We also say that q commits to arc a. Let M a, n denote the number of resource units that are committed to arc a when the system is in state n. The commitment can be naturally extended to a set of arcs as follows, M = M,forany A A A1, n a, n 1 a A1 Note that the number of resource units committed to the outgoing arcs of r can be less than the number of busy units. This happens when some of the busy units are being used as terminal steps. A resource unit is free if it is not committed to an arc; by this definition, a busy unit that is not committed is still termed free. Definition 2.2 The slack of any subgraph G 1 = (R 1, A 1 ) when the system is in state n, denoted as K G1, n is given by K = C M G1, n R1 A1, n The slack can be understood as the number of available free resource units to allow for parts flow on the subgraph. Lemma 2.1 Let G 1 and G 2 be two subgraphs of a WRG G in state n. Then K = K + K K G1 G2, n G1, n G2, n G1 G2, n Proof. This is a direct result of definition 2.2. r 7 b Deadlocks in a FMS In the flexible manufacturing system described earlier, the M types of parts can be concurrently manufactured among the N resources with system capacity C R. Due to limited system capacity and concurrency, parts in the system may have to share resources. Such a system often runs into deadlock, a situation where parts being made cannot advance due to resource request conflict. A part q is enabled in state n if its next resource is free. If part q is currently being processed in resource r 1 and its next resource is r 2, then q is enabled means that once r 1 finishes its operation on q, the part can be transported from r 1 to r 2. This part movement process is called the part propagation. Definition 2.3 A system state n is live if a sequence of part propagations exists such that the system can be emptied. Otherwise, the state is in deadlock. Deadlocks can be further categorized into two major types, primary deadlock and impending deadlock. A system state n is in primary deadlock if a circular wait situation exists [1]. A primary deadlock can be understood as a siphon in the Petri net model of the system becomes empty of tokens, or as a circuit in the digraph model is filled with parts where no part is enabled. A system state n is in impending deadlock if it is not in primary deadlock and parts exist in the system that can be propagated, but the system cannot be emptied. Shown in Fig. 2 is an example of primary deadlock where the four parts form a circular wait situation. The state shown in Fig. 1 is an impending deadlock, where advancing either a 1 or b 1 to resource r 4 will result in a primary deadlock. III. SUFFICIENT CONDITIONS FOR A LIVE STATE Part of our preliminary research results has been published in [9]. Results presented here are improved or more formally formulated, in addition to new developments. In this section, the necessary and sufficient conditions for liveness of a manufacturing system whose digraph contains only a single simple circuit will be presented first. Then sufficient conditions for liveness of systems with circuits interactions will be developed. 3.1 Liveness of a simple circuit A necessary condition for a system to be in deadlock is that the system WRG contains a circuit [11]. For a simple circuit, the following necessary and sufficient conditions for liveness are obvious.

4 220 Asian Journal of Control, Vol. 6, No. 2, June 2004 r 2 a 4 r 1 b 2 r 3 a a 3 a 2 a 1 r 3 r 4 Fig. 2. A primary deadlock example, where the process plan for all parts is p a = r 1 r 2 r 3 r 4 r 1. Theorem 3.1. Given a manufacturing system in state n, if its WRG G = (R, A) consists of a simple circuit only, then the state is live if and only if K G, n > Liveness of WRG with circuits interactions Example 3.1 Revisit example 2.1. The state n shown in Fig. 1 is in deadlock. Now assume p b = r 5 r 6 r 7 r 4 r 5. Then n is a live state. To help distinguish between the two cases, the concepts of knot, order of a knot, order of a circuit will be developed in the following. Definition 3.1 Let c 1, c 2,, c m, m > 1, be m circuits in a WRG G. If their intersection c 1 c 2 c m contains exactly one resource with capacity one, then the resource is called a knot. Knots are also termed as key resources in some literature, such as Gural et al. [16]. c 1 is connected to c 2 if a part currently exists in the system in state n that must propagate through an arc of c 1 to c 2 and commit an arc on c 2, denote as c 1 c 2. c 1, c 2,, c m are cyclically connected if c 1 c 2, c 2 c 3,, c m c 1. When m = 2, c 1 and c 2 are called cross-connected, denoted as c 1 c 2. Definition 3.2 Let a circuit c consist of m circuits, c 1, c 2,, c m, such that c = c 1 c 2 c m and c 1 c 2 c m = k where k is a knot. The order of knot k with respect to the circuit c in state n, denoted as O k, c, n, is defined as O kc,, n 1, if two or more circuits are cyclically = connected. 0, otherwise. Based on this definition, if c 1 and c, c 1 c, are two circuits and K = {all knots on c 1 }. Then, Okc,, n = Okc, 1, n, k K. This definition can be extended to a circuit. Let c be a circuit that contains m knots. Then, the order of c is given by O m c, n = Oki, c, n i= 1 d r 2 a c 1 r 1 r 6 c 2 b 1 r 4 c 3 r 5 Fig. 3. WRG for example 3.2. c 4 r 7 d b The order of any simple circuit is zero. Since a simple circuit does not contain any other circuits, so it has no knot. Definition 3.3 Let c be a circuit in a WRG G in state n. The effective free space (EFS) of c, denoted as F c, n, is given by, F = K O c, n c, n c, n where K c, n is the slack of circuit c and O c, n is the order of circuit c. Example 3.2 Consider the WRG G of a manufacturing system shown in Fig. 3 where all resources are of capacity one and three process plans are defined as p a = r 1 r 6 r 2 r 3, p b = r 3 r 4 r 6 r 5 r 7 and p d = r 7 r 5 r 6 r 1. G is composed of four simple circuits c 1, c 2, c 3 and c 4 joined together by two knots r 5 and r 6. Shown in Table 1 are orders and EFSs calculated in the given state n 0 = [S a, 0, S b2, S b1, 0, 0, S d ] = [1, 0, 1, 2, 0, 0, 1]. Lemma 3.1 Let G 1 = (R 1, A 1 ) be any subgraph of a WRG in state n 0. Assume there exists an enabled part q committing to arc a in G 1. If n 1 is the resulting state of the system after q is propagated along arc a, then propagating q results in M M A1, n1 A1, n 0 Proof. Assume a = r 1 r 2. After propagation, the part is transferred from r 1 to r 2, M a, n1 = M a, n0 1 and it may or may not commit to another arc in A 1. Hence, M A1,n1 either remains the same or decreases by one. The following corollary shows that the EFS of any subgraph cannot decrease due to part propagation along an arc within the subgraph. Corollary 3.1 Under the same assumption as of lemma 3.1, F G1, n1 F G1, n0. Proof. First, combining definition 2.2 and lemma 3.1, we have K G1, n1 K G1, n0. Then, consider all connected circuits in G 1 in state n 0. After propagating a part in G 1, all

5 W. Zhang et al.: Necessary and Sufficient Conditions for Deadlocks in Flexible Manufacturing 221 Table 1. EFS computations for example 3.2. Circuit Slack Order EFS Circuit Slack Order EFS c c 2 c c c 3 c c c 1 c 2 c c c 1 c 3 c c 1 c c 2 c 3 c c 1 c c 1 c 2 c 3 c connected circuits will either remain connected or become disconnected. So, the set of connected circuits cannot increase, thus the order of G1 cannot increase. That is, O G1, n1 O G1, n0. From definition 3.3, we have, F G1, n1 F G1, n0. Proof. Propagating part q to resource r 2 does not commit q to any new circuits and does not affect the order. K G, n1 either remains the same or increases by one depending on whether r 2 is the terminal step of q or not. Therefore, F c, n1 F c, n0 > 0. Definition 3.4 A part q in WRG G can be shifted to resource r if it can be continuously propagated to r without propagating any other part in G. q can freely exit if it can be shifted to its terminal resource. Theorem 3.2 Given a part q in a WRG G that can freely exit, then removing part q from G will not decrease the EFS of any circuit of G. Proof. This is a direct result of Corollary 3.1. Given a WRG with EFS of all circuits greater than zero, the strategy to establish the sufficient conditions for liveness is to find an enabled part such that when it is propagated, the EFS of all circuits will remain greater than zero. Repeat this process. If a sequence of part propagations exists that will empty the system, then the original system state must be live. The approach to emptying the parts in a WRG will be accomplished by using the following three separate methods. These are the only three cases possible when propagating an enabled part. i) Parts that propagate to a non-converging resource. ii) Parts that propagate to a converging resource where all circuits have EFS greater than one. iii) Parts that propagate to a converging resource where one or more circuits have EFS equal to one Propagation to a non-converging resource For propagating a part to a non-converging resource on a circuit, we have the following theorem. Theorem 3.3 Let C G be the set of circuits in a non-empty WRG G in state n 0. Let a 0 = r 1 r 2 be the arc part q commits in state n 0 and r 2 be a non-converging resource. If F c, n0 > 0, c C G, then F c, n1 > 0, c C G Propagation to circuits with EFS greater than one The following theorem will show that propagating a part to a converging resource on circuits with EFS greater than one will not cause EFS of any circuit to become zero. Theorem 3.4 Let C G be the set of circuits in a non-empty WRG G in state n 0. Let a 0 = r 1 r 2 be the arc part q commits in state n 0. Assume that after part q is propagated to resource r 2, it commits to arc a 1 in state n 1. Let C = {c C G : a 0 c and a 1 c}. If F c, n0 > 1, c C and F c, n0 > 0, c C G C, then F c, n1 > 0, c C G. Proof. Two cases will be considered. Case 1. c C G C. If a 0 c and a 1 c, then according to corollary 3.1, F c, n1 F c, n0 > 0. If a 0 c and a 1 c, then one unit of r 1 is freed on c, that is, F c, n1 = F c, n0 + 1 > 0. If a 0 c and a 1 c, then obviously c has no space change. Case 2. c C. By propagating part q to r 2 and committing to arc a 1 in state n 1, the EFS on c can only decrease by one. Therefore, F c, n1 = F c, n0 1 > 0, c C Propagation to circuits with EFS equal to one An algorithmic method will be developed to determine which part can be safely shifted into a converging resource r where some of the circuits containing r have EFS equal to one. The part will be selected such that when it is shifted to r, it will not decrease the EFS of any circuit of the WRG to zero. Definition 3.5 Given r is a free resource and q is a part of WRG G, define the set Q s (r) = {q : q can be shifted to r}. Let C be the set of circuits containing r. If c C has a

6 222 Asian Journal of Control, Vol. 6, No. 2, June 2004 single pair of arcs to/from r, then c is a fundamental circuit of C. If all the elements of C are fundamental circuits, then C is called a fundamental set. Let C f be the largest subset of C that is a fundamental set, then every c C can be expressed as the union of one or more element of C f. An example will clarify this definition. In Fig. 3, let r 6 be the free resource, then C = {c 1, c 2, c 3, c 1 c 2, c 1 c 3, c 2 c 3, c 3 c 4, c 1 c 2 c 3, c 1 c 3 c 4, c 2 c 3 c 4, c 1 c 2 c 3 c 4 }, C f = {c 1, c 2, c 3, c 3 c 4 }. Notice that c 4 is not in C since c 4 does not contain r 6 and every circuit of C can be expressed as the union of one or more element of C f. Algorithm 3.1 Let WRG G be in state n 0. Let C G be the set of all circuits in G. Suppose F c,n0 > 0, c C G and r is a free resource in G such that there exists a circuit c that contains r and has F c, n0 = 1. The algorithm given in Fig. 4 will find a part q* in G such that when q* is shifted to r, the resulting state n* has F c, n* > 0, c C G. Algorithm 3.1 will terminate, since the set C 0 is finite. In step 8 of algorithm 3.1, an element is subtracted from the set each iteration until i 1 C =1. In this case, the condition in step 7 has to be satisfied, since according to corollary 3.1, propagating a part on a circuit cannot decrease its EFS. Essentially the algorithm will select a part to be shifted to a fundamental circuit that either has EFS > 1 or the part will remain on the same circuits after being shifted into r. In example 3.1, when p b = r 5 r 6 r 7 r 4 r 5, all circuits c 1, c 2 and c 1 c 2 have EFS = 1. Q s (r 4 ) = {a 1, b 1 }. The algorithm will find b 1 can be shifted into r 4 while maintaining all circuits EFS greater than 0. Consider the WRG G shown in Fig. 3. Let C G denote the set of all circuits in G, that is, C G = {c 1, c 2, c 3, c 4, c 1 c 2, c 1 c 3, c 2 c 3, c 3 c 4, c 1 c 2 c 3, c 1 c 3 c 4, c 2 c 3 c 4, c 1 c 2 c 3 c 4 }. We wish to determine which part can be shifted to resource r 6 so that the EFS of all circuits in C G remain greater than zero. The parts that can be shifted to resource r 6 are a, b 1 and d, that is, Q s (r 6 ) = {a, b 1, d}. C 0 = C G {c 4 }, C f 0 = {c 1, c 2, c 3, c 3 c 4 } with F c1 = 1, F c2 = 2, F c3 = 2 and F c3 c4 = 1. So, C 0 ={c 3 c 4, c 1 }, applying algorithm 3.1 will find q* = a. Let n* be the state after part a is shifted to resource r 6. It is easy to verify that the EFS of all circuits in state n* remains greater than zero. Note here C 0 is a small subset of C G, which means the algorithm is efficient. The following lemma will prove that in general, the EFS of all circuits in state n* will remain greater than zero as a result of shifting the part q* found by algorithm 3.1. Theorem 3.5. Shifting part q* identified by algorithm 3.1 to resource r will not decrease the EFS of any circuit of C G to zero in state n*. Algorithm 3.1. ================================= 1. C 0 = {c C G : c = (R c, A c ) and r R c } 2. C 0 = {c C f 0 : F c, n0 = 1} 3. i = 1 4. ci Ci 1 5. Let q i Q s (r) such that q i is on c i 6. Let n i be the state after q i is shifted to r 7. If F c, ni > 0 c C0 then go to step Ci = Ci 1 { ci} 9. i = i Let c i be the c with F c, ni = 0 in step Go to step q* = q i 13. n* = n i ============== end ================ Fig. 4. Listing of algorithm 3.1. Proof. First, F c, n* > 0, c C0 by step 7 of the algorithm. Second, we need to show F c, n* > 0, c C f 0. Since F c, n0 > 1, c C f 0 C 0 and q* commits to one arc of c at most, so F c, n* F c, n0 1 > 0. Third, need to show F c, n* > 0, c C 0 C f 0. c is the union of two or more elements of C f 0. Consider two cases: i) q* is on c in state n 0, then it may or may not commit to c in state n*, so F c, n* F c, n0 ; ii) q* is not on c in state n 0, if it does not commit to c, then F c, n* = F c, n0. If it does, then it must commit to the component circuit c i c and c i C f 0, which has F ci, n0 > 1 due to step 7. By Lemma 2.1, F c, n0 > 1 and by corollary 3.1, shifting q* does not affect the order, so F c, n* = F c, n0 1 > 0. Lastly, shifting q* to resource r does not affect any c C G C 0. The major result of this section is given in the following theorem which shows that if all circuits of a WRG G have EFS greater than zero, then G is live. Theorem 3.6 Let C G be the set of all circuits in a non-empty WRG G in state n 0. If F c, n0 > 0, c C G, then G is live. Proof. Since F c, n0 > 0, c C G, then the space of all simple circuits of G must be greater than zero, a free resource r exists in G. Also an enabled part q exists in G, since G is not empty and F c, n0 > 0, c C G. If a series of part propagations or shifts exist which will empty the system, then the system must be live. There are four cases to consider in order to show all possibilities. Case 1. Part q has a free exit. According to theorem 3.2, removing part q from the system will not decrease the EFS of any circuit in G. Therefore, if

7 W. Zhang et al.: Necessary and Sufficient Conditions for Deadlocks in Flexible Manufacturing 223 moving part q out of the system results in state n 1, then F c, n1 > 0, c C G. In the following, assume that part q can be propagated to r, and n 1 is the state after the propagation. Let a 0 be the arc part q commits in state n 0 and a 1 be the arc part q commits in state n 1. Case 2. Resource r is a non-converging resource. According to theorem 3.3, the EFS of any circuit in C G cannot decrease. Therefore, F c, n1 > 0, c C G. In the next two cases, assume that resource r is a converging resource and part q is being shifted onto a circuit in C G. Define C = {c C G : a 0 c and a 1 c}. Case 3. F c, n0 > 1, c C. According to theorem 3.4, shifting part q on any circuit in C will result in F c, n1 > 0, c C G. Case 4. F c, n0 = 1, for some c C G. By theorem 3.5, algorithm 3.1 will identify a part q* that can be shifted to resource r such that F c, n1 > 0, c C G. Applying cases 1, 2, 3 or 4 at each step of the way to empty the system, the EFS of all the circuits in G will remain strictly positive. Therefore, there will always be an empty resource into which a part can be propagated or shifted. Since all the process plans are finite, this process can continue until all parts exit. Example 3.3 Consider the example manufacturing system given in Fig. 3 again. The given state is live by Theorem 3.6. One possible sequence of part propagations that might be used to empty the system is shown in Table 2. The above theorem states that as long as every circuit of the WRG in a given state has EFS greater than 0, the system can be emptied and thus the given state is a live state. Here it is important to note that required is not the actual number of free resource units of a circuit, but the effective free space of the circuit, which takes into account such factors as resource unit committed to the circuit, the order of the circuit and of course the actual number of free resource units of the circuit. And it is the order one knots that contribute to every possible impending deadlock. By identifying order one knots in an early stage, impending deadlocks can be avoided in advance. Thus our result is unique in that it will lead to a new class of deadlock avoidance policies that will avoid both primary deadlocks and impending deadlocks that are arbitrary steps away from a primary one, whereas only second level deadlocks have been studied in the literature. Table 2. Part propagations to empty the system. Part propagation Theorem applied Resulting state a to r [0,0,1,2,0,2,1] a to r [0,3,1,2,0,0,1] d free exit 3.2 [0,3,1,2,0,0,0] b 1 free exit 3.2 [0,3,1,0,0,0,0] b 2 free exit 3.2 [0,3,0,0,0,0,0] a free exit 3.2 [0,0,0,0,0,0,0] c a c 1 r 3 r 1 r 6 b c 2 a r 2 r 4 c 4 c 3 Fig. 5. The system graph for example 3.4. r 5 c b However, the theorem only provides the sufficient conditions for a system state to be live. That is, there may be system states that have a circuit with EFS equal to zero that are live. An example is given in the following. Example 3.4 Consider the system WRG G given in Fig. 5. The system in the given state n has three part a, b and c, all at their first step. Assume the process plans for part a, b and c are r 1 r 2 r 4 r 6 r 5, r 3 r 4 r 6 r 2 r 1 and r 5 r 6 r 2 r 4 r 3, respectively. Then r 2, r 4 and r 6 are all order one knots and F c1 c2 c3 c4, n = 0, theorem 3.6 does not apply. In fact, the system state is live. However, if the process plans are r 1 r 2 r 4 r 3, r 3 r 4 r 6 r 5 and r 5 r 6 r 2 r 1 instead, then G is the same, r 2, r 4 and r 6 are still order one knots and F c1 c2 c3 c4, n = 0, but the state is in deadlock. IV. NECESSARY AND SUFFICIENT CONDITIONS FOR A LIVE STATE In this section, the necessary and sufficient conditions for a system state to be live will be established for a special class of states called the evaluation state. It can be shown that when the system is in an evaluation state, the system will be in deadlock if and only if one of the circuits has EFS equal to zero. However, this cannot be established in the general case, since there is not enough information, as shown in example 3.4, for the two cases both with EFS 0, the state is live in one case, deadlock in the other.

8 224 Asian Journal of Control, Vol. 6, No. 2, June 2004 r 2 a 2 a 1 r 3 r 1 a 3 b 3 c 1 c 2 r 5 r 4 d 1 r 7 b 2 r 6 Definition 4.1 Given a WRG G in state n, a basic circuit of G is always in an evaluation state. Let c be a chained circuit of G and divided into two circuits c 1 and c 2, at any order-one knot k such that c 1 c 2 = k. Then c is in an evaluation state if all order-one knots are empty and for each order-one knot k, two parts q 1 and q 2 exist such that 4.1 Basic circuits Fig. 6. Evaluation state. A circuit c with order zero in state n, O c, n = 0, is called a basic circuit. A simple circuit is a basic circuit, but a basic circuit might not be simple. In example 3.1, the circuit c 1 c 2 is a basic circuit but not a simple circuit. Theorem 4.1 Given a basic circuit c = (R c, A c ) in state n. If F c, n = 0 then c is in deadlock. Proof. F c, n = 0 and O c, n = 0 mean C Rc = M Ac, n, which indicates no resource is free and the system cannot be emptied. From theorem 3.6 and theorem 4.1, if G is a basic circuit, then the EFS of a basic circuit greater than zero is the necessary and sufficient condition for the system state to be live. 4.2 Chained circuits A circuit c is called a chained circuit if it contains one or more order one knots such that c can be decomposed into a set of basic circuits, which intersect at only the order one knots. In example 2.1, c = c 1 c 2 is a chained circuit, which has only one order one knot r 4 and can be decomposed into two basic circuits c 1 and c 2. To conceptualize the need for an evaluation state, let us introduce a third part type d as shown in Fig. 6. Part type a still has process plan p a = r 4 r 1 r 2 r 3 r 4 r 5, type b has p b = r 5 r 6 r 7 r 4 r 1. Then the state may or may not be in deadlock depending on the route of part type d: i) p d = p b, then the state is in deadlock as in example 2.1; ii) however if p d = r 5 r 6 r 7 r 4 r 5, then the state is live. In order to distinguish and to evaluate the two cases, the dynamics of the part crossing through the knot r 4 should be analyzed. In case ii) part d 1 can leave circuit c 2 before part b 2 crosses the knot. In other words, a resource may become free on c 2 before part b 2 must cross the knot. In this case, we say that the circuit c = c 1 c 2 is not in an evaluation state. The method presented earlier cannot determine if deadlock exists by computing the EFS. In case i), part d 1 must cross knot r 4 before any other part on c 2 can leave c 2. In this case, we say that c is in an evaluation state. 1. q 1 must cross from c 1 to c 2 before any other part can leave c 1, and c 2 is in an evaluation state if q 1 is shifted to k, and 2. q 2 must cross from c 2 to c 1 before any other part can leave c 2, and c 1 is in an evaluation state if q 2 is shifted to k. The following lemma will show how the parts are committed when a chained circuit is in an evaluation state. Lemma 4.1 Given a WRG G in state n, a chained circuit c = (R, A) that is in an evaluation has F c, n = 0 if and only if all resources except all order-one knots of c are filled and committed to arcs of c. Proof. First necessity. Let R k = {r: O r, c, n = 1} and R n = R R k. Let A k and A n be the sets of arcs that parts in R k and R n commit, respectively. Since c is in an evaluation state, all order-one knots are empty, so M Ak, n = 0, and capacity of a knot is one, so O c, n = C Rk. From F c, n = 0, we have, K c, n O c, n = 0, that is, C R M A, n C Rk = C Rk M Ak, n + C Rn M An, n C Rk = C Rn M An, n = 0, indicating no free resources exist on c except for the order-one knots. Sufficiency can be proved similarly. Given all resources on c other than the order-one knots are filled and committed to resources on c. We have F c, n = K c, n O c, n = C Rk M Ak, n + C Rn M An, n O c, n. Since c is in an evaluation state, all order-one knots are empty, so M Ak, n = 0, and capacity of a knot is one, so O c, n = C Rk. Then, F c, n = C Rn M An, n. But since all resources in R n are filled and committed to resources on c, then C Rn = M An, n. Therefore, F c, n = 0. Theorem 4.2 Given a WRG G in state n, a chained circuit c that is in an evaluation state, is in deadlock if F c, n = 0. Proof. From Lemma 4.1, only order one knots of c are empty. Let k be an order one knot such that c = c 1 c 2 and c 1 c 2 = k. Let q 1 and q 2 be the first part to leave c 1 and c 2, respectively, q 1, q 2 Q s (k). According to definition 4.1, shifting part q 1 (q 2 ) to k will put circuit c 2 (c 1 ) into an evaluation state. If c 2 (c 1 ) is a basic circuit then F c2, n = 0 and from theorem 4.1, c 2 (c 1 ) is in deadlock. Otherwise, recursive application of this process to c 2 (c 1 ) will eventually produce a basic circuit that is in deadlock. Then by definition 2.3, c is in deadlock.

9 W. Zhang et al.: Necessary and Sufficient Conditions for Deadlocks in Flexible Manufacturing 225 r 6 r 1 a 2 b,d d 1 c Complex circuits d 2 r 5 c 3 a 1 r 2 c 2 r 3 Fig. 7. Complex circuit example. A complex circuit is a circuit that contains one or more order-one knots but is not a chained circuit. A complex circuit can be decomposed into two paths, one is a chained circuit and the other is called an auxiliary circuit. The intersection of the auxiliary circuit and the chained circuit must contain one or more order-one knots of the chained circuit. A bypass path is the portion of the auxiliary circuit that does not intersect the chained circuit. And the first arc on the bypass path is a bypass arc. Example 4.1 Consider the system shown in Fig. 7 where all resources have capacity one. Suppose the process plans for part a, b and d are r 1 r 2 r 3 r 4, r 4 r 2 r 6 r 1 and r 3 r 5 r 6 r 1, respectively. The system WRG G consists of three simple circuits: c 1 = r 1 r 2 r 6 r 1, c 2 = r 2 r 3 r 4 r 2 and c 3 = r 2 r 3 r 5 r 6 r 1 r 2. The order of c 1 c 2 is one, so G is not a basic circuit. It is not a chained circuit either, since the intersection (c 1 c 2 ) c 3 contains more than knot r 2. This complex circuit can be decomposed into a chained circuit c 1 c 2 and an auxiliary circuit c 3. The path r 3 r 5 r 6 is the bypass path and the arc from r 3 to r 5 is the bypass arc. Definition 4.2 A complex circuit in a WRG G is in an evaluation state if its bypass arcs are not committed and the decomposed chained circuit is in an evaluation state. Definition 4.3 A WRG G is in an evaluation state if all circuits in G are in an evaluation state. Theorem 4.3 Given a WRG G in state n, a complex circuit c that is in an evaluation state, is in deadlock if any chained circuit c* c has F c*, n = 0. Proof. According to theorem 4.2, c* is in deadlock. Then by definition 2.3, circuit c is in deadlock. Theorem 4.4 Given a WRG G in state n, if any circuit c is in an evaluation state and F c, n = 0, then G is in deadlock. Proof. The circuit c can be a basic circuit, a chained circuit or a complex circuit. Applying theorem 4.1, theorem 4.2 or theorem 4.3, respectively will show that c is in deadlock. Then by definition 2.3, G is in deadlock. b r 4 a The system in Fig. 7 is in an evaluation state. This is because part a 1 in resource r 3 does not commit to the bypass arc and the chained circuit c 1 c 2 is in an evaluation state by definition 4.1. The space of the chained circuit c 1 c 2 is zero. Obviously, the system is in deadlock. Theorem 4.5 Let C G be the set of circuits in a WRG G in state n. If G is in an evaluation state, then G is live if and only if F c, n > 0, c C G. Proof. Applying theorem 3.6 and the contra positive of theorem 4.4 proves the result. Example 4.2 Consider the system WRG G given in Fig. 5. G is a chained circuit, r 2, r 4 and r 6 are all order one knots. However, G is not in an evaluation state, since although part a must cross knot r 2 from c 1 to c 2 c 3 c 4 but part c can leave c 2 c 3 c 4 before part b must cross knot r 2 to c 1. Then theorem 4.5 does not apply, and with F c1 c2 c3 c4, n = 0, theorem 3.6 does not apply either. In fact, the system state is live. Now consider the second set of process plans for part a, b and c, r 1 r 2 r 4 r 3, r 3 r 4 r 6 r 5 and r 5 r 6 r 2 r 1, respectively. Then G is still a chained circuit, r 2, r 4 and r 6 are all order one knots with c 1 c 2 c 3 c 4, c 2 c 1 c 3 c 4 and c 3 c 1 c 2 c 4. G is in an evaluation state, since part a must cross knot r 2 from c 1 to c 2 c 3 c 4, part c must cross knot r 2 from c 2 c 3 c 4 to c 1 before part b can leave c 2 c 3 c 4. The EFS of every circuit in G is greater than zero except for G itself, that is, F c1 c2 c3 c4, n = 0. Apply theorem 4.5, G is in deadlock. As a matter of fact, the system cannot be emptied. V. DEADLOCK AVOIDANCE POLICIES Based on the sufficient conditions established earlier, two deadlock avoidance policies will be developed, which can be applied to process controllers of actual manufacturing systems to detect and avoid deadlocks. The difference of the two policies is they evaluate order of a knot or circuit differently. Policy I uses a lazy order evaluation and policy II uses an incremental order evaluation. Lazy order evaluation. Given m circuits c 1, c 2,, c m and c 1 c 2 c m = k is a knot. The order of k is calculated as one if there exist i > 1 circuits, say c 1, c 2,, c i, such that there exist a type of part that needs to visit c 1 then c 2, a type of part that needs to visit c 2 then c 3,, and a type of part that needs to visit c i then c 1 ; calculated as zero, otherwise. Lazy order evaluation determines the order by statically establishing cyclic connectedness among a

10 226 Asian Journal of Control, Vol. 6, No. 2, June 2004 group of circuits joined by a knot so that orders can be calculated offline. This evaluation implies as long as it s possible to have cyclic connectedness in the future evolution of the system, the order is set to one. Policy I. Given the WRG G of a system starting from empty of parts. Let C G be the set of all circuits of G and the EFS of each circuit be calculated based on lazy order evaluation. Then, a part move is accepted only if after the part move, the EFS of all affected circuits remain positive (Theorem 3.6). Incremental order evaluation. Given m circuits c 1, c 2,, c m and c 1 c 2 c m = k is a knot. The order of k is initialized to zero and incrementally updated using definition 3.2 only if i) a part is loaded into the system and its process plan has k; ii) a part is propagated to k. According to definition 3.1, loading a part may cause two circuits to become connected and propagating a part to a knot may cause two circuits to become disconnected. Then only when a part is loaded or propagated to a knot, the order of the affected circuits needs to be updated. Policy II. Policy II is policy I, except that the EFS calculation is based on incremental order evaluation. Both policies need to calculate C G, which might be expensive but can be done offline. An efficient string manipulation procedure to compute circuits was presented in [11]. [2,4] and [5] have similar calculation to find all circuits or siphons. Assume C G is given for a system. Let K be the set of knots of G, L i be the length of process plan p i, i =1 ~ M, where M be the number of process plans, and L = Σ(L i, i = 1 ~ M). In general, it can be assumed that K << L. Policy I can be computed in linear time (O( C G )), since orders can be established offline while calculating C G. Policy II dynamically calculates orders of knots and captures more dynamics of the system, thus is more permissive but need extra online calculation for the incremental update of orders of circuits. However, the incremental order calculation can be done in polynomial time. Since the connectedness of two circuits c 1 and c 2 with c 1 c 2 = k can be established by examining if arc r 1 k r 2 (assume r 1 on c 1 and r 2 on c 2 ) is contained in the process plan of all parts in the system, but for all parts of the same type, this test needs only be done once and the number of such tests is limited by the number of process plans. There are at most 2 C G such pairs of circuits. The computation needed to update connectedness among all circuits is then in the 2 G order of O( C L). The cyclic connectedness (thus the order) can then be established by checking for connectedness among m circuits for all knots and the computation is trivial compared to update connectedness. Then policy II can be computed in polynomial time. Example 5.1. Consider the system given in Fig. 3. With lazy order evaluation, the order of both knot r 5 and r 6 is always one. With incremental order evaluation, after part d is propagated to r 5, the order of r 5 becomes zero since c 4 is no longer connected to c 3 although c 3 is still connected to c 4. Simulation results show that policy I allows 455 states out of 621 live states (state space size is 879), while policy II allows 563. Policy I has a percentage permissiveness 455/621 = 73.3% and policy II has 563/621 = 90.7%. More simulation results on previous examples are, Example 2.1 Both policies have 99.2%. Example 3.1 Both policies have 100%. Example 3.2 Policy I has 73.3% and policy II has 90.7%. Example 4.1 Policy I has 93.5% and policy II has 99.4%. Example 4.2 Case 1: Policy I has 49.8% and policy II has 89.4%. Case 2: Policy I has 50.2% and policy II has 91.7%. In general, policy II allows more live states than [2] and [4]. Essentially, this is because the order evaluation captures more parts flow dynamics, especially when there exist multiple knots. Method of [2] allows more states than [4]. However, even with the one step look-ahead controller, method [2] still cannot guarantee to avoid all deadlocks. Also, policy II performs better than [5] when higher than second level deadlock exists. VI. CONCLUSIONS Circuits and knots in the WRG of a manufacturing system are the rudimentary causes of deadlocks. Especially, order one knots are essential to impending deadlocks a type of deadlock more difficult to detect (The impending deadlock one step away from primary deadlock is called second level deadlock [5]). The order of a knot is thus defined and used to calculate the effective free space on a circuit. Based on the space calculation, sufficient conditions are precisely quantified for a system to be live. Necessary and sufficient conditions for liveness are quantified only for a special class of states, called the evaluation states. This is because when a system is not in an evaluation state, in most cases, order one knots are filled with parts and thus parts flow dynamics are hidden from the space calculation of some circuits in the WRG. Two deadlock avoidance policies are established

11 W. Zhang et al.: Necessary and Sufficient Conditions for Deadlocks in Flexible Manufacturing 227 on the sufficient conditions. Several examples are simulated with the two policies applied. Simulation results show that policy II is very promising and provides more live states than results given in [8] which is the same as or better than some famous methods in the literature. Development of the algorithms for connectedness check, order calculation, etc. and their computational complexity analysis are quite involved. Results have been published in [15] and as indicated by [15], the computational complexity for connectedness check is in the order of O(m 2 2 C R P q ), the order calculation is in the order of O(C R m 2 ), where m is the number of simple circuits, C R is number of resources and P q is the length of longest process plan. However, application of the necessary conditions has one major difficulty computation of the evaluation state. Developing an efficient algorithm to compute the evaluation state thus improving our deadlock avoidance policies will be one of our future research topics. REFERENCES 1. Banaszak, Z. and B. H. Krogh, Deadlock Avoidance in Flexible Manufacturing Systems with Concurrently Competing Process Flows, IEEE Trans. Rob. Autom., Vol. 6, No. 6, pp (1990). 2. Barkaoui, K. and I. B. Abdallah, Deadlock Avoidance in FMS Based on Structural Theory of Petri Nets, IEEE Symp. Emerging Technol. Factory Autom., pp , Paris (1995). 3. Cho, H., T. K. Kumaran, R.A. Wysk, Graph-Theoretic Deadlock Detection and Resolution for Flexible Manufacturing Systems, IEEE Trans. Rob. Autom., Vol. 11, No. 3, pp (1995). 4. Ezpeleta, J., J. Colom, J. Martinez, A Petri Net Based Deadlock Prevention policy for Flexible Manufacturing Systems, IEEE Trans. Rob. Autom., Vol. 11, No. 2, pp (1995). 5. Fanti, M. P., B. Maione, S. Mascolo, and B. Turchiano, Event-Based Feedback Control for Deadlock Avoidance in Flexible Production Systems, IEEE Trans. Rob. Autom., Vol. 13, pp (1997). 6. Guro, D., H. Muller, Toward an Optimal Deadlock Avoidance Algorithm for Flexible Manufacturing Systems, Pro. IEEE Int. Conf. Syst. Man Cybern., Vancouver, pp (1995). 7. Hsieh, F. and S. Chang, Dispatching-Driven Deadlock Avoidance Controller Synthesis for Flexible Manufacturing Systems, IEEE Trans. Rob. Autom., Vol. 10, No. 2, pp , (1994). 8. Judd, Robert P., and Faiz, Tariq Nadeem, Deadlock Detection and Avoidance for a Class of Manufacturing Systems, Proc. Amer. Contr. Conf., Washington, pp (1995). 9. Lipset, R., P. Deering, and R. P. Judd, Necessary and Sufficient Conditions for Deadlock in Manufacturing Systems, Proc. Amer. Contr. Conf., Vol. 2, pp , Albuquerque (1997). 10. Reveliotis, S. A. and P. M. Ferreira, Deadlock Avoidance Policies for Automated Manufacturing Cells, IEEE Trans. Rob. Autom., Vol. 12, No. 7, pp (1996). 11. Wysk R., N. Yang, and S. Joshi,, Detection of Deadlocks in Flexible Manufacturing Systems, IEEE Trans. Rob. Autom., Vol. 7, No. 6, pp (1991). 12. Viswanadham, N., Y. Narahari, T. Johnson, Deadlock Prevention and Deadlock Avoidance in Flexible Manufacturing Systems Using Petri Net Models, IEEE Trans. Rob. Autom., Vol. 6, No. 6, pp (1990). 13. Xing, K., Bao-Sheng, Hu, and Chen, Hao-Hun, Deadlock Avoidance Policy for Petri-Net Modeling of Flexible Manufacturing Systems with Shared Resources, IEEE Trans. Automat. Contr., Vol. 41, No. 2 (1996). 14. Zhou, M., and F. DiCesare, Parallel and Sequential Mutual Exclusion for Petri Net Modeling of Manufacturing Systems with Shared Resources, IEEE Trans. Rob. Autom., Vol. 7, No. 4, pp (1992). 15. Wenle Zhang, Robert P. Judd and Paul Deering, Evaluating Order Of Circuits For Deadlock Avoidance In A Flexible Manufacturing System, Proc. Amer. Contr. Conf., Dever, pp (2003). 16. Gurel A., S. Bogdan and F. L. Lewis, Matrix Approach to Deadlock-Free Dispatching in Multi-Class Finite Buffer Flowlines, IEEE Trans. Automat. Contr., Vol. 45, No. 11, pp (2000). Wenle Zhang received his B.S. and M.S. from Shandong Univ. of Sci. and Tech. in 1983 and Shanghai Univ. of Sci. and Tech. in 1986, respectively. Then He worked as an instructor in the dept. of computer engineering at Shanghai Univ. of Sci. and Tech. until He received his Ph.D. in Electrical Engineering from Ohio University in After received his Ph.D., Dr. Zhang worked for Lucent Technologies as a software engineer until March Prior to pursuing his Ph.D. at Ohio University, he was employed with Rockwell Automation, a famous industrial controls supplier, as a control engineer for more than 5 years. He has experience in PLC application, industrial control networking, control software development. Since spring of 2001, Dr. Zhang has been an assis-

12 228 Asian Journal of Control, Vol. 6, No. 2, June 2004 tant professor in the School of Electrical Engineering and Computer Science at Ohio University. Dr. Zhang's current research interests include manufacturing system, industrial controls, distributed computing and object oriented programming. Dr. Judd has over twenty years of experience as an educator, researcher and consultant in system simulation, discrete event controls, and systems integration. Dr. Judd has received over thirty research grants totaling over $3,500,000. His funding has come from both industrial and governmental sources. He is the author or co-author of over a hundred published papers in journals and conferences. He also wrote a book chapter devoted to integrating manufacturing design tools and edited a special issue of the International Journal of Computer Integrated Manufacturing dedicated to intelligent manufacturing systems. Dr. Judd holds a patent on simulation software integration. Paul Deering received his BSEE and M.S. in Mathematics and Computer Science from Ohio University in 1984 and 1988 respectively. He then became employed by the Russ College of Engineering and Technology as an Instructor and Computer Specialist. In 2000 he received his Ph.D. in Integrated Engineering from Ohio University. Dr. Deering is still employed by the Russ College of Engineering and Technology and serves as an Adjunct Professor for the school of Electrical Engineering and Industrial Technology. Dr. Deering s research interest includes manufacturing and computer systems.