Assertions and Measurements for Mixed-Signal Simulation
|
|
- Carmella Harrell
- 5 years ago
- Views:
Transcription
1 Assertions and Measurements for Mixed-Signal Simulation PhD Thesis Thomas Ferrère VERIMAG, University of Grenoble (directeur: Oded Maler) Mentor Graphics Corporation (co-encadrant: Ernst Christen) October 28, 2016
2 Cyber-Physical Systems Both discrete and continuous modes of operation Example: a cell phone A design: A bug: (courtesy of Samsung and AppleInsider) Verification is needed 1 / 40
3 Cyber-Physical Systems Both discrete and continuous modes of operation Example: a cell phone A design: A bug: (courtesy of Samsung and AppleInsider) Verification is needed 1 / 40
4 Cyber-Physical Systems Both discrete and continuous modes of operation Example: a cell phone A design: A bug: (courtesy of Samsung and AppleInsider) Verification is needed 1 / 40
5 Cyber-Physical Systems Both discrete and continuous modes of operation Example: a cell phone A design: A bug: (courtesy of Samsung and AppleInsider) Verification is needed 1 / 40
6 Cyber-Physical Systems Both discrete and continuous modes of operation Example: a cell phone A design: A bug: (courtesy of Samsung and AppleInsider) Verification is needed 1 / 40
7 Mixed-Signal Simulation Integrated Circuits Modeling Digital: event-driven p q = 0 q = 1 p (courtesy of ST Microelectronics) Implement both analog and digital electronics Design uses HDL and net lists at several stages Analog: algebraic differential equations ( f p x, dx ) = 0 dt Mixed-Signal: analog events (x > 2.0) and digital control f q 2 / 40
8 Mixed-Signal Simulation Integrated Circuits Modeling Digital: event-driven p q = 0 q = 1 p (courtesy of ST Microelectronics) Implement both analog and digital electronics Design uses HDL and net lists at several stages Analog: algebraic differential equations ( f p x, dx ) = 0 dt Mixed-Signal: analog events (x > 2.0) and digital control f q 2 / 40
9 Simulation-Based Verification During the design stage run multiple simulations Each simulation produces a trace Records evolution of quantities over time Real-valued and Boolean signals Monitoring: each traced need to be analysed Evaluate requirements: correctness, robusteness, diagnostics In general measuring some performance Automation of the monitoring activity: Additional observer blocks Declarative property or measurement languages 3 / 40
10 Declarative Languages in Industry Assertions Digital domain Languages psl and sva built using two layers: regular expression temporal logic Discrete time interpretation Measurements Analog domain extract commands: signal processing, offline meas commands: event-driven, online 4 / 40
11 Research on Realtime Properties Problem: mixed-signal characterized by a synchronous interaction Solution: use continous-time representation Metric Temporal Logic (Koymans, 1990) Signal Temporal Logic for real-valued signals (Maler and Nickovic, 2004) Quantitative semantics for robustness estimate (Fainekos and Pappas, 2009) Timed Regular Expressions (Asarin, Caspi and Maler, 1998) 5 / 40
12 Limitations of Existing Tools and Techniques Digital assertions bound to precision of sampling clock Realtime properties monitoring not implemented Robustness computation is not efficient No easy diagnostic of temporal logic properties failure Measurements not controllable by sequential conditions No analog measures in a digital context 6 / 40
13 Outline 1. Preliminaries 2. Robustness Computation 3. Diagnostics 4. Regular Expressions Monitoring 5. Pattern-Based Measurements 6. Analog Measures in Digital Environment 7. Conclusion 7 / 40
14 Outline 1. Preliminaries 2. Robustness Computation 3. Diagnostics 4. Regular Expressions Monitoring 5. Pattern-Based Measurements 6. Analog Measures in Digital Environment 7. Conclusion 7 / 40
15 Signal Temporal Logic Propositions p: Boolean variables q, conditions x c, and events p Temporal operators: Until: ϕ U I ψ Eventually: I ψ = U I ψ Always: I ψ = I ψ Formulas can be written with [a,b] and U only Example: stabilization property ϕ = ( q [0,5] [0,5] x 0.2) x q t 0 t t t 8 / 40
16 Signal Temporal Logic Propositions p: Boolean variables q, conditions x c, and events p Temporal operators: Until: ϕ U I ψ Eventually: I ψ = U I ψ Always: I ψ = I ψ Formulas can be written with [a,b] and U only Example: stabilization property ϕ = ( q [0,5] [0,5] x 0.2) x q t 0 t t t 8 / 40
17 Monitoring Offline approach (Maler and Nickovic, 2004): for each subformula ϕ compute set of times [ϕ] w where ϕ holds according to w Definition (Satisfaction Set) [p] w = {t : p w (t) = 1} [ [a,b] ϕ ] w = [ϕ] w [a, b] [ϕ ψ] w = [ϕ] w [ψ] w [ ϕ] w = [ϕ] w 9 / 40
18 Computation Theorem For any ϕ and w with finite variability, [ϕ] w is finite union of intervals Eventually operator: ϕ T [a,b] ϕ T [a, b] t Worst-case complexity O( ϕ ) 2 w 10 / 40
19 Example x q x 0.2 q [0,5] x 0.2 [0,5] [0,5] x 0.2 q [0,5] [0,5] x 0.2 ( q [0,5] [0,5] x 0.2) 0 5 t 11 / 40
20 Example x q x 0.2 q [0,5] x 0.2 [0,5] [0,5] x 0.2 q [0,5] [0,5] x 0.2 ( q [0,5] [0,5] x 0.2) 0 5 t 11 / 40
21 Example x q x 0.2 q [0,5] x 0.2 [0,5] [0,5] x 0.2 q [0,5] [0,5] x 0.2 ( q [0,5] [0,5] x 0.2) 0 5 t 11 / 40
22 Example x q x 0.2 q [0,5] x 0.2 [0,5] [0,5] x 0.2 q [0,5] [0,5] x 0.2 ( q [0,5] [0,5] x 0.2) 0 5 t 11 / 40
23 Example x q x 0.2 q [0,5] x 0.2 [0,5] [0,5] x 0.2 q [0,5] [0,5] x 0.2 ( q [0,5] [0,5] x 0.2) 0 5 t 11 / 40
24 Example x q x 0.2 q [0,5] x 0.2 [0,5] [0,5] x 0.2 q [0,5] [0,5] x 0.2 ( q [0,5] [0,5] x 0.2) 0 5 t 11 / 40
25 Example x q x 0.2 q [0,5] x 0.2 [0,5] [0,5] x 0.2 q [0,5] [0,5] x 0.2 ( q [0,5] [0,5] x 0.2) 0 5 t 11 / 40
26 Quantitative Semantics Robustness value ϕ w indicates how strongly ϕ is satisfied / violated by w Positive if satisfied / negative if violated Magnitude = conservative estimate of distance to satisfaction / violation boundary Definition (Robustness Signal) x c w = c x w [a,b] ϕ w = t sup t [t+a,t+b] ϕ w = ϕ w ϕ w (t ) ϕ ψ w = max{ ϕ w, ψ w } 12 / 40
27 Outline 1. Preliminaries 2. Robustness Computation 3. Diagnostics 4. Regular Expressions Monitoring 5. Pattern-Based Measurements 6. Analog Measures in Digital Environment 7. Conclusion 12 / 40
28 Principle Theorem For any ϕ and w piecewise linear, ϕ w is piecewise linear Until rewrite rules preserve the robustness value Timed eventually computed using optimal streaming algorithm of (Lemire, 2006) adapted to variable-step sampling 13 / 40
29 Eventually Computation Problem: compute g(t) = sup t [t+a,t+b] f(t ) Solution: take maximum of f at t + a, t + b and sampling points inside (a, b) f i 2 t + a t + b 14 / 40
30 Eventually Computation Problem: compute g(t) = sup t [t+a,t+b] f(t ) Solution: take maximum of f at t + a, t + b and sampling points inside (a, b) f i 1 i 2 i 3 i 4 t + a t + b 14 / 40
31 Eventually Computation Problem: compute g(t) = sup t [t+a,t+b] f(t ) Solution: take maximum of f at t + a, t + b and sampling points inside (a, b) f i 1 i 2 i 3 i 5 i 4 t + a t + b 14 / 40
32 Eventually Computation Problem: compute g(t) = sup t [t+a,t+b] f(t ) Solution: take maximum of f at t + a, t + b and sampling points inside (a, b) f i 1 i 2 i i 5 3 t + a t + b 14 / 40
33 Eventually Computation Problem: compute g(t) = sup t [t+a,t+b] f(t ) Solution: take maximum of f at t + a, t + b and sampling points inside (a, b) f i 1 i 2 i 5 t + a t + b 14 / 40
34 Eventually Computation Problem: compute g(t) = sup t [t+a,t+b] f(t ) Solution: take maximum of f at t + a, t + b and sampling points inside (a, b) f i 1 i 2 i 5 t + a t + b 14 / 40
35 Eventually Computation Problem: compute g(t) = sup t [t+a,t+b] f(t ) Solution: take maximum of f at t + a, t + b and sampling points inside (a, b) f i 2 i 5 t + a t + b 14 / 40
36 Example x 0.2 x [0,5] x [0,5] [0,5] x t 15 / 40
37 Evaluation Worst-case complexity in 2 O( ϕ ) w Implementation benchmarked with random signals: w [1,2] [1,11] [1,21] [1,31] Cost of computing [a,b] independent from b a Improves on related works by several orders of magnitude 16 / 40
38 Publications Donzé, Ferrère, and Maler. Efficient robust monitoring for STL. In Computer Aided Verification (CAV), / 40
39 Outline 1. Preliminaries 2. Robustness Computation 3. Diagnostics 4. Regular Expressions Monitoring 5. Pattern-Based Measurements 6. Analog Measures in Digital Environment 7. Conclusion 16 / 40
40 Motivation Find small segment of w sufficient to cause violation of ϕ Example: violation of ( q [0,5] [0,5] x 0.2) x q 0 Sub-traces = temporal implicants 5 t 17 / 40
41 Motivation Find small segment of w sufficient to cause violation of ϕ Example: violation of ( q [0,5] [0,5] x 0.2) x q 0 Sub-traces = temporal implicants 5 t 17 / 40
42 Propositional Implicants Implicant of ϕ partial valuation whose extensions satisfy ϕ Definition Implicant of ϕ = term γ such that γ ϕ Prime implicant of ϕ = implicant of ϕ maximal relative to For diagnostic: implicant compatible with observed values v Problem (Diagnostic) For given ϕ and v, find γ ϕ such that v = γ 18 / 40
43 Propositional Implicants Implicant of ϕ partial valuation whose extensions satisfy ϕ Definition Implicant of ϕ = term γ such that γ ϕ Prime implicant of ϕ = implicant of ϕ maximal relative to For diagnostic: implicant compatible with observed values v Problem (Diagnostic) For given ϕ and v, find γ ϕ such that v = γ 18 / 40
44 Temporal Implicants Temporal implicant of ϕ partial trace whose extensions satisfy ϕ Syntactical considerations: Terms with conjunctions t T θ(t) over intervals Limit values handled by non-standard reals t +, t Example: p(t) [1,2] p t [0.5,3.0] Theorem Every realtime property ϕ has a prime implicant Relies on boundedness of the time domain and non-standard extension 19 / 40
45 Computation for Signal Temporal Logic Diagnostic operators E, F such that: Explanation E(ϕ) ϕ Falsification F (ϕ) ϕ Definition (Diagnostic Signal) E(p) = p E( ϕ) = F (ϕ) E( [a,b] ϕ) = t E(ϕ)(ξ(t)) F ( [a,b] ϕ) = t F (ϕ)(t ) with selection function ξ such that ξ(t) [t + a, t + b] t [t+a,t+b] 20 / 40
46 Selection Function Compute ξ over some interval T where [a,b] ϕ holds: Current time t is at start of T Select last witness s of ϕ to account for [a,b] ϕ at t Remove from T the part R that has been accounted for ϕ [a,b] ϕ t already covered T 21 / 40
47 Selection Function Compute ξ over some interval T where [a,b] ϕ holds: Current time t is at start of T Select last witness s of ϕ to account for [a,b] ϕ at t Remove from T the part R that has been accounted for [t + a, t + b] ϕ [a,b] ϕ t already covered T 21 / 40
48 Selection Function Compute ξ over some interval T where [a,b] ϕ holds: Current time t is at start of T Select last witness s of ϕ to account for [a,b] ϕ at t Remove from T the part R that has been accounted for [t + a, t + b] ϕ s [a,b] ϕ t already covered T 21 / 40
49 Selection Function Compute ξ over some interval T where [a,b] ϕ holds: Current time t is at start of T Select last witness s of ϕ to account for [a,b] ϕ at t Remove from T the part R that has been accounted for ϕ s [a,b] ϕ t already covered R T 21 / 40
50 Selection Function Compute ξ over some interval T where [a,b] ϕ holds: Current time t is at start of T Select last witness s of ϕ to account for [a,b] ϕ at t Remove from T the part R that has been accounted for ϕ s [a,b] ϕ t already covered R T 21 / 40
51 Overview Example: x 0.2 q [0,5] x 0.2 [0,5] [0,5] x 0.2 q [0,5] [0,5] x 0.2 ( q [0,5] [0,5] x 0.2) 0 5 t Worst-case complexity O( ϕ ) 2 w 22 / 40
52 Overview Example: x 0.2 q [0,5] x 0.2 [0,5] [0,5] x 0.2 q [0,5] [0,5] x 0.2 ( q [0,5] [0,5] x 0.2) 0 5 t Worst-case complexity O( ϕ ) 2 w 22 / 40
53 Overview Example: x 0.2 q [0,5] x 0.2 [0,5] [0,5] x 0.2 q [0,5] [0,5] x 0.2 ( q [0,5] [0,5] x 0.2) 0 5 t Worst-case complexity O( ϕ ) 2 w 22 / 40
54 Overview Example: x 0.2 q [0,5] x 0.2 [0,5] [0,5] x 0.2 q [0,5] [0,5] x 0.2 ( q [0,5] [0,5] x 0.2) 0 5 t Worst-case complexity O( ϕ ) 2 w 22 / 40
55 Overview Example: x 0.2 q [0,5] x 0.2 [0,5] [0,5] x 0.2 q [0,5] [0,5] x 0.2 ( q [0,5] [0,5] x 0.2) 0 5 t Worst-case complexity O( ϕ ) 2 w 22 / 40
56 Overview Example: x 0.2 q [0,5] x 0.2 [0,5] [0,5] x 0.2 q [0,5] [0,5] x 0.2 ( q [0,5] [0,5] x 0.2) 0 5 t Worst-case complexity O( ϕ ) 2 w 22 / 40
57 Publications Ferrère, Maler, and Nickovic. Trace diagnostics using temporal implicants. In Automated Technology for Verification and Analysis (ATVA), / 40
58 Outline 1. Preliminaries 2. Robustness Computation 3. Diagnostics 4. Regular Expressions Monitoring 5. Pattern-Based Measurements 6. Analog Measures in Digital Environment 7. Conclusion 22 / 40
59 Signal Regular Expressions Propositions p: Boolean variables q, threshold conditions x c Atomic expressions: holding p, events p Concatenation: ϕ ψ Kleene star: ϕ Duration restriction: ϕ I 23 / 40
60 Example Pulse pattern: ψ = r q p q [5,6] r p = (x 4.0) x q = (4.0 < x 7.0) r = (x > 7.0) r q p q r t [5, 6] 24 / 40
61 Monitoring For any w expression ϕ defines a set of segments (t, t ) such that w[t, t ] matches ϕ Offline approach: for all subexpressions ϕ compute the complete set of matches [ϕ] w of ϕ relative to w Definition (Match Set) [ p ] w = {(t, t ) : t < t < t p w (t ) = 1} [ ϕ I ] w = {(t, t ) : t t I} [ϕ] w [ϕ ψ] w = [ϕ] w [ψ] w [ϕ ψ] w = [ϕ] w [ψ] w [ϕ ψ] w = [ϕ] w [ψ] w [ϕ ] w = i 0 [ ϕ i ] w 25 / 40
62 Match Set Representation A zone = convex set with horizontal, vertical and diagonal boundaries Represents a set of signal segments t Theorem For any ϕ and w with finite variability, [ϕ] w is a finite union of zones t 26 / 40
63 Match Set Representation A zone = convex set with horizontal, vertical and diagonal boundaries Represents a set of signal segments t t p t, t Theorem For any ϕ and w with finite variability, [ϕ] w is a finite union of zones 26 / 40
64 Match Set Representation A zone = convex set with horizontal, vertical and diagonal boundaries Represents a set of signal segments t p t s s t, t Theorem For any ϕ and w with finite variability, [ϕ] w is a finite union of zones 26 / 40
65 Match Set Representation A zone = convex set with horizontal, vertical and diagonal boundaries Represents a set of signal segments t p t s s t, t Theorem For any ϕ and w with finite variability, [ϕ] w is a finite union of zones 26 / 40
66 Example p [2,4] q [1,2] t Match set of p Match set of p [2,4] Match set of q [1,2] Match set of p [2,4] q [1,2] p t q t, t 27 / 40
67 Example p [2,4] q [1,2] t Match set of p Match set of p [2,4] Match set of q [1,2] Match set of p [2,4] q [1,2] p t q t, t 27 / 40
68 Example p [2,4] q [1,2] t Match set of p Match set of p [2,4] Match set of q [1,2] Match set of p [2,4] q [1,2] p t q s s t, t 27 / 40
69 Example p [2,4] q [1,2] t Match set of p Match set of p [2,4] Match set of q [1,2] Match set of p [2,4] q [1,2] p t q t, t 27 / 40
70 Example p [2,4] q [1,2] t Match set of p Match set of p [2,4] Match set of q [1,2] Match set of p [2,4] q [1,2] p t q t, t 27 / 40
71 Example p [2,4] q [1,2] t Match set of p Match set of p [2,4] Match set of q [1,2] Match set of p [2,4] q [1,2] p t q t, t 27 / 40
72 Example p [2,4] q [1,2] t Match set of p Match set of p [2,4] Match set of q [1,2] Match set of p [2,4] q [1,2] p t q t, t 27 / 40
73 Example p [2,4] q [1,2] t Match set of p Match set of p [2,4] Match set of q [1,2] Match set of p [2,4] q [1,2] p t q t, t 27 / 40
74 Example p [2,4] q [1,2] t Match set of p Match set of p [2,4] Match set of q [1,2] Match set of p [2,4] q [1,2] p t q s s s t, t 27 / 40
75 Kleene Star On bounded traces w the sequence n i=0 ϕi converges to a fix-point in finitely many steps Assume w can be split in m constant segments v of length less that 1 Over each segment either [ϕ] v = [ ] v or [ϕ] v = [ ] v Lemma [ϕ n ] w [ ϕ n 1] w for any n > 2m + 1 Compute n i=0 ϕi by squaring: ɛ, ϕ, ϕ 2, ϕ 4,..., ϕ 2k up to k > log(2m + 1) 28 / 40
76 Evaluation Worst-case complexity: w O( ϕ ) without star Implementation using DBM for efficient zones computation Benchmarked for with randomized traces: ϕ = ( p p [0,10] ) ( q q [0,10] ) [80, ] w [ϕ] w time Observed performance linear in w 29 / 40
77 Publications Ulus, Ferrère, Asarin, and Maler. Timed pattern matching. In Formal Modeling and Analysis of Timed Systems (FORMATS), Ulus, Ferrère, Asarin, and Maler. Online timed pattern matching using derivatives In Tools and Algorithms for the Construction and Analysis of Systems (TACAS), / 40
78 Outline 1. Preliminaries 2. Robustness Computation 3. Diagnostics 4. Regular Expressions Monitoring 5. Pattern-Based Measurements 6. Analog Measures in Digital Environment 7. Conclusion 29 / 40
79 Measurement Language Motivation: automate the extraction of mixed-signal measures Signal Regular Expressions control when the measure takes place Measure: aggregating operator duration, min, max, and average Example: average( (x > 1.0) (x > 1.0) (x > 1.0)) measures average value of x on high portions 30 / 40
80 Conditionals and Events Construct expressions delimited by events conditional operators:?ϕ begins a match of ϕ!ϕ ends a match of ϕ event-bounded expressions ψ: event p, p conditional event ψ?, ψ! sequence ψ ϕ ψ Theorem For any w and ψ event-bounded, [ϕ] ψ is finite 31 / 40
81 Case Study: Distributed System Interface DSI3 is a protocol for electronics in automotive industry Based on pulse communication Requirements about magnitude of signals and timing of events Implementation: behavioral model Controler i Sensor R e(t) v a(t) C 32 / 40
82 Timing Requirement x r r q p q ψ r ψ? ψ t [5, 6] time between consecutive pulses 33 / 40
83 Results Pulse description: ψ = r q p q [5,6] r Measure expression: Computation time cost: ϕ = duration(ψ r ψ?) w quantize match extract total / 40
84 Publications Ferrère, Maler, Nickovic, and Ulus. Measuring with timed patterns. In Computer Aided Verification (CAV), / 40
85 Outline 1. Preliminaries 2. Robustness Computation 3. Diagnostics 4. Regular Expressions Monitoring 5. Pattern-Based Measurements 6. Analog Measures in Digital Environment 7. Conclusion 34 / 40
86 Analog Measurements and Digital Testbench Simulator-implemented measures provide guarantees: accuracy reproducible Unfortunately only accessible in analog environment Digital testbench enables structured verification assertion tracking coverage indicators... Mixed-signal verification often done with user-defined monitors 35 / 40
87 Measurement Tasks We propose new measurements functions as system tasks Input: (x, p), output: (y, q) task µ (x, p, y, q, e, r) Control: enable event e and reset event r Accessed in a variety of context: module, class, etc. Prototype implementation using VPI with functions: initialize µ, update µ, status µ, and evaluate µ 36 / 40
88 Phase Locked Loop Digital testbench using the Universal Verification Methodology: Measure relative jitter online, locking time and enforce safe operating area of current through VDD Computation time < 1s for measurements, 300s for simulation 37 / 40
89 Outline 1. Preliminaries 2. Robustness Computation 3. Diagnostics 4. Regular Expressions Monitoring 5. Pattern-Based Measurements 6. Analog Measures in Digital Environment 7. Conclusion 37 / 40
90 Contributions Diagnostic procedure for realtime assertions Efficient algorithms for robustness computation Monitoring of regular expressions Pattern-based measurements Bring practice of analog and digital verification closer 38 / 40
91 Publications 1. Donzé, Ferrère, and Maler. Efficient robust monitoring for STL. In Computer Aided Verification (CAV), Ulus, Ferrère, Asarin, and Maler. Timed pattern matching. In Formal Modeling and Analysis of Timed Systems (FORMATS), Ferrère, Maler, Nickovic, and Ulus. Measuring with timed patterns. In Computer Aided Verification (CAV), Ferrère, Maler, and Nickovic. Trace diagnostics using temporal implicants. In Automated Technology for Verification and Analysis (ATVA), Ulus, Ferrère, Asarin, and Maler. Online timed pattern matching using derivatives In Tools and Algorithms for the Construction and Analysis of Systems (TACAS), / 40
92 Future Works Robustness of Signal Regular Expressions New monitoring algorithms for SRE Integrate SRE with STL Formal verification using regular expressions 40 / 40
Trace Diagnostics using Temporal Implicants
Trace Diagnostics using Temporal Implicants ATVA 15 Thomas Ferrère 1 Dejan Nickovic 2 Oded Maler 1 1 VERIMAG, University of Grenoble / CNRS 2 Austrian Institute of Technology October 14, 2015 Motivation
More informationEfficient Robust Monitoring for STL
100 120 Efficient Robust Monitoring for STL Alexandre Donzé 1, Thomas Ferrère 2, Oded Maler 2 1 University of California, Berkeley, EECS dept 2 Verimag, CNRS and Grenoble University May 28, 2013 Efficient
More informationPattern Matching with Time Theory and Applications
Thesis Defense Pattern Matching with Time Theory and Applications Doğan Ulus January 15, 2018 Grenoble, France Supervisor Reviewers Examiners Invited Oded Maler Rajeev Alur Saddek Bensalem Eugene Asarin
More informationAMT 2.0: Qualitative and Quantitative Trace Analysis with Extended Signal Temporal Logic
* Evaluated * TACAS * Artifact * AEC AMT 2.0: Qualitative and Quantitative Trace Analysis with Extended Signal Temporal Logic Dejan Ničković 1, Olivier Lebeltel 2, Oded Maler 2, Thomas Ferrère 3, Dogan
More informationOn the Quantitative Semantics of Regular Expressions over Real-Valued Signals
On the Quantitative Semantics of Regular Expressions over Real-Valued Signals Alexey Bakhirkin 1, Thomas Ferrère 2, Oded Maler 1, and Dogan Ulus 1 1 Université Grenoble-Alpes, VERIMAG, F-38000 Grenoble,
More informationOn Signal Temporal Logic
100 120 On Signal Temporal Logic Alexandre Donzé University of California, Berkeley February 3, 2014 Alexandre Donzé EECS294-98 Spring 2014 1 / 52 Outline 100 120 1 Signal Temporal Logic From LTL to STL
More informationSpecification Mining of Industrial-scale Control Systems
100 120 Specification Mining of Industrial-scale Control Systems Alexandre Donzé Joint work with Xiaoqing Jin, Jyotirmoy V. Deshmuck, Sanjit A. Seshia University of California, Berkeley May 14, 2013 Alexandre
More informationTesting System Conformance for Cyber-Physical Systems
Testing System Conformance for Cyber-Physical Systems Testing systems by walking the dog Rupak Majumdar Max Planck Institute for Software Systems Joint work with Vinayak Prabhu (MPI-SWS) and Jyo Deshmukh
More informationSpecification-based Monitoring of Cyber-Physical Systems: A Survey on Theory, Tools and Applications
Specification-based Monitoring of Cyber-Physical Systems: A Survey on Theory, Tools and Applications Ezio Bartocci 1, Jyotirmoy Deshmukh 2, Alexandre Donzé 3, Georgios Fainekos 4, Oded Maler 5, Dejan Ničković
More informationTimed Pattern Matching
Timed Pattern Matching Dogan Ulus 1, Thomas Ferrère 1, Eugene Asarin 2, and Oded Maler 1 1 VERIMAG, CNRS and the University of Grenoble-Alpes, France 2 LIAFA, Université Paris Diderot / CNRS, Paris, France
More informationThe State Explosion Problem
The State Explosion Problem Martin Kot August 16, 2003 1 Introduction One from main approaches to checking correctness of a concurrent system are state space methods. They are suitable for automatic analysis
More informationRanking Verification Counterexamples: An Invariant guided approach
Ranking Verification Counterexamples: An Invariant guided approach Ansuman Banerjee Indian Statistical Institute Joint work with Pallab Dasgupta, Srobona Mitra and Harish Kumar Complex Systems Everywhere
More informationVerifying Global Convergence for a Digital Phase-Locked Loop
Verifying Global Convergence for a Digital Phase-Locked Loop Jijie Wei & Yan Peng & Mark Greenstreet & Grace Yu University of British Columbia Vancouver, Canada October 22, 2013 Wei & Peng & Greenstreet
More informationRuntime Verification of Analog and Mixed Signal Designs
Runtime Verification of Analog and Mixed Signal Designs Zhiwei Wang A Thesis in The Department of Electrical and Computer Engineering Presented in Partial Fulfillment of the Requirements for the Degree
More informationarxiv: v1 [cs.ro] 12 Mar 2019
Arithmetic-Geometric Mean Robustness for Control from Signal Temporal Logic Specifications *Noushin Mehdipour, *Cristian-Ioan Vasile and Calin Belta arxiv:93.5v [cs.ro] Mar 9 Abstract We present a new
More informationOn Real-time Monitoring with Imprecise Timestamps
On Real-time Monitoring with Imprecise Timestamps David Basin 1, Felix Klaedtke 2, Srdjan Marinovic 1, and Eugen Zălinescu 1 1 Institute of Information Security, ETH Zurich, Switzerland 2 NEC Europe Ltd.,
More informationFormal Requirement Debugging for Testing and Verification of Cyber-Physical Systems
Formal Requirement Debugging for Testing and Verification of Cyber-Physical Systems arxiv:1607.02549v3 [cs.sy] 18 May 2017 Adel Dokhanchi, Bardh Hoxha, and Georgios Fainekos School of Computing, Informatics
More informationDryVR: Data-driven verification and compositional reasoning for automotive systems
DryVR: Data-driven verification and compositional reasoning for automotive systems Chuchu Fan, Bolun Qi, Sayan Mitra, Mahesh Viswannathan University of Illinois at Urbana-Champaign CAV 2017, Heidelberg,
More informationAbstractions and Decision Procedures for Effective Software Model Checking
Abstractions and Decision Procedures for Effective Software Model Checking Prof. Natasha Sharygina The University of Lugano, Carnegie Mellon University Microsoft Summer School, Moscow, July 2011 Lecture
More informationAn On-the-fly Tableau Construction for a Real-Time Temporal Logic
#! & F $ F ' F " F % An On-the-fly Tableau Construction for a Real-Time Temporal Logic Marc Geilen and Dennis Dams Faculty of Electrical Engineering, Eindhoven University of Technology P.O.Box 513, 5600
More informationGeorgios E. Fainekos and George J. Pappas
FORMATS 2007 Georgios E. Fainekos and George J. Pappas Department of Computer and Information Science University of Pennsylvania fainekos @ seas.upenn.edu http://www.seas.upenn.edu/~fainekos/ Motivation
More informationIMPROVED MODEL GENERATION AND PROPERTY SPECIFICATION FOR ANALOG/MIXED-SIGNAL CIRCUITS
IMPROVED MODEL GENERATION AND PROPERTY SPECIFICATION FOR ANALOG/MIXED-SIGNAL CIRCUITS by Dhanashree R. Kulkarni A thesis submitted to the faculty of The University of Utah in partial fulfillment of the
More informationAnalysis of a Boost Converter Circuit Using Linear Hybrid Automata
Analysis of a Boost Converter Circuit Using Linear Hybrid Automata Ulrich Kühne LSV ENS de Cachan, 94235 Cachan Cedex, France, kuehne@lsv.ens-cachan.fr 1 Introduction Boost converter circuits are an important
More informationA Hierarchy for Accellera s Property Specification Language
A Hierarchy for Accellera s Property Specification Language Thomas Türk May 1st, 2005 Diploma Thesis University of Kaiserslautern Supervisor: Prof. Dr. Klaus Schneider Vorliegende Diplomarbeit wurde von
More informationVacuity Aware Falsification for MTL Request-Response Specifications
Vacuity Aware Falsification for MTL Request-Response Specifications Adel Dokhanchi, Shakiba Yaghoubi, Bardh Hoxha, and Georgios Fainekos Abstract We propose a method to improve the automated test case
More informationHelsinki University of Technology Laboratory for Theoretical Computer Science Research Reports 66
Helsinki University of Technology Laboratory for Theoretical Computer Science Research Reports 66 Teknillisen korkeakoulun tietojenkäsittelyteorian laboratorion tutkimusraportti 66 Espoo 2000 HUT-TCS-A66
More informationResilient Formal Synthesis
Resilient Formal Synthesis Calin Belta Boston University CDC 2017 Workshop: 30 years of the Ramadge-Wonham Theory of Supervisory Control: A Retrospective and Future Perspectives Outline Formal Synthesis
More informationarxiv: v1 [cs.lo] 1 Jan 2019
ONLINE MONITORING OF METRIC TEMPORAL LOGIC USING SEQUENTIAL NETWORKS DOGAN ULUS arxiv:1901.00175v1 [cs.lo] 1 Jan 2019 Abstract. Metric Temporal Logic (MTL) is a popular formalism to specify patterns with
More informationProving Real-time Properties of Embedded Software Systems 0-0
Proving Real-time Properties of Embedded Software Systems 0-0 Outline of Presentation Introduction and Preliminaries Previous Related Work Held For Operator Sensor Lock System Verified Design for Timing
More informationDiagnosis of Dense-Time Systems using Digital-Clocks
Diagnosis of Dense-Time Systems using Digital-Clocks Shengbing Jiang GM R&D and Planning Mail Code 480-106-390 Warren, MI 48090-9055 Email: shengbing.jiang@gm.com Ratnesh Kumar Dept. of Elec. & Comp. Eng.
More informationAugmenting a Regular Expression-Based Temporal Logic with Local Variables
Augmenting a Regular Expression-Based Temporal Logic with Local Variables Cindy Eisner IBM Haifa Research Laboratory Email: eisner@il.ibm.com Dana Fisman Hebrew University and IBM Haifa Research Laboratory
More informationPSL Model Checking and Run-time Verification via Testers
PSL Model Checking and Run-time Verification via Testers Formal Methods 2006 Aleksandr Zaks and Amir Pnueli New York University Introduction Motivation (Why PSL?) A new property specification language,
More informationSynthesis of Designs from Property Specifications
Synthesis of Designs from Property Specifications Amir Pnueli New York University and Weizmann Institute of Sciences FMCAD 06 San Jose, November, 2006 Joint work with Nir Piterman, Yaniv Sa ar, Research
More informationFormal Verification of Analog and Mixed Signal Designs in Mathematica
Formal Verification of Analog and Mixed Signal Designs in Mathematica Mohamed H. Zaki, Ghiath Al-Sammane, and Sofiène Tahar Dept. of Electrical & Computer Engineering, Concordia University 1455 de Maisonneuve
More informationFormally Analyzing Adaptive Flight Control
Formally Analyzing Adaptive Flight Control Ashish Tiwari SRI International 333 Ravenswood Ave Menlo Park, CA 94025 Supported in part by NASA IRAC NRA grant number: NNX08AB95A Ashish Tiwari Symbolic Verification
More informationHybridSAL Relational Abstracter
HybridSAL Relational Abstracter Ashish Tiwari SRI International, Menlo Park, CA. ashish.tiwari@sri.com Abstract. In this paper, we present the HybridSAL relational abstracter a tool for verifying continuous
More informationEfficient Verification of Multi-Property Designs. The benefit of wrong assumptions (E. Goldberg, M. Güdemann, D. Kroening, R.
Efficient Verification of Multi-Property Designs The benefit of wrong assumptions (E. Goldberg, M. Güdemann, D. Kroening, R. Mukherjee) Motivation Main bulk of research: single property verification A
More informationModels for Efficient Timed Verification
Models for Efficient Timed Verification François Laroussinie LSV / ENS de Cachan CNRS UMR 8643 Monterey Workshop - Composition of embedded systems Model checking System Properties Formalizing step? ϕ Model
More informationLogic-based Multi-Objective Design of Chemical Reaction Networks
Logic-based Multi-Objective Design of Chemical Reaction Networks Luca Bortolussi 1 Alberto Policriti 2 Simone Silvetti 2,3 1 DMG, University of Trieste, Trieste, Italy luca@dmi.units.it 2 Dima, University
More informationFrom MITL to Timed Automata Oded Maler 1, Dejan Nickovic 1 and Amir Pnueli 2,3 1 Verimag, 2 Av. de Vignate, 38610 Gières, France [Dejan.Nickovic Oded.Maler]@imag.fr 2 Weizmann Institute of Science, Rehovot
More informationCourse Runtime Verification
Course Martin Leucker (ISP) Volker Stolz (Høgskolen i Bergen, NO) INF5140 / V17 Chapters of the Course Chapter 1 Recall in More Depth Chapter 2 Specification Languages on Words Chapter 3 LTL on Finite
More informationAnalyzing fuzzy and contextual approaches to vagueness by semantic games
Analyzing fuzzy and contextual approaches to vagueness by semantic games PhD Thesis Christoph Roschger Institute of Computer Languages Theory and Logic Group November 27, 2014 Motivation Vagueness ubiquitous
More informationIMITATOR: A Tool for Synthesizing Constraints on Timing Bounds of Timed Automata
ICTAC 09 IMITATOR: A Tool for Synthesizing Constraints on Timing Bounds of Timed Automata Étienne ANDRÉ Laboratoire Spécification et Vérification LSV, ENS de Cachan & CNRS Étienne ANDRÉ (LSV) ICTAC 09
More informationFrom MTL to Deterministic Timed Automata
From MTL to Deterministic Timed Automata Dejan Ničković 1 and Nir Piterman 1 IST, Klosterneuburg, Austria Imperial College London, London, UK Abstract. In this paper we propose a novel technique for constructing
More informationSoftware Verification with Abstraction-Based Methods
Software Verification with Abstraction-Based Methods Ákos Hajdu PhD student Department of Measurement and Information Systems, Budapest University of Technology and Economics MTA-BME Lendület Cyber-Physical
More informationSTL Model Checking of Continuous and Hybrid Systems
STL Model Checking of Continuous and Hybrid Systems Hendrik Roehm 1, Jens Oehlerking 1, Thomas Heinz 1, and Matthias Althoff 1 Robert Bosch GmbH, Corporate Research, Renningen, Germany {hendrik.roehm,
More informationNon-elementary Lower Bound for Propositional Duration. Calculus. A. Rabinovich. Department of Computer Science. Tel Aviv University
Non-elementary Lower Bound for Propositional Duration Calculus A. Rabinovich Department of Computer Science Tel Aviv University Tel Aviv 69978, Israel 1 Introduction The Duration Calculus (DC) [5] is a
More informationUsing Patterns and Composite Propositions to Automate the Generation of LTL Specifications
Using Patterns and Composite Propositions to Automate the Generation of LTL Specifications Salamah Salamah, Ann Q. Gates, Vladik Kreinovich, and Steve Roach Dept. of Computer Science, University of Texas
More informationRobust Linear Temporal Logic
Robust Linear Temporal Logic Paulo Tabuada 1 and Daniel Neider 2 1 Department of Electrical Engineering, University of California at Los Angeles, Los Angeles, CA 90095, USA tabuada@ucla.edu 2 Department
More informationA Quantum Computing Approach to the Verification and Validation of Complex Cyber-Physical Systems
A Quantum Computing Approach to the Verification and Validation of Complex Cyber-Physical Systems Achieving Quality and Cost Control in the Development of Enormous Systems Safe and Secure Systems and Software
More informationCharacterizing Fault-Tolerant Systems by Means of Simulation Relations
Characterizing Fault-Tolerant Systems by Means of Simulation Relations TECHNICAL REPORT Ramiro Demasi 1, Pablo F. Castro 2,3, Thomas S.E. Maibaum 1, and Nazareno Aguirre 2,3 1 Department of Computing and
More informationDesign of Embedded Systems: Models, Validation and Synthesis (EE 249) Lecture 9
Design of Embedded Systems: Models, Validation and Synthesis (EE 249) Lecture 9 Prof. Dr. Reinhard von Hanxleden Christian-Albrechts Universität Kiel Department of Computer Science Real-Time Systems and
More informationLecture 3: Semantics of Propositional Logic
Lecture 3: Semantics of Propositional Logic 1 Semantics of Propositional Logic Every language has two aspects: syntax and semantics. While syntax deals with the form or structure of the language, it is
More informationAdvanced Verification and Validation Methods for Cyber-Physical Systems
Advanced Verification and Validation Methods for Cyber-Physical Systems James Kapinski, Joint work with Hisahiro Ito, Ken Butts, Jyotirmoy Deshmukh, and Xiaoqing Jin October, 2017 Outline 1. Cyber-physical
More informationRelational Interfaces and Refinement Calculus for Compositional System Reasoning
Relational Interfaces and Refinement Calculus for Compositional System Reasoning Viorel Preoteasa Joint work with Stavros Tripakis and Iulia Dragomir 1 Overview Motivation General refinement Relational
More informationMetric Interval Temporal Logic Specification Elicitation and Debugging
Metric Interval Temporal Logic Specification Elicitation and Debugging Adel Dokhanchi, Bardh Hoxha, and Georgios Fainekos School of Computing, Informatics and Decision Systems Arizona State University,
More informationSecurity as a Resource in Process-Aware Information Systems
Security as a Resource in Process-Aware Information Systems 14 October 2011 Joint Work with: Jason Crampton Information Security Group Royal Holloway Jim Huan-Pu Kuo Department of Computing Imperial College
More informationFormal Verification Methods 1: Propositional Logic
Formal Verification Methods 1: Propositional Logic John Harrison Intel Corporation Course overview Propositional logic A resurgence of interest Logic and circuits Normal forms The Davis-Putnam procedure
More informationEAHyper: Satisfiability, Implication, and Equivalence Checking of Hyperproperties
EAHyper: Satisfiability, Implication, and Equivalence Checking of Hyperproperties Bernd Finkbeiner, Christopher Hahn, and Marvin Stenger Saarland Informatics Campus, Saarland University, Saarbrücken, Germany
More informationLinear Temporal Logic and Büchi Automata
Linear Temporal Logic and Büchi Automata Yih-Kuen Tsay Department of Information Management National Taiwan University FLOLAC 2009 Yih-Kuen Tsay (SVVRL @ IM.NTU) Linear Temporal Logic and Büchi Automata
More informationComputation Tree Logic
Computation Tree Logic Hao Zheng Department of Computer Science and Engineering University of South Florida Tampa, FL 33620 Email: zheng@cse.usf.edu Phone: (813)974-4757 Fax: (813)974-5456 Hao Zheng (CSE,
More informationFormally Correct Monitors for Hybrid Automata. Verimag Research Report n o TR
Formally Correct Monitors for Hybrid Automata Goran Frehse, Nikolaos Kekatos, Dejan Nickovic Verimag Research Report n o TR-2017-5 September 20, 2017 Verimag, University of Grenoble Alpes, Grenoble, France.
More informationTimed Automata. Semantics, Algorithms and Tools. Zhou Huaiyang
Timed Automata Semantics, Algorithms and Tools Zhou Huaiyang Agenda } Introduction } Timed Automata } Formal Syntax } Operational Semantics } Verification Problems } Symbolic Semantics & Verification }
More informationProving Inter-Program Properties
Unité Mixte de Recherche 5104 CNRS - INPG - UJF Centre Equation 2, avenue de VIGNATE F-38610 GIERES tel : +33 456 52 03 40 fax : +33 456 52 03 50 http://www-verimag.imag.fr Proving Inter-Program Properties
More informationModel Checking of Hybrid Systems
Model Checking of Hybrid Systems Goran Frehse AVACS Autumn School, October 1, 2015 Univ. Grenoble Alpes Verimag, 2 avenue de Vignate, Centre Equation, 38610 Gières, France, Overview Hybrid Automata Set-Based
More informationBounded Model Checking with SAT/SMT. Edmund M. Clarke School of Computer Science Carnegie Mellon University 1/39
Bounded Model Checking with SAT/SMT Edmund M. Clarke School of Computer Science Carnegie Mellon University 1/39 Recap: Symbolic Model Checking with BDDs Method used by most industrial strength model checkers:
More informationSemi-formal verification of the steady state behavior of mixed-signal circuits by SAT-based property checking
Theoretical Computer Science 404 (2008) 293 307 Contents lists available at ScienceDirect Theoretical Computer Science journal homepage: www.elsevier.com/locate/tcs Semi-formal verification of the steady
More informationarxiv: v1 [cs.sy] 8 Mar 2017
Control Synthesis for Multi-Agent Systems under Metric Interval Temporal Logic Specifications Sofie Andersson Alexandros Nikou Dimos V. Dimarogonas ACCESS Linnaeus Center, School of Electrical Engineering
More informationRefinement-Robust Fairness
Refinement-Robust Fairness Hagen Völzer Institut für Theoretische Informatik Universität zu Lübeck May 10, 2005 0 Overview 1. Problem 2. Formalization 3. Solution 4. Remarks 1 Problem weak fairness wrt
More informationUsing Valued Booleans to Find Simpler Counterexamples in Random Testing of Cyber-Physical Systems
Using Valued Booleans to Find Simpler Counterexamples in Random Testing of Cyber-Physical Systems Koen Claessen Nicholas Smallbone Johan Eddeland, Zahra Ramezani Knut Åkesson Department of Computer Science
More informationRobustness of Temporal Logic Specifications for Continuous-Time Signals
Robustness of Temporal Logic Specifications for Continuous-Time Signals Georgios E. Fainekos a, George J. Pappas a,b a Department of Computer and Information Science, University of Pennsylvania, 3330 Walnut
More informationarxiv: v1 [cs.lo] 21 Nov 2018
Information-Guided Temporal ogic Inference with Prior Knowledge arxiv:1811.08846v1 [cs.o] 21 Nov 2018 Zhe Xu, Melkior Ornik, A. Agung Julius, Ufuk Topcu November 22, 2018 Abstract This paper investigates
More informationApplied Logic. Lecture 1 - Propositional logic. Marcin Szczuka. Institute of Informatics, The University of Warsaw
Applied Logic Lecture 1 - Propositional logic Marcin Szczuka Institute of Informatics, The University of Warsaw Monographic lecture, Spring semester 2017/2018 Marcin Szczuka (MIMUW) Applied Logic 2018
More informationCOP4020 Programming Languages. Introduction to Axiomatic Semantics Prof. Robert van Engelen
COP4020 Programming Languages Introduction to Axiomatic Semantics Prof. Robert van Engelen Assertions and Preconditions Assertions are used by programmers to verify run-time execution An assertion is a
More informationAlgorithms for Monitoring Real-time Properties
Algorithms for Monitoring Real-time Properties David Basin, Felix Klaedtke, and Eugen Zălinescu Computer Science Department, ETH Zurich, Switzerland Abstract. We present and analyze monitoring algorithms
More informationIC3 and Beyond: Incremental, Inductive Verification
IC3 and Beyond: Incremental, Inductive Verification Aaron R. Bradley ECEE, CU Boulder & Summit Middle School IC3 and Beyond: Incremental, Inductive Verification 1/62 Induction Foundation of verification
More informationStructural Contradictions
Structural Contradictions Cindy Eisner 1 and Dana Fisman 1,2 1 IBM Haifa Research Laboratory 2 Hebrew University Abstract. We study the relation between logical contradictions such as p p and structural
More informationMethodology to combine Formal and Fault simulator to measure safety metrics
Methodology to combine Formal and Fault simulator to measure safety metrics Jain Gaurav, Infineon Technologies AP Pte LTD, Singapore Kadambi Ranga, Infineon Technologies AP Pte LTD, Singapore Bandlamudi
More informationLinear Time Logic Control of Discrete-Time Linear Systems
University of Pennsylvania ScholarlyCommons Departmental Papers (ESE) Department of Electrical & Systems Engineering December 2006 Linear Time Logic Control of Discrete-Time Linear Systems Paulo Tabuada
More informationAutomata, Logic and Games: Theory and Application
Automata, Logic and Games: Theory and Application 1. Büchi Automata and S1S Luke Ong University of Oxford TACL Summer School University of Salerno, 14-19 June 2015 Luke Ong Büchi Automata & S1S 14-19 June
More informationSemi-asynchronous. Fault Diagnosis of Discrete Event Systems ALEJANDRO WHITE DR. ALI KARIMODDINI OCTOBER
Semi-asynchronous Fault Diagnosis of Discrete Event Systems ALEJANDRO WHITE DR. ALI KARIMODDINI OCTOBER 2017 NC A&T State University http://www.ncat.edu/ Alejandro White Semi-asynchronous http://techlav.ncat.edu/
More informationDeclarative modelling for timing
Declarative modelling for timing The real-time logic: Duration Calculus Michael R. Hansen mrh@imm.dtu.dk Informatics and Mathematical Modelling Technical University of Denmark 02153 Declarative Modelling,
More informationSymbolic Model Checking Property Specification Language*
Symbolic Model Checking Property Specification Language* Ji Wang National Laboratory for Parallel and Distributed Processing National University of Defense Technology *Joint Work with Wanwei Liu, Huowang
More informationAlgorithmic verification
Algorithmic verification Ahmed Rezine IDA, Linköpings Universitet Hösttermin 2018 Outline Overview Model checking Symbolic execution Outline Overview Model checking Symbolic execution Program verification
More informationThe algorithmic analysis of hybrid system
The algorithmic analysis of hybrid system Authors: R.Alur, C. Courcoubetis etc. Course teacher: Prof. Ugo Buy Xin Li, Huiyong Xiao Nov. 13, 2002 Summary What s a hybrid system? Definition of Hybrid Automaton
More informationAnalysis for Dynamic of Analog Circuits by using HSPN
Proceedings of the 11th WSEAS International Conference on CIRCUITS, Agios Nikolaos, Crete Island, Greece, July 23-25, 2007 207 Analysis for Dynamic of Analog Circuits by using HSPN MENG ZHANG, SHENGBING
More informationFormal Verification and Automated Generation of Invariant Sets
Formal Verification and Automated Generation of Invariant Sets Khalil Ghorbal Carnegie Mellon University Joint work with Andrew Sogokon and André Platzer Toulouse, France 11-12 June, 2015 K. Ghorbal (CMU,
More informationGeorgios E. Fainekos, Savvas G. Loizou and George J. Pappas. GRASP Lab Departments of CIS, MEAM and ESE University of Pennsylvania
Georgios E. Fainekos, Savvas G. Loizou and George J. Pappas CDC 2006 Math free Presentation! Lab Departments of CIS, MEAM and ESE University of Pennsylvania Motivation Motion Planning 60 50 40 π 0 π 4
More informationOn Timed Components and their Abstraction
On Timed Components and their Abstraction Ramzi Ben Salah VERIMAG 2, av. de Vignate 386 Gieres, France Ramzi.Salah@imag.fr Marius Bozga VERIMAG 2, av. de Vignate 386 Gieres, France Marius.Bozga@imag.fr
More informationThe Quasi-Synchronous Approach to Distributed Control Systems
The Quasi-Synchronous Approach to Distributed Control Systems Paul Caspi caspi@imag.fr Verimag Laboratory http://www-verimag.imag.fr Crisys Esprit Project http://borneo.gmd.de/ ap/crisys/ The Quasi-Synchronous
More informationVerification of analog and mixed-signal circuits using hybrid systems techniques
FMCAD, November 2004, Austin Verification of analog and mixed-signal circuits using hybrid systems techniques Thao Dang, Alexandre Donze, Oded Maler VERIMAG Grenoble, France Plan 1. Introduction 2. Verification
More informationConstraint Solving for Program Verification: Theory and Practice by Example
Constraint Solving for Program Verification: Theory and Practice by Example Andrey Rybalchenko Technische Universität München Abstract. Program verification relies on the construction of auxiliary assertions
More informationExecuting the formal semantics of the Accellera Property Specification Language
Executing the PSL semantics 1/17 Executing the formal semantics of the Accellera Property Specification Language joint work with Joe Hurd & Konrad Slind Standard practice: generate tools from formal syntax
More informationMotivation Framework Proposed theory Summary
A Compositional Theory for Observational Equivalence Checking of Hardware Presenter : Authors : Daher Kaiss Zurab Khasidashvili Daher Kaiss Doron Bustan Formal Technology and Logic Group Core Cad Technologies
More informationOn the Design of Adaptive Supervisors for Discrete Event Systems
On the Design of Adaptive Supervisors for Discrete Event Systems Vigyan CHANDRA Department of Technology, Eastern Kentucky University Richmond, KY 40475, USA and Siddhartha BHATTACHARYYA Division of Computer
More informationFirst Order Differential Equations Lecture 3
First Order Differential Equations Lecture 3 Dibyajyoti Deb 3.1. Outline of Lecture Differences Between Linear and Nonlinear Equations Exact Equations and Integrating Factors 3.. Differences between Linear
More informationSPACES ENDOWED WITH A GRAPH AND APPLICATIONS. Mina Dinarvand. 1. Introduction
MATEMATIČKI VESNIK MATEMATIQKI VESNIK 69, 1 (2017), 23 38 March 2017 research paper originalni nauqni rad FIXED POINT RESULTS FOR (ϕ, ψ)-contractions IN METRIC SPACES ENDOWED WITH A GRAPH AND APPLICATIONS
More informationLinking Duration Calculus and TLA
Linking Duration Calculus and TLA Yifeng Chen and Zhiming Liu Department of Computer Science, University of Leicester, Leicester LE1 7RH, UK Email: {Y.Chen, Z.Liu}@mcs.le.ac.uk Abstract. Different temporal
More informationFolk Theorems on the Determinization and Minimization of Timed Automata
Folk Theorems on the Determinization and Minimization of Timed Automata Stavros Tripakis VERIMAG Centre Equation 2, avenue de Vignate, 38610 Gières, France www-verimag.imag.fr Abstract. Timed automata
More informationTemporal Logic Made Practical
Temporal Logic Made Practical Cindy Eisner and Dana Fisman Abstract In the late seventies, Pnueli suggested that functional properties of reactive systems be formally expressed in temporal logic. In order
More information