Logical Effort EE141
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1 Logical Effort 1
2 Question #1 How to best combine logic and drive for a big capacitive load? C L C L 2
3 Question #2 All of these are decoders Which one is best? 3
4 Method to answer both of these questions Extension of buffer sizing problem Logical effort 4
5 Complex Gate Sizing 5
6 Complex Gate Sizing: NAND-2 Example Cgnand = 4C G = (4/3) C ginv C dnand = 6C D = 6γC G =2γC ginv f = C L /C gnand = (3/4) C L /C ginv t pnand = kr N (C dnand + C L ) = kr N (2γC ginv + C L ) = kr N C ginv (2γ + C L /C ginv ) = t inv (2γ + (4/3)f) 6
7 Logical Effort Defines ease of gate to drive external capacitance Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates Logical effort LE is defined as: (R eq,gate C in,gate )/(R eq,inv C in,inv ) Easiest way to calculate (usually): Size gate to deliver same current as an inverter, take ratio of gate input capacitance to inverter capacitance LE increases with gate complexity 7
8 Logical Effort t pgate = t inv (p + LEf) Measure everything in units of t inv (divide by t inv ): p intrinsic delay - gate parameter f(w) LE logical effort gate parameter f(w) f electrical fanout = C L /C in = f (W) Normalize everything to an inverter: LE inv =1, p inv = γ 8
9 Delay of a Logic Gate Gate delay: Delay = EF + p (measured in units of t inv ) effective fanout Effective fanout: EF = LE f intrinsic delay logical effort electrical fanout = C L /C in Logical effort is a function of topology, independent of sizing Effective fanout is a function of load/gate size 9
10 Logical Effort of Gates Normalized delay (d) LE= p= d= t pnand-2 LE= p= d= tpinv p = γ Fan-in (for top input) Fan-out (f) 10
11 Delay Of NOR-2 Gate 1. Size for same resistance as inverter 2. LE = ratio of input cap of gate versus inverter Intrinsic capacitance (C dnor ) = t pint (NOR) = 11
12 Question Any logic function can be implemented using NOR gates only or NAND gates only! Which of the two approaches is preferable in CMOS (from a performance perspective)? 12
13 Logical Effort [From Sutherland, Sproull, Harris] 13
14 Optimizing Complex Combinational Logic 14
15 Multistage Networks Effective fanout: EF i = LE i f i Only for tree networks Path delay D = Σd i = Σp i + ΣEF i Path electrical fanout: F = C L /C in = Πf i Path logical effort: ΠLE = LE 1 LE 2 LE N Path effort: PE = ΠLE F 15
16 Adding branching C L,on_path path of interest C L,off_path,, Branching effort: b = C + C L on path L off path C L, on path 16
17 Multistage Networks Effective fanout: EF i = LE i f i Path delay D = Σd i = Σp i + ΣEF i Path electrical fanout: F = C L /C in Branching effort: ΠB = b 1 b 2 b N Πf i = ΠΒ F (assuming all paths in the tree are important) Path logical effort: ΠLE = LE 1 LE 2 LE N Path effort: PE = ΠLE ΠΒ F 17
18 Optimum Effort per Stage When each stage bears the same effort (effective fanout): N EF EF = = PE N PE Effective fanouts: LE 1 f 1 = LE 2 f 2 = = LE N f N Minimum path delay ( ) 1/ N ˆ N N = 1 i i + i i = + = i= 1 i D LE f p N PE p 18
19 Optimal Number of Stages For a given load, and given input capacitance of the first gate Find optimal number of stages and optimal sizing 1/ N D = N PE + p i Remember: we can always add inverters to the end of the chain The best effective fanout EF = PE 1/ Nˆ is still around 4 (3.6 with γ=1) 19
20 Method of Logical Effort: Summary Compute the path effort: PE = (ΠLE)BF Find the best number of stages N ~ log 4 PE Compute the effective fanout/stage EF = PE 1/N Sketch the path with this number of stages Work either from either end, find sizes: C in = C out *LE/EF Reference: Sutherland, Sproull, Harris, Logical Effort, Morgan-Kaufmann
21 Optimizing Complex Combinational Logic: Examples 21
22 Example 1: No branching LE = 1 f = a LE = 5/3 f = b/a LE = 5/3 f = c/b LE = 1 f = 5/c Electrical fanout, F = Π LE = PE = EF/stage = a = b = c = 22
23 Example 1: No branching LE = 1 f = a LE = 5/3 f = b/a LE = 5/3 f = c/b LE = 1 f = 5/c a, b, c are input capacitances normalized to the unit inverter Electrical fanout, F = 5 Π LE = 25/9 PE = 125/9 EF/stage = 1.93 a = 1.93 b = 2.23 c = 2.59 From the back 5/c = 1.93 (5/3)c/b = 1.93 (5/3)b/a =
24 Our old problem: which one is better? LE=10/3 1 ΠLE = 10/3 P = LE=2 5/3 ΠLE = 10/3 P = LE=4/3 5/3 4/3 1 ΠLE = 80/27 P =
25 Adding Branching LE = F = PE = EF 1 = EF 2 = PE = 1 90/5 = (wrong!) (15+15)/5 = 6 90/15 = 6 36, not 18! Better: PE = F LE B = = 36 25
26 Example 2 with Branching Select gate sizes y and z to minimize delay from A to B Logical Effort: LE = Electrical Fanout: F = Branching Effort: B = Path Effort: PE = Best Effective Fanout: EF = Delay: D = 26
27 Example 2 with Branching Select gate sizes y and z to minimize delay from A to B Logical Effort: LE = Electrical Fanout: F = Branching Effort: B = Path Effort: PE = (4/3) 3 C out /C in = = 6 LE F B= 128 PE Best Effective Fanout: EF = 1/3 5 Delay: D = = 21 Work backward for sizes: z = 9C (4/3) = 2.4C 5 y = 3z (4/3) = 1.9C 5 27
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