DIGITAL CONTROL OF POWER CONVERTERS. 2 Digital controller design

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1 DIGITAL CONTROL OF POWER CONVERTERS 2 Digital controller design

2 Outline Review of frequency domain control design Performance limitations Discrete time system analysis and modeling Digital controller design 2

3 Review of frequency domain control design

4 Response of linear systems Discrete system Analog system {r k } {e k } {u k } {y k } r(t) e(t) u(t) y(t) R(z) G(z) R(s) G(s)

5 Review of Continuous system design u G(s) y Frequency response A G(jw) A B B G(jw) w C C 5

6 Ideal controller z(t) disturbances r(t) e(t) f 1 (o) u(t) f(o) y(t) Conceptual controller y f ( u) z 1 y f ( f ( r z)) z y r 6

7 Realization of a conceptual controller z(t) disturbances r(t) u(t) h(o) f(o) y(t) f(o) Conceptual controller The loop implements an approximate inverse of f o, i.e. u = f r, if r h 1 u r 7

8 Realization of a conceptual controller Open loop controller r(t) u(t) h(o) f(o) y(t) f(o) Feedback controller r(t) R(s) G(s) y(t) 8

9 Review of Continuous system design r(t)?? e(t) u(t) y(t) R(s) G(s) e 1 r 1 RG error 1 S S :Nominal sensitivity 1 RG RG(jw) RG:Loop Gain R(jw) G(jw) w c w 1 e( jw) r( jw) 1 RG ( jw ) S(jw) Bandwidth RG(jw c ) =1 9

10 Review of Continuous system design r(t)?? e(t) u(t) y(t) R(s) G(s) e 1 r 1 RG error w=0.1w c e 0.1r r e RG(jw) w=w c e 0.7r e R(jw) G(jw) w c w w=10w c e r e S(jw) RG s For () c w jw e( jw) r( jw) s jw wc The control is useful bellow the loop gain bandwidth 10

11 Review of Continuous system design r(t) e(t)?? R(s) u(t) G(s) z(t) disturbances error y(t) w=0.1w c e 0.1r 1 e 1 RG z z e RG(jw) w=w c e 0.7r z e R(jw) G(jw) w c w w=10w c e r z e S(jw) The same effect of feedback for disturbances 11

12 Review of Continuous system design The higher the bandwidth the better the performance z(t) r(t) e(t)?? R(s) u(t) G(s) y(t) RG(jw) w c w S(jw) 12

13 Review of Continuous system design z(t) disturbances r(t) e(t)?? R(s) u(t) G(s) y(t) output y RG 1 RG r Control effort R(jw) G(jw) u u R 1 RG r w Below wc u 1 G r High values of u can lead to saturation!! 13

14 Review of Continuous system design r(t) e(t)?? R(s) u(t) G(s) y(t) n(t) referene y RG 1 RG r noise Noise y RG 1 RG n Noise and reference are amplified in the same way Limit the bandwidth to limit the effect of noise 14

15 Stability margins and sensitivity peak If G 0 is stable Stability is assured if R G does not enclosed 1 Z = N + P Gain and Phase Margins Peak Sensitivity 15

16 Stability margins The gain margin, M g, and the phase margin M f are defined as: Peak sensitivity: S 0 is a maximum at the frequency where G 0 (jw)r(jw) is closest to the point 1. The peak sensitivity is thus 1 / S 1, 1 GR 16

17 Stability margins in Bode diagrams r(t) R(s) G(s) y(t) GR 0 Useful Control Action 17

18 Performance limitations: Bode s Integral constraint r(t) R(s) G(s) y(t) for an open loop stable plant, the integral of the logarithm of the closed loop sensitivity is zero; i.e. ln S ( jw) dw S.2frsp S.1frsp 100 Equal areas 18

19 Performance limitations r(t) R(s) G(s) y(t) Loop gain Sensitivity function S.1frsp S.2frsp Improved performance at low freq S.1frsp 100 Worse performane around bandwidth 19

20 Performance limitations Physical interpretation logs ln S 0 0( jw) dw 0 1 w Sensitivity dirt 20

21 Effect of RHP zeroes and poles r(t) R(s) G(s) y(t) RG(jw) RG(jw) f RHPZ freq f RHPP freq ½ f RHPZ 2 f RHPZ To avoid large frequency domain sensitivity peaks it is necessary to limit the range of sensitivity reduction to be: (i) (ii) less than any right half plane open loop zero greater than any right half plane open loop pole. 21

22 Performance limitations This begs the question What happens if there is a right half plane open loop zero having smaller magnitude than a right half plan open loop pole? Clearly the requirements specified on the previous slide are then mutually incompatible. The consequence is that large sensitivity peaks are unavoidable and, as a result, poor feedback performance is inevitable. 22

23 Outline Review of frequency domain control design Performance limitations Discrete time system analysis and modeling Digital controller design 23

24 Modelling of discrete systems PWM + v e {d k } Driver i L DPWM L {d k } i C C R(z) i R R {e k } + v s processor H(s) ADC {d k } {v k } G(z) v o (t) v(t) {v k } {v ref,k } {v k } v (t) Inside the digital processor the system input and output simply appear as sequences of numbers It therefore makes sense to build digital models that relate a discrete time input sequence, {e(k)}, to a sampled output sequence {d(k )}. 24

25 Sampling and Aliasing Consider the signal HF if the sampling period is chosen equal to 0.1[s] then LF the high frequency component appears as a signal of low frequency (here zero). This phenomenon is known as aliasing. 25

26 Aliasing effect when using low sampling rate is chosen equal to 0.1s Rule of thumb sampling rate should be 5 to 10 times the bandwidth of the signals 26

27 Signal Reconstruction {u[k]} Sample and hold {u[k]} DPWM 27

28 Signal reconstruction Sample and Hold vs PWM

29 Typical discretization of G(s) Zeroorder Hold Sampler H O G(s) G(z) Matlab function: C2D(G(s),TS, zoh ) PWM Power converter ADC The zero order hold is used to model the PWM 29

30 Discrete systems basics sequences Continous functions {u k } {v k } G(z) u(t) u(t) G(s) v(t) v (t) {u k } {v k } Discrete Integral Integral v( k 1) v( k) T u( k) s v( t) v( t ) u( ) d 0 t t 0 30

31 ZTransform Ztransform for discrete time signals is equivalent to the Laplace transform (s) for continuous systems. Consider a sequence {y[k]; k = 0, 1, 2, ]. Then the Ztransform pair associated with {y[k]} is given by Ztransforms have a similar property than the Stransform for discrete time models, namely they convert difference equations (expressed in terms of the shift operator q) into algebraic equations. 31

32 Discrete systems basics sequences Continous functions {u k } {v k } u(t) {u k } Discrete Integral k T s Continous Integral v( k 1) v( k) T u( k) s v( t) v( t ) u( ) d 0 t t 0 Discrete derivative u(t) {u k } Continous derivative v( k) u( k) u( k T s 1) v( t) du( t) dt k T s 32

33 ztransform vs stranform X ( z) xk z k k x(t) {x k } st X ( s) x( t) e dt k T s v( k 1) v( k) T u( k) s Ztransform v( t) v( t ) u( ) d 0 t t 0 stransform z V( z) V( z) T U( z) s Ztransfer function 1 1 V ( s) V ( t0 ) U( s) s s stransfer function T s V ( z) U( z) z 1 1 V ( s) U( s) s 33

34 Z transfer function Ignoring the initial conditions, the Ztransform of the output Y(z) is related to the Ztransform of the input by Y(z) = G q (z)u(z) where G q (z) is called the discrete (shift form) transfer function. 34

35 An interesting observation The Ztransform of a unit pulse is 1 U ( z) 1 0 z Y(z) = G q (z)u(z) {u k } {y k } G q (z) {u k }={1,0,0 } {y k } G(z) is the z transform of the output when the Input is a unit pulse 35

36 Example of a buck converter i L L PWM + v e Driver i C C i R R + v s H(s) v o (t) DPWM {d k } R(z) {e k } ADC e (t) v ref (t) {d k } {e k } e (t) {d k } {e k } G(z) 36

37 Example of a buck converter L + v e Driver i i C L C i R R + v s H(s) v o (t) DPWM {d k } R(z) {e k } ADC e (t) v ref (t) {d k } e (t) {d k } {e k } DPWM G(s) H(s) ADC {e k } {d k } {e k } G(z) 37

38 Example of a buck converter PWM + v e Driver i L DPWM L i C C {d k } R(z) i R R {e k } + v s v o (t) H(s) v(t) ADC {v k } {v ref,k } {v k } v (t) {d k } {d k } {v k } G(z) 38

39 Example of a buck converter PWM + v e Driver i L DPWM L i C C {d k } R(z) i R R {e k } + v s v o (t) H(s) v(t) ADC {v k } {v ref,k } {v k } v (t) {d k } v (t) {d k } {v k } DPWM G(s) H(s) ADC {v k } {d k } {v k } G(z) 39

40 Example of a buck converter PWM + v e Driver i L L i C C i R R + v s v o (t) H(s) v(t) ADC {v k } v (t) DPWM {d k } R(z) {e k } {v k } {d k } {v k } DPWM G(s) H(s) ADC discretization {v k } {e k } {d k } {v k } R(z) G(z) 40

41 Digital controller design 41

42 Example of a buck converter 1 Analog design Design the analog controller Discrete design 1 Discretize the converter v ref (t) R(s) G(s) v o (t) DPWM G(s) H(s) ADC {v k } {d k } G(z) {v k } 2 Discretize the analog controller 2 Design the discrete controller R(s) R(z) {e k } R(z) G(z) {v k } 42

43 Discrete controllers design Analog design Good knowledge of averaged models for converters Complete design in the frequency domain? Good design practices and experience Discrete design Use this kwoledge as basics and push beyond with digital control 43

44 Discrete controllers design Analog design 1 Design the analog controller R(jw) RG(jw) v ref (t) v o (t) R(s) G(s) G(jw) wi s w Rs ( ) (1 ) w c s wz 2 Discretize the controller = How to map s poles to z? zoh foh matched N/A tustin Matlab C2D There are different methods: Zero order hold or step invariant First order hold Pole/zero match Backward Euler, derivative operator or rectangular integration Blinear, Tustin or trapezoidal integration Recommended by Duan, APEC

45 Example v ref (t) R(s) G(s) v o (t) discretize v ref (t) ADC ZOH G(s) R(z) v (t) 45

46 Example R(jw) RG(jw) G(jw) f c freq f c = 1kHz T s = 100us v ref (t) R(s) G(s) v o (t) FOH ZOH 46

47 Example R(jw) RG(jw) G(jw) f c freq f c = 1kHz T s = 100us v ref (t) R(s) G(s) v o (t) tustin Prewarp (1khz) 47

48 Example R(jw) RG(jw) G(jw) f c freq f c = 1kHz T s = 100us v ref (t) R(s) G(s) v o (t) Matched 48

49 Example: Sampling Time effect R(jw) RG(jw) G(jw) f c freq f c = 1kHz v ref (t) R(s) G(s) v o (t) ZOH T s = 100us ZOH T s = 250us 49

50 Example: Sampling time effect R(jw) RG(jw) G(jw) f c freq f c = 1kHz T s = 100us v ref (t) R(s) G(s) v o (t) Matched T s = 100us Matched T s = 250us 50

51 Example R(jw) RG(jw) G(jw) f c freq f c = 1kHz v ref (t) R(s) G(s) v o (t) Prewarp (1kHz) T s = 100us Prewarp (1khz) T s = 250us 51

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