Electronics II. Midterm #2


 Raymond Wade
 1 years ago
 Views:
Transcription
1 The University of Toledo EECS:3400 Electronics I su4ms_elct7.fm Section Electronics II Midterm # Problems Points Total 0 Was the exam fair? yes no
2 The University of Toledo su4ms_elct7.fm Problem 8 points Given is the operational amplifier circuit model shown in Figure.. R v v + R v d + r d Av d + r o R L R 5kΩ R 30kΩ R L 0kΩ A85dB r d 40kΩ r o 3kΩ Figure. An operational circuit amplifier model. Parameter values of circuit elements in the given operational circuit amplifier are finite, and are given in Figure.. For the operational circuit model of Figure., demonstrate an ability to:. recognize the type of the feedback amplifier that it implements,. derive an expression for the amplifier s loop gain T in terms of the given circuit element parameters, 3. work with logarithmic units of gain/amplification. Solution Hint # For full credit, give answers to all questions, prepare all required circuit diagrams and all equations in the space reserved for them; include all symbolic and numerical expressions whose evaluation produces shown numerical results. An explicit demonstration of understanding the following solution steps is expected.. Recognize the type of the operational circuit whose model is shown in Figure., and mark below the name by which it is referred to in professional literature. For full credit, mark your answers yes, no, or not applicable for all offered answers! yes no not applicable x transresistance operational amplifier x inverting operational amplifier, x noninverting operational amplifier, x transconductance operational amplifier.. In the circuit model of Figure., show the positive reference direction for voltage v d. 7/0/4
3 The University of Toledo su4ms_elct7.fm 3.3 Calculate the value of the differential amplifier s magnitudescale voltage gain A. Show your calculation in the space reserved for equation (). A[dB] 0 A[dB] lga A Construct an auxiliary circuit for determining the loop gain of the feedback amplifier circuit shown in Figure.. Show the constructed circuit, with indicated positive reference directions of all relevant voltages, in the space reserved for Figure.. () R R r Av d d r b a v o d v + v 0V v i R 3a v v a + b + + R L Figure. Auxiliary circuit for determining the loop gain T of the amplifier whose circuit model is shown in Figure...5 Using the auxiliary circuit model of Figure., derive an expression for the loop gain T of the amplifier shown in Figure.. Show your calculation in the space reserved for equation (). R d R r d v i R d R +R d v a R a R L (R +R d ) R L (R +R d ) R L +R +R d ) v d v i v b Av d R a r o +R a T v b v i v d v v b a v a v i v d R a R d ()A R +R d ro +R a R R d L (R +R d ) ()(A) R +R d r o +R L (R +R d ) A R d R L r o (R L +R +R d )+R L (R +R d ) 7/0/4
4 The University of Toledo su4ms_elct7.fm 4.6 Calculate the numerical value of the loop gain T of the amplifier whose circuit model is shown in Figure.. Show your calculation in the space reserved for equation (3). R d R r d R r d R +r d 5 40 kω 5+40 (3) T A R d R L r o (R L +R +R d )+R L (R +R d ) ( )+ 0 4 ( ) ( ) ( ) /0/4
5 The University of Toledo su4ms_elct7.fm 5 Problem 7 points Given is the electric circuit model of a Reference Current Source cell shown in Figure.(a). S S M G M G D,D D,D R int M S I REF G + V SS M S R int G + V SS 0V (a) (b) Figure. MOSFET Reference Current Source cell circuit model. (a) The complete circuit model. (b)nonlinear AC model for the model in Figure.(a). For the given electric circuit model of Figure.(a), demonstrate an ability to:. prepare and use in analysis the smallsignal linearized equivalent models of MOSFETs,. determine an expression for the internal AC resistance of a given reference current source, R int. Hint # For full credit, give answers to all questions, prepare all required circuit diagrams and all equations in the space reserved for them; include all symbolic and numerical expressions whose evaluation produces shown numerical results. An explicit demonstration of understanding the following solution steps is expected Label on the circuit models in Figures.(a),.(b) and.(b) the locations of the six transistor terminals: S, G, D, S, G, D.. Prepare the nonlinear AC circuit model of the circuit model shown in Figure.(a). Show the prepared model in the space reserved for Figure.(b) Prepare the smallsignal equivalent circuit model of the MOSFET transistor, and show the prepared model in the space reserved for Figure.(a). 7/0/4
6 The University of Toledo su4ms_elct7.fm 6.4 Prepare the smallsignal, linearized AC, circuit model for the circuit model shown in Figure.(a), and show the prepared model in the space reserved for Figure.(b). S G D g m v gs g o v ds v gs v gs g m v gs S go i t v t g m v gs v g g o D,G D,G v ds v gs (a) Figure. Reference Current Source circuit models. (a) Smallsignal model of the MOSFET transistor. (b)smallsignal linearized AC model of the MOSFET Reference Current Source shown in Figure.(a). (b) S Hint # Notice that in the equivalent circuits of Figures.(b) and.(b) the internal AC resistance, R int, of the analyzed Reference Current Source appears between nodes S and S. As a consequence, the remaining steps for determining R int are:.5 through.7..5 Modify the circuit model of Figure.(b) by connecting a test current source, i t, between the nodes S and S, with its current direction into S..6 Prepare the equations that solve the modified circuit of Figure.(b) for the voltage v t that appears across the current source i t, and has the active convention positive reference direction with respect to i t. Since all energy sources in the circuit are current sources, use the S node, in Figure.(b), as the reference node, for preparing the normal form of Nodal Voltage Method equations (with unknown voltages designated by v t and v g. Show the necessary symbolic calculations in the space reserved for equations (). g o v g g o v t g m (v g + v gs ) g o v g + g o v t i t +g m v gs v gs v g v t g o v g g o v t g m (v g + v g v t ) g o v g + g o v t i t +g m (v g v t ) () (g o + g m )v g (g o + g m )v t 0 (g o + g m )v g + (g o + g m )v t i t 7/0/4
7 The University of Toledo su4ms_elct7.fm 7.7 Solve the resulting equations of section.6 for the ratio v t /i t. Show the necessary symbolic calculations in the space reserved for equations (). Hint #3 For full credit use the determinant method for solving the equations. In the case when a different solution method is used, and the resulting solution is incorrect, the credit for this section will be 0.. (g o + g m ) (g o + g m ) (g o + g m ) (g o + g m ) (g (g o + g m ) (g o + g m ) o + g m ) (g o + g m ) 0 t (g o + g m ) i t (g o + g m ) i t () v t t it (go + gm ) (g o + g m ) i t go + g m R int v t g o + g m i t r o r m r o + r m r o r m. 7/0/4
8 The University of Toledo su4ms_elct7.fm 8 Problem 3 5 points Given is the electric circuit model of a BJT differential amplifier shown in Figure 3.(a). +V CC v I + R C R C v R C R o v o C v o v o v i od C ic Q Q + i E i E i b Q i b i e i Q + e v + I v d I + v be v EE be + R EE v e R EE v d (a) (b) Figure 3. A BJT differential amplifier circuit model. (a) The circuit model with connected signal sources. (b) Equivalent AC circuit model for AC analysis of the circuit in Figure 3.(a). For the given amplifier s circuit model of Figure 3.(a), demonstrate an ability to use:. AC analysis of a BJT differential amplifier to determine the potential at the node to which both emitters are connected.. draw the conclusions suggested by the performed analysis. Hint # For full credit, give answers to all questions, prepare all required circuit diagrams and all equations in the space reserved for them; include all symbolic and numerical expressions whose evaluation produces shown numerical results. Solution An explicit demonstration of understanding the following solution steps is expected. 3. In the space reserved for Figure 3.(b), prepare the AC equivalent circuit model of the circuit model shown in Figure 3.(a). 3. In the circuits of Figure 3.(b) and 3.(b) indicate the positive reference directions for: base currents of the two transistors, emitter currents of the two transistors, base to emitter voltages of the two transistors, emitter to ground voltage. 7/0/4
9 The University of Toledo su4ms_elct7.fm Prepare the smallsignal hybridπ equivalent model of the BJT. Show the prepared model in the space reserved for Figure 3.(a). R C R C B v be i b r π β o i b E i c C v ce v d B B + C C + i b r π V BE E v e β o i b i e β o i b i e i b r π V BE E + R EE v d (a) (b) Figure 3. BJT differential amplifier circuit models. (a) Hybridπ equivalent model of the BJT. (b) Linearized equivalent AC circuit model for the differential amplifier circuit of Figure 3.(a). 3.4 Prepare the linearized AC equivalent model of the differential amplifier by replacing the transistor symbols in the circuit model of Figure3.(b) by the hybridπ equivalent model of the BJT from Figure 3.(a). Show the prepared model in the space reserved for Figure 3.(b). Hint # Check the correctness of expressions that are shown in the space reserved for equations (3). Make sure that you will be using the correct expressions in the sequel. i b g π v be i b g π v be β o i b g m r π i b g m v be β o i b g m r π i b g m v be (3) i e (+β o )i b (g π +g m )v be i e (+β o )i b (g π +g m )v be 7/0/4
10 The University of Toledo su4ms_elct7.fm Prepare the KCL equation for the emitter node in the circuit model of Figure 3.(b), followed by: substitution of emitter currents by their correct expressions from equations (3), and determining the solution of KCL equation for the emitter voltage v e. Show your calculation in the space reserved for equation (3). KCL: i e + i e + G EE v e 0 (g π +g m )v be (g π + g m )v be + G EE v e 0 (g π +g m )(v be + v be ) + G EE v e 0 (3) Voltages v be and v be are related to the voltage v e as, Therefore, (g π +g m )v e + G EE v e 0 v e 0 v d v be v d v e v be v e CONCLUSION v e 0V In the circuit model of Figure 3.(b), Emitter node has the same potential as the ground node. This fact is often reffered to by the statement: "In the Equivalent AC Circuit Model of a DiffAmp, Emitter node is a virtual ground." 7/0/4
Electronics II. Midterm #2
The University of Toledo EECS:3400 Electronics I Section sums_elct7.fm  StudentName Electronics II Midterm # Problems Points. 8. 3. 7 Total 0 Was the exam fair? yes no The University of Toledo sums_elct7.fm
More informationElectronics II. Midterm #1
The University of Toledo EECS:3400 Electronics I su3ms_elct7.fm Section Electronics II Midterm # Problems Points. 5. 6 3. 9 Total 0 Was the exam fair? yes no The University of Toledo su3ms_elct7.fm Problem
More informationElectronics II. Midterm II
The University of Toledo su7ms_elct7.fm  Electronics II Midterm II Problems Points. 7. 7 3. 6 Total 0 Was the exam fair? yes no The University of Toledo su7ms_elct7.fm  Problem 7 points Equation ()
More informationElectronics II. Midterm II
The University of Toledo f4ms_elct7.fm  Section Electronics II Midterm II Problems Points. 7. 7 3. 6 Total 0 Was the exam fair? yes no The University of Toledo f4ms_elct7.fm  Problem 7 points Given in
More informationElectronics II. Final Examination
The University of Toledo f17fs_elct27.fm 1 Electronics II Final Examination Problems Points 1. 11 2. 14 3. 15 Total 40 Was the exam fair? yes no The University of Toledo f17fs_elct27.fm 2 Problem 1 11
More informationElectronics II. Final Examination
f3fs_elct7.fm  The University of Toledo EECS:3400 Electronics I Section Student Name Electronics II Final Examination Problems Points.. 3 3. 5 Total 40 Was the exam fair? yes no Analog Electronics f3fs_elct7.fm
More informationElectronics II. Final Examination
The University of Toledo f6fs_elct7.fm  Electronics II Final Examination Problems Points. 5. 0 3. 5 Total 40 Was the exam fair? yes no The University of Toledo f6fs_elct7.fm  Problem 5 points Given is
More informationThe equivalent model of a certain op amp is shown in the figure given below, where R 1 = 2.8 MΩ, R 2 = 39 Ω, and A =
The equivalent model of a certain op amp is shown in the figure given below, where R 1 = 2.8 MΩ, R 2 = 39 Ω, and A = 10 10 4. Section Break Difficulty: Easy Learning Objective: Understand how real operational
More information55:041 Electronic Circuits The University of Iowa Fall Exam 2
Exam 2 Name: Score /60 Question 1 One point unless indicated otherwise. 1. An engineer measures the (step response) rise time of an amplifier as t r = 0.35 μs. Estimate the 3 db bandwidth of the amplifier.
More informationElectric Circuits I Final Examination
EECS:300 Electric Circuits I ffs_elci.fm  Electric Circuits I Final Examination Problems Points. 4. 3. Total 38 Was the exam fair? yes no //3 EECS:300 Electric Circuits I ffs_elci.fm  Problem 4 points
More informationHomework Assignment 09
Homework Assignment 09 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. What is the 3dB bandwidth of the amplifier shown below if r π = 2.5K, r o = 100K, g m = 40 ms, and C L =
More informationEE 321 Analog Electronics, Fall 2013 Homework #8 solution
EE 321 Analog Electronics, Fall 2013 Homework #8 solution 5.110. The following table summarizes some of the basic attributes of a number of BJTs of different types, operating as amplifiers under various
More informationCircle the one best answer for each question. Five points per question.
ID # NAME EE255 EXAM 3 November 8, 2001 Instructor (circle one) Talavage Gray This exam consists of 16 multiple choice questions and one workout problem. Record all answers to the multiple choice questions
More informationElectric Circuits I. Midterm #1
The University of Toledo Section number s5ms_elci7.fm  Electric Circuits I Midterm # Problems Points. 3 2. 7 3. 5 Total 5 Was the exam fair? yes no The University of Toledo Section number s5ms_elci7.fm
More informationElectric Circuits I. Midterm #1 Examination
EECS:2300, Electric Circuits I s8ms_elci7.fm  Electric Circuits I Midterm # Examination Problems Points. 4 2. 6 3. 5 Total 5 Was the exam fair? yes no EECS:2300, Electric Circuits I s8ms_elci7.fm  2
More informationHomework Assignment 08
Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance
More informationDigital VLSI Design I
The University of Toledo Section f04ms  EES:460/560 Digital VLSI Design I: Basic Subsystems Digital VLSI Design I MIDTERM EXAMINATION Problems Points. 4. 3. 5 Total Was the exam fair? yes no The University
More informationAt point G V = = = = = = RB B B. IN RB f
Common Emitter At point G CE RC 0. 4 12 0. 4 116. I C RC 116. R 1k C 116. ma I IC 116. ma β 100 F 116µ A I R ( 116µ A)( 20kΩ) 2. 3 R + 2. 3 + 0. 7 30. IN R f Gain in Constant Current Region I I I C F
More informationBiasing the CE Amplifier
Biasing the CE Amplifier Graphical approach: plot I C as a function of the DC baseemitter voltage (note: normally plot vs. base current, so we must return to EbersMoll): I C I S e V BE V th I S e V th
More informationBJT Biasing Cont. & Small Signal Model
BJT Biasing Cont. & Small Signal Model Conservative Bias Design (1/3, 1/3, 1/3 Rule) Bias Design Example SmallSignal BJT Models SmallSignal Analysis 1 Emitter Feedback Bias Design R B R C V CC R 1 R
More informationMidterm Exam (closed book/notes) Tuesday, February 23, 2010
University of California, Berkeley Spring 2010 EE 42/100 Prof. A. Niknejad Midterm Exam (closed book/notes) Tuesday, February 23, 2010 Guidelines: Closed book. You may use a calculator. Do not unstaple
More informationElectric Circuits I FINAL EXAMINATION
EECS:300, Electric Circuits I s6fs_elci7.fm  Electric Circuits I FINAL EXAMINATION Problems Points.. 3. 0 Total 34 Was the exam fair? yes no 5//6 EECS:300, Electric Circuits I s6fs_elci7.fm  Problem
More informationECE 3050A, Spring 2004 Page 1. FINAL EXAMINATION  SOLUTIONS (Average score = 78/100) R 2 = R 1 =
ECE 3050A, Spring 2004 Page Problem (20 points This problem must be attempted) The simplified schematic of a feedback amplifier is shown. Assume that all transistors are matched and g m ma/v and r ds.
More informationFYSE400 ANALOG ELECTRONICS
YSE400 ANALOG ELECTONCS LECTUE 3 Bipolar Sub Circuits 1 BPOLA SUB CCUTS Bipolar Current Sinks and Sources Transistor operates in forwardactive region. < < sat CE CN max CE < < + BN CN BN max CE N N N
More informationFinal Exam. 55:041 Electronic Circuits. The University of Iowa. Fall 2013.
Final Exam Name: Max: 130 Points Question 1 In the circuit shown, the opamp is ideal, except for an input bias current I b = 1 na. Further, R F = 10K, R 1 = 100 Ω and C = 1 μf. The switch is opened at
More informationRIB. ELECTRICAL ENGINEERING Analog Electronics. 8 Electrical Engineering RIBR T7. Detailed Explanations. Rank Improvement Batch ANSWERS.
8 Electrical Engineering RIBR T7 Session 089 S.No. : 9078_LS RIB Rank Improvement Batch ELECTRICL ENGINEERING nalog Electronics NSWERS. (d) 7. (a) 3. (c) 9. (a) 5. (d). (d) 8. (c) 4. (c) 0. (c) 6. (b)
More information55:041 Electronic Circuits The University of Iowa Fall Final Exam
Final Exam Name: Score Max: 135 Question 1 (1 point unless otherwise noted) a. What is the maximum theoretical efficiency for a classb amplifier? Answer: 78% b. The abbreviation/term ESR is often encountered
More informationBipolar Junction Transistor (BJT)  Introduction
Bipolar Junction Transistor (BJT)  Introduction It was found in 1948 at the Bell Telephone Laboratories. It is a three terminal device and has three semiconductor regions. It can be used in signal amplification
More informationID # NAME. EE255 EXAM 3 April 7, Instructor (circle one) Ogborn Lundstrom
ID # NAME EE255 EXAM 3 April 7, 1998 Instructor (circle one) Ogborn Lundstrom This exam consists of 20 multiple choice questions. Record all answers on this page, but you must turn in the entire exam.
More informationDesigning Information Devices and Systems I Fall 2018 Lecture Notes Note Introduction: Opamps in Negative Feedback
EECS 16A Designing Information Devices and Systems I Fall 2018 Lecture Notes Note 18 18.1 Introduction: Opamps in Negative Feedback In the last note, we saw that can use an opamp as a comparator. However,
More informationECE Analog Integrated Circuit Design  II P.E. Allen
Lecture 290 Feedback Analysis using Return Ratio (3/20/02) Page 2901 LECTURE 290 FEEDBACK CIRCUIT ANALYSIS USING RETURN RATIO (READING: GHLM 599613) Objective The objective of this presentation is: 1.)
More informationEECS 105: FALL 06 FINAL
University of California College of Engineering Department of Electrical Engineering and Computer Sciences Jan M. Rabaey TuTh 23:30 Wednesday December 13, 12:303:30pm EECS 105: FALL 06 FINAL NAME Last
More informationor Op Amps for short
or Op Amps for short Objective of Lecture Describe how an ideal operational amplifier (op amp) behaves. Define voltage gain, current gain, transresistance gain, and transconductance gain. Explain the operation
More informationUNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences
UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EE 105: Microelectronic Devices and Circuits Spring 2008 MIDTERM EXAMINATION #1 Time
More informationElectric Circuits I Final Examination
The University of Toledo s8fs_elci7.fm  EECS:300 Electric Circuits I Electric Circuits I Final Examination Problems Points.. 3. Total 34 Was the exam fair? yes no The University of Toledo s8fs_elci7.fm
More informationEE105 Fall 2014 Microelectronic Devices and Circuits
EE05 Fall 204 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 5 Sutardja Dai Hall (SDH) Terminal Gain and I/O Resistances of BJT Amplifiers Emitter (CE) Collector (CC) Base (CB)
More informationand V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )
ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets
More informationThe CommonEmitter Amplifier
c Copyright 2009. W. Marshall Leach, Jr., Professor, Georgia Institute of Technology, School of Electrical and Computer Engineering. The CommonEmitter Amplifier Basic Circuit Fig. shows the circuit diagram
More informationECE2262 Electric Circuits. Chapter 4: Operational Amplifier (OPAMP) Circuits
ECE2262 Electric Circuits Chapter 4: Operational Amplifier (OPAMP) Circuits 1 4.1 Operational Amplifiers 2 4. Voltages and currents in electrical circuits may represent signals and circuits can perform
More informationElectronic Circuits Summary
Electronic Circuits Summary Andreas Biri, DITET 6.06.4 Constants (@300K) ε 0 = 8.854 0 F m m 0 = 9. 0 3 kg k =.38 0 3 J K = 8.67 0 5 ev/k kt q = 0.059 V, q kt = 38.6, kt = 5.9 mev V Small Signal Equivalent
More informationBipolar junction transistors
Bipolar junction transistors Find parameters of te BJT in CE configuration at BQ 40 µa and CBQ V. nput caracteristic B / µa 40 0 00 80 60 40 0 0 0, 0,5 0,3 0,35 0,4 BE / V Output caracteristics C / ma
More informationCE/CS Amplifier Response at High Frequencies
.. CE/CS Amplifier Response at High Frequencies INEL 4202  Manuel Toledo August 20, 2012 INEL 4202  Manuel Toledo CE/CS High Frequency Analysis 1/ 24 Outline.1 High Frequency Models.2 Simplified Method.3
More informationE40M. Op Amps. M. Horowitz, J. Plummer, R. Howe 1
E40M Op Amps M. Horowitz, J. Plummer, R. Howe 1 Reading A&L: Chapter 15, pp. 863866. Reader, Chapter 8 Noninverting Amp http://www.electronicstutorials.ws/opamp/opamp_3.html Inverting Amp http://www.electronicstutorials.ws/opamp/opamp_2.html
More informationDepartment of Electrical Engineering and Computer Sciences University of California, Berkeley. Final Exam Solutions
Electrical Engineering 42/00 Summer 202 Instructor: Tony Dear Department of Electrical Engineering and omputer Sciences University of alifornia, Berkeley Final Exam Solutions. Diodes Have apacitance?!?!
More informationESE319 Introduction to Microelectronics. BJT Biasing Cont.
BJT Biasing Cont. Biasing for DC Operating Point Stability BJT Bias Using Emitter Negative Feedback Single Supply BJT Bias Scheme Constant Current BJT Bias Scheme Rule of Thumb BJT Bias Design 1 Simple
More informationECE137B Final Exam. There are 5 problems on this exam and you have 3 hours There are pages 119 in the exam: please make sure all are there.
ECE37B Final Exam There are 5 problems on this exam and you have 3 hours There are pages 9 in the exam: please make sure all are there. Do not open this exam until told to do so Show all work: Credit
More informationDesigning Information Devices and Systems I Fall 2017 Midterm 2. Exam Location: 150 Wheeler, Last Name: Nguyen  ZZZ
EECS 16A Designing Information Devices and Systems I Fall 2017 Midterm 2 Exam Location: 150 Wheeler, Last Name: Nguyen  ZZZ PINT your student ID: PINT AND SIGN your name:, (last name) (first name) (signature)
More informationDigital Logic Design. Midterm #2
EECS: igital Logic esign r. nthony. Johnson s7m2s_dild7.fm  igital Logic esign Midterm #2 Problems Points. 5 2. 4 3. 6 Total 5 Was the exam fair? yes no EECS: igital Logic esign r. nthony. Johnson s7m2s_dild7.fm
More informationEE100Su08 Lecture #9 (July 16 th 2008)
EE100Su08 Lecture #9 (July 16 th 2008) Outline HW #1s and Midterm #1 returned today Midterm #1 notes HW #1 and Midterm #1 regrade deadline: Wednesday, July 23 rd 2008, 5:00 pm PST. Procedure: HW #1: Bart
More informationECE343 Test 1: Feb 10, :008:00pm, Closed Book. Name : SOLUTION
ECE343 Test : Feb 0, 00 6:008:00pm, Closed Book Name : SOLUTION C Depl = C J0 + V R /V o ) m C Diff = τ F g m ω T = g m C µ + C π ω T = g m I / D C GD + C or V OV GS b = τ i τ i = R i C i ω H b Z = Z
More informationChapter7. FET Biasing
Chapter7. J configurations Fixed biasing Self biasing & Common Gate Voltage divider MOS configurations Depletiontype Enhancementtype JFET: Fixed Biasing Example 7.1: As shown in the figure, it is the
More informationLecture 050 Followers (1/11/04) Page ECE Analog Integrated Circuits and Systems II P.E. Allen
Lecture 5 Followers (1/11/4) Page 51 LECTURE 5 FOLLOWERS (READING: GHLM 344362, AH 221226) Objective The objective of this presentation is: Show how to design stages that 1.) Provide sufficient output
More informationECE 6412, Spring Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120
ECE 6412, Spring 2002 Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120 Problem 1O 2O 3 4 5 6 7 8 Score INSTRUCTIONS: This exam is closed book with four sheets of notes permitted. The exam consists of
More informationLecture 13 MOSFET as an amplifier with an introduction to MOSFET smallsignal model and smallsignal schematics. Lena Peterson
Lecture 13 MOSFET as an amplifier with an introduction to MOSFET smallsignal model and smallsignal schematics Lena Peterson 20151013 Outline (1) Why is the CMOS inverter gain not infinite? Largesignal
More informationMetalOxideSemiconductor Field Effect Transistor (MOSFET)
MetalOxideSemiconductor ield Effect Transistor (MOSET) Source Gate Drain p p n substrate  SUB MOSET is a symmetrical device in the most general case (for example, in an integrating circuit) In a separate
More informationEECS 312: Digital Integrated Circuits Midterm Exam 2 December 2010
Signature: EECS 312: Digital Integrated Circuits Midterm Exam 2 December 2010 Robert Dick Show your work. Derivations are required for credit; end results are insufficient. Closed book. No electronic mental
More informationTransistor Characteristics and A simple BJT Current Mirror
Transistor Characteristics and A simple BJT Current Mirror Currentoltage (I) Characteristics Device Under Test DUT i v T T 1 R X R X T for test Independent variable on horizontal axis Could force current
More informationECE343 Test 2: Mar 21, :008:00, Closed Book. Name : SOLUTION
ECE343 Test 2: Mar 21, 2012 6:008:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may
More informationMicroelectronic Circuit Design 4th Edition Errata  Updated 4/4/14
Chapter Text # Inside back cover: Triode region equation should not be squared! i D = K n v GS "V TN " v & DS % ( v DS $ 2 ' Page 49, first exercise, second answer: 1.35 x 10 6 cm/s Page 58, last exercise,
More informationElectronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices
Electronic Circuits 1 Transistor Devices Contents BJT and FET Characteristics Operations 1 What is a transistor? Threeterminal device whose voltagecurrent relationship is controlled by a third voltage
More informationChapter 13 SmallSignal Modeling and Linear Amplification
Chapter 13 SmallSignal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 131 Chapter Goals Understanding of concepts related to: Transistors
More informationEE 230 Lecture 20. Nonlinear Op Amp Applications. The Comparator Nonlinear Analysis Methods
EE 230 Lecture 20 Nonlinear Op Amp Applications The Comparator Nonlinear Analysis Methods Quiz 14 What is the major purpose of compensation when designing an operatinal amplifier? And the number is? 1
More informationECE 523/421  Analog Electronics University of New Mexico Solutions Homework 3
ECE 523/42  Analog Electronics University of New Mexico Solutions Homework 3 Problem 7.90 Show that when ro is taken into account, the voltage gain of the source follower becomes G v v o v sig R L r o
More informationUniversity of Toronto. Final Exam
University of Toronto Final Exam Date  Dec 16, 013 Duration:.5 hrs ECE331 Electronic Circuits Lecturer  D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last
More informationLecture 37: Frequency response. Context
EECS 05 Spring 004, Lecture 37 Lecture 37: Frequency response Prof J. S. Smith EECS 05 Spring 004, Lecture 37 Context We will figure out more of the design parameters for the amplifier we looked at in
More informationUNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences
UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EECS 40 Spring 2000 Introduction to Microelectronic Devices Prof. King MIDTERM EXAMINATION
More informationHalfcircuit incremental analysis techniques
6.012 Electronic Devices and Circuits Lecture 19 Differential Amplifier Stages Outline Announcements Handouts Lecture Outline and Summary Design Problem out tomorrow in recitation Review Singletransistor
More information6.012 Electronic Devices and Circuits Spring 2005
6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) OPEN BOOK Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):
More information(Refer Slide Time: 1:49)
Analog Electronic Circuits Professor S. C. Dutta Roy Department of Electrical Engineering Indian Institute of Technology Delhi Lecture no 14 Module no 01 Midband analysis of FET Amplifiers (Refer Slide
More informationEE201 Review Exam I. 1. The voltage Vx in the circuit below is: (1) 3V (2) 2V (3) 2V (4) 1V (5) 1V (6) None of above
EE201, Review Probs Test 1 page1 Spring 98 EE201 Review Exam I Multiple Choice (5 points each, no partial credit.) 1. The voltage Vx in the circuit below is: (1) 3V (2) 2V (3) 2V (4) 1V (5) 1V (6)
More informationEE 330. Lecture 35. Parasitic Capacitances in MOS Devices
EE 330 Lecture 35 Parasitic Capacitances in MOS Devices Exam 2 Wed Oct 24 Exam 3 Friday Nov 16 Review from Last Lecture Cascode Configuration Discuss V CC gm1 gm1 I B VCC V OUT g02 g01 A  β β VXX Q 2
More informationEE 330 Lecture 25. Amplifier Biasing (precursor) TwoPort Amplifier Model
EE 330 Lecture 25 Amplifier Biasing (precursor) TwoPort Amplifier Model Review from Last Lecture Exam Schedule Exam 2 Friday March 24 Review from Last Lecture Graphical Analysis and Interpretation 2 OX
More informationSOME USEFUL NETWORK THEOREMS
APPENDIX D SOME USEFUL NETWORK THEOREMS Introduction In this appendix we review three network theorems that are useful in simplifying the analysis of electronic circuits: Thévenin s theorem Norton s theorem
More informationBJT Biasing Cont. & Small Signal Model
BJT Biasing Cont. & Small Signal Model Conservative Bias Design Bias Design Example Small Signal BJT Models Small Signal Analysis 1 Emitter Feedback Bias Design Voltage bias circuit Single power supply
More informationEE 330 Lecture 22. Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits
EE 330 Lecture 22 Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits Exam 2 Friday March 9 Exam 3 Friday April 13 Review Session for Exam 2: 6:00
More informationDesign of Analog Integrated Circuits
Design of Analog Integrated Circuits Chapter 11: Introduction to Switched Capacitor Circuits Textbook Chapter 13 13.1 General Considerations 13.2 Sampling Switches 13.3 SwitchedCapacitor Amplifiers 13.4
More informationEE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET
EE 230 Lecture 33 Nonlinear Circuits and Nonlinear Devices Diode BJT MOSFET Review from Last Time: nchannel MOSFET Source Gate L Drain W L EFF Poly Gate oxide nactive psub depletion region (electrically
More informationLecture 23: Negative Resistance Osc, Differential Osc, and VCOs
EECS 142 Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs Prof. Ali M. Niknejad University of California, Berkeley Copyright c 2005 by Ali M. Niknejad A. M. Niknejad University of California,
More informationLecture 11: JFET and MOSFET
ENE 311 Lecture 11: JFET and MOSFET FETs vs. BJTs Similarities: Amplifiers Switching devices Impedance matching circuits Differences: FETs are voltage controlled devices. BJTs are current controlled devices.
More informationCARLETON UNIVERSITY. FINAL EXAMINATION December DURATION 3 HOURS No. of Students 130
ALETON UNIVESITY FINAL EXAMINATION December 005 DUATION 3 HOUS No. of Students 130 Department Name & ourse Number: Electronics ELE 3509 ourse Instructor(s): Prof. John W. M. ogers and alvin Plett AUTHOIZED
More informationEE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR
EE 23 Lecture 3 THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR Quiz 3 Determine I X. Assume W=u, L=2u, V T =V, uc OX =  4 A/V 2, λ= And the number is? 3 8 5 2? 6 4 9 7 Quiz 3
More informationDelhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Ph:
Serial : ND_EE_NW_Analog Electronics_05088 Delhi Noida Bhopal Hyderabad Jaipur Lucknow ndore Pune Bhubaneswar Kolkata Patna Web: Email: info@madeeasy.in Ph: 04546 CLASS TEST 089 ELECTCAL ENGNEENG Subject
More informationExact Analysis of a CommonSource MOSFET Amplifier
Exact Analysis of a CommonSource MOSFET Amplifier Consider the commonsource MOSFET amplifier driven from signal source v s with Thévenin equivalent resistance R S and a load consisting of a parallel
More information1. (50 points, BJT curves & equivalent) For the 2N3904 =(npn) and the 2N3906 =(pnp)
HW 3 1. (50 points, BJT curves & equivalent) For the 2N3904 =(npn) and the 2N3906 =(pnp) a) Obtain in Spice the transistor curves given on the course web page except do in separate plots, one for the npn
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences E. Alon Final EECS 240 Monday, May 19, 2008 SPRING 2008 You should write your results on the exam
More information6.012 Electronic Devices and Circuits
Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to
More informationAssignment 3 ELEC 312/Winter 12 R.Raut, Ph.D.
Page 1 of 3 ELEC 312: ELECTRONICS II : ASSIGNMENT3 Department of Electrical and Computer Engineering Winter 2012 1. A commonemitter amplifier that can be represented by the following equivalent circuit,
More informationPHYS225 Lecture 9. Electronic Circuits
PHYS225 Lecture 9 Electronic Circuits Last lecture Field Effect Transistors Voltage controlled resistor Various FET circuits Switch Source follower Current source Similar to BJT Draws no input current
More informationMassachusetts Institute of Technology Department of Electrical Engineering and Computer Science Circuits & Electronics Spring 2007.
Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.002 Circuits & Electronics Spring 2007 Quiz #2 25 April 2007 Name: There are 20 pages in this quiz, including
More informationECE 6412, Spring Final Exam Page 1
ECE 64, Spring 005 Final Exam Page FINAL EXAMINATION SOLUTIONS (Average score = 89/00) Problem (0 points This problem is required) A comparator consists of an amplifier cascaded with a latch as shown below.
More informationNotes for course EE1.1 Circuit Analysis TOPIC 10 2PORT CIRCUITS
Objectives: Introduction Notes for course EE1.1 Circuit Analysis 45 Reexamination of 1port subcircuits Admittance parameters for port circuits TOPIC 1 PORT CIRCUITS Gain and port impedance from port
More informationChapter 9 Frequency Response. PART C: High Frequency Response
Chapter 9 Frequency Response PART C: High Frequency Response Discrete Common Source (CS) Amplifier Goal: find high cutoff frequency, f H 2 f H is dependent on internal capacitances V o Load Resistance
More informationChapter 6: FieldEffect Transistors
Chapter 6: FieldEffect Transistors slamic University of Gaza Dr. Talal Skaik FETs vs. BJTs Similarities: Amplifiers Switching devices mpedance matching circuits Differences: FETs are voltage controlled
More informationCHAPTER 3: TRANSISTOR MOSFET DR. PHAM NGUYEN THANH LOAN. Hà Nội, 9/24/2012
1 CHAPTER 3: TRANSISTOR MOSFET DR. PHAM NGUYEN THANH LOAN Hà Nội, 9/24/2012 Chapter 3: MOSFET 2 Introduction Classifications JFET DFET (Depletion MOS) MOSFET (Enhancement EFET) DC biasing Small signal
More informationECE 342 Electronic Circuits. Lecture 6 MOS Transistors
ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2
More informationUniversity of California at Berkeley College of Engineering Dept. of Electrical Engineering and Computer Sciences. EECS 40 Midterm II
University of California at Berkeley College of Engineering Dept. of Electrical Engineering and Computer Sciences EECS 40 Midterm II Spring 2001 Prof. Roger T. Howe April 11, 2001 Name: Last, First Student
More informationOperational Amplifiers
Operational Amplifiers A Linear IC circuit Operational Amplifier (opamp) An opamp is a highgain amplifier that has high input impedance and low output impedance. An ideal opamp has infinite gain and
More informationLecture Stage Frequency Response  I (1/10/02) Page ECE Analog Integrated Circuits and Systems II P.E.
Lecture 070 Stage Frequency esponse I (/0/0) Page 070 LECTUE 070 SINGLESTAGE FEQUENCY ESPONSE I (EADING: GHLM 488504) Objective The objective of this presentation is:.) Illustrate the frequency analysis
More informationFig. 1 Simple BJT (NPN) current mirror and its test circuit
1 Lab 01: Current Mirrors Total 30 points: 20 points for lab, 5 points for wellorganized report, 5 points for immaculate circuit on breadboard Note: There are two parts for this lab. You must answer the
More informationLecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:
Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I curve (SquareLaw Model)
More information