Dynamic Voltage and Frequency Scaling Under a Precise Energy Model Considering Variable and Fixed Components of the System Power Dissipation

Transcription

1 Dyamc Volage ad requecy Scalg Uder a recse Eergy Model Cosderg Varable ad xed Compoes of he Sysem ower Dsspao ABSRAC hs paper preses a dyamc volage ad frequecy scalg (DVS) echque ha mmzes he oal sysem eergy cosumpo for performg a ask whle sasfyg a gve execuo me cosra. We frs show ha order o guaraee mmum eergy for ask execuo by usg DVS s esseal o dvde he sysem power o fxed dle ad ve power compoes. ex we prese a ew DVS echque whch cosders o oly ve power bu also dle ad fxed power compoes of he sysem. hs s sharp coras o prevous DVS echques whch oly cosder he ve power compoe. he fxed plus dle compoes of he sysem power are measured by moorg he sysem power whe s dle. he ve compoe of he sysem power s esmaed a ru me by a echque kow as workload decomposo whereby he workload of a ask s decomposed o o-chp ad -chp based o sascs repored by a performace moorg u (MU). We have mplemeed he proposed DVS echque o he BsyX plaform; a Iel XA55- based plaform maufured by ADS Ic. ad performed dealed eergy measuremes. hese measuremes show ha for a umber of wdely used sofware applcaos a oal sysem eergy ss of up o 8% compared o a coveoal DVS echque ha cosders oly varable power s acheved whle sasfyg he user-specfed mg cosras.. Iroduco Demad for low power cosumpo baery-powered compuer sysems has rse sharply. hs s due o he f ha exedg he servce lfeme of hese sysems by reducg her power dsspao requremes s a key cusomer requreme. Low power desg s a crcal desg cosderao eve hgh-ed compuer sysems where expesve coolg ad packagg coss ad lower relably ofe assocaed wh hgh levels of o-chp power dsspao are he mpora cocers. Dyamc volage ad frequecy (DVS) echque has prove o be a hghly effecve mehod of achevg low power cosumpo for he CU whle meeg he performace requremes. he key dea behd he DVS echque s o dyamcally scale he supply volage level of he CU so as o provde jus-eough crcu speed o process he sysem workload whle meeg oal compuao me ad/or hroughpu cosras ad hereby reduce he eergy dsspao (whch s quadracally depede o he supply volage level). A umber of moder mcroprocessors such as Iel s XScale [] ad rasmea s Cruso [] are equpped wh he DVS fucoaly. here have bee exesve sudes of low power sysem desgs usg DVS echques [3]-[]. All of hese works have focused oly o he reduco of he CU power. However realy he baery lfeme of a VLSI crcu s also affeced by he fxed power cosumed oher compoes of he sysem. he valdy of hese sudes for low eergy sysem desg s based o he followg wo assumpos: () execuo me of a ask s exly proporoal o he verse of operag frequecy f as /f. () he sysem cosss of a sgle processor meag he processor power s equal o he sysem power ad s proporoal o he operag frequecy cubc way.e. f 3 wh he frs order relao bewee frequecy ad volage. Based o hese wo assumpos for performace ad power reducg processg speed always resuls he sysem eergy ss. Uforuaely hese wo assumpos may o be vald sce mos compug sysems currely avalable he marke are made up of several subsysems such as memory sysems ad oher perpheral compoes for user demads. hese subsysems have her ow operag clock frequecy ad volage levels. he heerogeey performace ad power of he sysem compoes make dffcul o apply DVS echques for such sysems. A umber of sudes [] - [8] repored ha due o asychroy bewee he memory access cycle ad he processor speed CU speed could be slowed dow wh lle mp of he oal execuo me whe he execuo me of a ask s domaed by he memory access me whch makes he assumpo () vald for memory-esve applcaos. urhermore whe power cosumed he subsysems s comparable o he CU power o slow dow he processg speed mgh cause more sysem eergy; eve CU eergy s saved because of he large fxed eergy cosumpo due o creased execuo me. hs paper preses a dyamc volage ad frequecy scalg (DVS) echque ha mmzes he oal sysem eergy cosumpo o perform a ask whle sasfyg a gve execuo me cosra. o guaraee mmum eergy for ask execuo usg DVS s mpora o dvde he sysem power o wo pars: fxed ad varable power. xed power represes he compoe of power ha remas uchaged durg he ask execuo. Examples clude DC-DC coverer power ad LL power as well as leakage power dsspaos. Varable power capures he compoe of he sysem power cosumpo ha chages wh me. Examples clude he CU ad memory power dsspaos as well as I/O coroller power. he varable power compoe s ur decomposed o wo subcompoes: dle ad ve power. As he ame mples ve (dle) power s he poro of varable power ha s cosumed whe he sysem s execug some (o) useful ask. We also defe sadg power as he summao of fxed plus dle power compoes of he sysem. DVS ca reduce oly he ve compoe of sysem power dsspao. If hs compoe s large compared o he sadg compoes of sysem power he lowerg he CU clock frequecy ad he reducg he supply volage of he CU (whle meeg a ask execuo me deadle) wll resul lower sysem eergy cosumpo due o he lear relao bewee he CU cycle me ad volage ad he quadrac relao bewee he CU power cosumpo ad volage. O he oher had f he ve compoe of sysem power s small compared o he sadg compoes he slowg dow he CU speed may f crease he sysem eergy cosumpo due o a crease he ask execuo me ad he domace of he sadg power dsspao compoes.

2 I hs paper we prese a ew DVS echque whch cosders o oly ve power bu also sadg power compoes of he sysem. hs s sharp coras o prevous DVS echques whch oly cosder he ve power compoe. he sadg compoes of he sysem power are measured by moorg he sysem power whe s dle. he ve compoe of he sysem power s esmaed a ru me by a echque kow as workload decomposo whereby he workload of a ask s decomposed o o-chp ad -chp based o sascs repored by a performace moorg u (MU) whch mos moder processors such as XScale8 [] or XA55 [5] come equpped wh. he proposed echque has bee mplemeed o a embedded sysem plaform bul aroud he XA55 processor. Dealed eergy s resuls have bee obaed by dog curre measuremes ual hardware. O hs plaform we performed a ask wh up o % less sysem eergy compared o he case wh ormal DVS echques whch cosder oly varable power. or boh CU ad memory-boud programs arge performace degradao was fely corolled. More precsely a opmal CU frequecy for a ask s deermed such ha he mmal sysem eergy s cosumed for he ask. he ma corbuos of our work are: () I preses he frs mplemeao of a DVS polcy for he oal sysem eergy reduco accoug for ve dle ad fxed sysem power compoes. () I preses a hghly accurae execuo me model for a ask a ru me by usg a embedded MU. (3) I preses a accurae power cosumpo model of he arge sysem based o workload decomposo wh less ha a 3% error. (4) Evaluao of he proposed mehod s performed hrough ual hardware measuremes for a umber of dffere applcaos. he remader of hs paper s orgazed as follows. Relaed work s descrbed Seco. I Seco 3 models for boh execuo me ad power dsspao usg workload decomposo are descrbed. Deals of arge plaform ad he proposed DVS polcy are preseed Seco 4 ad 5 respecvely. Expermeal resuls ad coclusos are gve Secos 6 ad 7 respecvely.. Relaed Work here have bee may sudes o DVS for eher real-me or o realme operaos. hey ca be dvded o may caegores eher erask [4][5][6][7] ad ra-ask [8][9] depedg o he scalg graulary or applcao-specfc [8][9] ad applcao o-specfc [3][5][6][7][] depedg o he modfcao of he applcao self or o. However all hese approaches solely focused o he CU eergy s based o he wo assumpos meoed he prevous seco; verse relaoshp bewee execuo me versus operag frequecy ad cubc relaoshp bewee he sysem power ad operag frequecy. here are dffere DVS approaches ha make use of he asychroy of memory access o he CU clock durg a ask execuo. I [] ad [3] compler-asssed DVS approaches were proposed whch frequecy s lowered memory-boud rego of a program wh lle performace degradao. DVS approaches ha rely o mcroarchecure or embedded hardware whou ay asssace from a compler or a smulaor have also bee repored. I [4] a mcroarchecure-drve DVS echque was proposed whch cache mss drves he volage scalg. I [5] IC (sruco per cycle) rae of a program execuo was used o gude he volage scalg. Referece [6] preseed a polcy o choose he opmal CU clock frequecy uder a fxed performace degradao cosra (of say %) based o dyamc program behavor such as he umber of execued srucos ad memory access cous durg he whole execuo me by usg a performace moorg u (MU). I [7] a DVS echque whch eables more precse eergy-performace rade- usg MU was preseed whch he opmal CU clock frequecy ad he correspodg mmum volage level are chose based o he rao of he o-chp compuao me o he -chp access me. A smlar DVS approach explog he rao of he ochp ad -chp access mes has bee proposed for he MEG decodg applcao [8]. hese approaches usg a MU requre o help from eher -le smulao or compler ad used dyamc eve cous from he MU oly. hese approaches also cosdered CU eergy reduco oly whou ocg he exsece of fxed power poro he sysem power. here are some works cosderg fxed power occurred by subcompoes usg DVS echques. Refereces [9] ad [] have suggesed ha power cosumpo he memory effecs should be ake o accou. Referece [] repored ha here s a lower boud o he CU frequecy such ha ay furher slowg dow degrades he amou of compuao ha ca be performed per baery dscharge. he auhors also allude o he problem ha he hgh cos of memory may domae he oal eergy cosumpo of a sysem such ha eve effecve DVS for he CU eergy s mgh be less effecve erms of he sysem eergy. 3. Workload Decomposo 3. Esmag he Execuo me of a ask Workload of a ask s defed as he sum of he CI s of all srucos he sruco sream of he ask. I depeds o varous dyamc parameers such as he o-chp sall cycle cou due o daa/corol depedecy or he brach mspredco ad he -chp sall cycle cou due o I/D cache mss or I/D LB mss. Some of hese eves resul a small overhead (e.g. cache h) whle ohers gve rse o a large pealy due o exeral memory access (e.g. cache mss). Durg a -chp access whch s asychroous wh respec o he CU clock he CU salls ul he requesed memory raso s compleed. hus CU clock cycles durg -chp access are wased whou dog ay useful work. urhermore he -chp access me s solely deermed by exeral access clock cycle o by he CU clock cycle. o llusrae he key po of he workload decomposo for he sysem eergy reduco we defe wo dffere ypes of workload: ochp ad -chp workload. Defo : O-chp workload W o s he umber of CU clock cycles requred o perform he se of o-chp srucos whch are execued sde he CU oly. he execuo me requred o fsh W o o vares depedg o he CU frequecy f cpu ad s calculaed as o = W o /f cpu. Defo : Off-chp workload W s he umber of exeral clock cycles eeded o perform he se of -chp accesses. oe ha he CU salls ul he exeral memory rasos are compleed (see dscusso abou ou-of-order execuo processors laer hs seco.). he execuo me requred o fsh W depeds o he exeral memory clock frequecy f ex ad s calculaed as = W /f ex. Based o defos ad W o ad W are wre as: W = CI W = M CI o o where CI o deoes he umber of CU clock cycles per o-chp sruco M s he umber of -chp accesses ad CI deoes he umber of exeral clock cycles per a -chp access. See Seco 5. for how o calculae hese wo CI s. rom hese wo defos he execuo me for a ask s calculaed as: o CIo M CI = = cpu ex () f f oce ha hs breakdow of he oal execuo me s o ex whe he arge processor suppors ou-of-order execuo whereby ()

3 srucos afer he sruco ha caused a -chp access may be execued durg he -chp access. I such a case o ad ca overlap. However prce he error roduced hs way s que small cosderg ha he memory access me s abou wo orders of magude greaer ha he sruco execuo me. herefore ouof-order execuo does o cause a large error eq. (). Whe he CU frequecy chages he chage s solely due o o : o = cpu cpu cpu f f f 3. Modelg he Sysem ower Cosumpo We cosder a compug sysem cossg of a CU wh a varable operag frequecy f where fm f f. Le max deoe he CU cpuf power dsspao a f. he sysem also cludes sysem modules. Le deoe he power dsspao of he h module. he we ca mod wre he followg: = = = dle = fx dle cpu f cpu f cpu f cpu cpu f cpu f mod mod mod mod mod s he ve poro of cpu f. cpu f s he sadg poro of cpu f whch s ur he summao of he dle poro ( dle cpu f ) plus cpu f he fxed poro ( fx ). cpu f s he ve poro of mod mod whe he h module s beg accessed whereas deoes he sadg poro of mod whe he h module s o accessed whch s equal o he dle mod compoe of he h module dle. Here s assumed ha he dle mod compoe ad he fxed compoe of power dsspao a sysem module are he same as oe aoher because geerally speakg he operag clock ad volage for he modules are o dyamcally vared bu hey rema fxed. he requred sysem eergy o complee a ask me wh a CU clock frequecy of f s gve by: sys f () sys f (3) (4) E = d (5) where sys f () s he me-varyg sysem power a f ad s ur calculaed as: () = () = () fx dle sys f sys sys f sys f sys f sys f = cpu f mod cpu f mod = = ( ) ( ) Here deoes he sadg sysem power cosumpo cpu f mod = whereas deoes he ve sysem power sys f cpu f () () mod = cosumpo sys f (). Geerally speakg s dffcul o accuraely calculae sys f () because he power requreme for each sruco s dffere. or example cosderg srucos he dyamc race of a applcao program rug o he sysem he CU s used o execue he o-chp workload whereas he memory s requred o execue he -chp workload. Whe o-chp ad -chp workload are execued radomly durg he program execuo sys f () should be severely flucuag as show gure (a). However oce workload of a ask s decomposed o o-chp ad -chp sys f () ca be modeled as: ( ) durg o cpu f sys f f () = sys f mod ( ) sys f durg = (6) (7) gure (b) shows sys f () afer workload decomposo. Hece E afer workload decomposo s gve as: sys f o E = sys f cpu f sys f f mod sys f = (8) I eq.(8) ad cpu f sys f ca easly be obaed from smple measuremes o he arge sysem by performg bechmark programs wh dffere CU frequeces bu s dffcul o ge () mod = because complee formao abou sysem compoes usage by he arge program s o avalable a ru me. I prce s () mod = approxmaed by memory power for geeral applcaos used hs paper because memory s he mos frequely-used sysem compoe ad he power cosumed he memory akes up more ha half of he sysem power our arge sysem. So we clude he power cosumpos of all oher sysem compoes. power () sys f sys f me 3 (a) whou workload decomposo power () sys f sys f cpu f mod = o f 3 me (b) wh workload decomposo gure : Sysem power cosumpo durg ask execuo () 3.3 Sysem Eergy vs. CU requecy As show eq.(8) E s a fuco of varous parameers of he sys f sysem cofgurao ( cpu f ad sys f ) ad applcao program mod ( o ad ). Depedg o hese parameers a opmal CU f frequecy whch resuls ask execuo wh mmum sysem eergy cosumpo s deermed as explaed ex. he sysem eergy equao (8) s rewre as: sys f mem o sys f Esys f = cpu f f o cpu f cpu f f where s memory power ad used sead of mem mod = (9) eq.(8) () as meoed before. he case whch ad are all zero s sys f equal o he suao assumed he prevous DVS works where purely CU-esve ask s execued o he sysem cossg of oly oe CU wh o sadg power. I ha case lowerg CU frequecy always resuls sysem eergy s. Assumg a lear relaoshp bewee he operag volage ad frequecy ( 3 cpu f f ad o - f f ) he followg form: Esys f mem becomes depede upo f as

4 E a f b f c sys f = () where a b ad c are cosa coeffces. I parcular b ad c represe he amous of sadg power he oal sysem power dsspaos. Subsequely a opmal CU frequecy whch gves he mmum sysem eergy f op s calculaed as 3.5 b/ a by akg he dervave of eq.(). If b s zero he f op creases. s f m bu f op creases as b 4. Descrpo of he arge Sysem 4. BsyX laform Our arge sysem for DVS s he BsyX sysem from ADS Ic. []. BsyX has a XA55 mcroprocessor whch s a 3-b RISC processor core wh a 3KB sruco cache ad a 3KB wre-back daa cache a KB m-cache a wre buffer ad a memory maageme u (MMU) combed a sgle chp. I ca operae from MHz o 4MHz wh a correspodg core supply volage of.85v o.3v. ower supply for he XA55 core s provded exerally hrough a o-board varable volage geeraor. here are e dffere frequecy combaos o 9. Each combao s gve as a 3-uple cossg of he processor clock frequecy (f cpu ) he eral bus clock frequecy (f ) ad he exeral bus clock frequecy (f ex ). hese frequecy combaos ad approprae CU volage levels are repored able. he eral bus coecs he core ad oher fucoal blocks sde he CU such as I/D-cache u ad he memory coroller whereas he exeral bus he arge sysem s coeced o SDRAM (64MB). able. requecy combaos BsyX sysem o f cpu (MHz) CU Vol. (V) f (MHz) f ex (MHz) Execuo me Model BsyX o derve a suable execuo mg model for BsyX fve dffere applcaos were ru over all frequecy ses o 9 ad he oal execuo me for each case was measured ad show gure. gure provdes he execuo me of all he applcaos for each frequecy seg ormalzed o he execuo me wh he maxmum performace seg.e. seg 7. rom gure we ca easly see ha mah crc ad djpeg are more CU-esve ha he gzp ad qsor applcaos sce lowerg he CU frequecy for hese applcaos roduce sgfca execuo me crease compared o gzp ad qsor cases. Comparg execuo mes of segs ad 3 (where oly he CU frequecy s dffere whle all oher clocks are he same) also valdaes hs observao. I f hs comparso allows us o deerme ha gzp s more memory-boud ha qsor by lookg a he execuo me varao accordg o CU frequecy oly. he same observaos ca be made by examg segs 4 5 ad 6 whch are aga oly dffere from each oher erms of he CU clock frequecy. I should be oed ha whe frequecy scalg s performed o oly f cpu s chaged bu also f ad f ex are scaled BsyX. herefore he effec of f ad f ex o he oal program execuo me should also be cosdered. Execuo me s sum of o ad as eq.() ad clearly s srogly depede o he exeral clock frequecy. However a mpora observao from daa repored gure s ha he eral bus clock frequecy also affecs. he relao bewee he eral bus clock ad ca be udersood from a closer examao of he operaos performed durg he exeral memory access. or example a D-cache mss requres wo operaos: daa fech from he exeral memory ad daa rasfer o he CU core where he cache-le ad desao regser are updaed. he me eeded for he laer operao s obvously affeced by he eral bus frequecy. Due o he lack of ex mg formao abou hese wo operaos ha are performed durg a D-cache mss servce we have oped o model as a fuco of boh he eral clock frequecy ad he exeral memory access clock as follows: α α = = ( ) W W ex () f f where α s he rao bewee he daa rasfer me ( ) ad he daa fech me ( ) ad f s eral bus clock frequecy. Execuo me (orm.) mah crc djpeg qsor gzp requecy combao gure : Execuo me varao over dffere frequecy combaos Based o he expermeal resuls o varous applcao programs he average error predcg he execuo me for all applcaos ad over all frequecy combaos was less ha % wh α value of.35 as show gure 3. Execo me esmao error [%] mah crc djpeg qsor gzp requecy combao gure 3: Execuo me esmao error 4.3 Eergy Cosumpo Model for BsyX Measured eergy cosumpos for each applcao are preseed gure 4. he frequecy combao a whch he mmum eergy s cosumed s o whch has he mmum CU frequecy of MHz for all esed applcaos. O he corary causes he larges sysem eergy amog all frequecy combaos. Eergy red accordg o frequecy ses s smlar o execuo me varao gure.e. less execuo me cause less sysem eergy. hs resul s due o he f ha here s he sadg compoe he oal sysem power durg ask execuo ad should be beer o fsh a program as soo as possble for less sysem eergy.

5 Oe more mpora observao gure 4 s ha hs mmal eergy frequecy s varyg depedg o applcaos eher CU-esve or memory-esve. or example 6 (CU frequecy of 4MHz) gves mmum eergy for he mah whch s he mos CU-esve whereas 9 (CU frequecy of 65MHz) does for he gzp whch s he mos memory-esve. he reaso why 9 s he bes for gzp s ha 9 has he fases codo for memory access operao boh memory clock ad eral bus clock are 33MHz. Eergy cosumpo (orm.) 3 mah crc djpeg qsor gzp requecy combao gure 4: Eergy cosumpo over dffere frequecy combaos Eergy cosumpo model BsyX s show gure 5. erms used hs fgure are explaed ex. : he h frequecy seg cpu ex ( f f f ) : o-chp compuao me a : daa updae me afer fech from memory a : daa fech me from memory a o sys () : me-varyg sysem power a : sadg power sys sys () o : ve power durg o sys : ve power durg sys : ve power durg sys V k k : CU operag volage a : fg coeffce for [] : fg coeffce for [V ] s represeed as cpu k V f k f sce power Here cosumpo durg s a fuco of he CU volage/frequecy for daa updae o he desao regser or I/D-Cache ad he volage level of he eral bus clock geeraor for daa rasfer o he CU (assumed o be 3.3V). k ad k are coeffces whch relaes wh CU frequecy/volage ad eral bus clock frequecy/volage respecvely. s obaed by measurg he sysem power all sys frequecy segs whe he sysem s dle. o whch s he ve compoe of he CU power s he dfferece bewee ad he sys measured power whe a CU-esve ask s rug. s he power cosumpo of accessg he memory. he ma memory has a oal sze of 64MB comprsg of wo 3MB SDRAMs. or each 3MB SDRAM we used daa shee values [3] of 446mW whe he SDRAM s beg accessed ad 3mW whe s he dle mode. herefore ca be calculaed as *(446mW-3mW)/.8 = 785mW where for of.8 represes he effcecy for for he DC- DC coverer (V o 3.3V coverso). We performed a curve fg procedure wh measured power values o ge k ad k ad foud hem o be.73 ad 6. respecvely. Exred parameers are summarzed able. able. Exred parameers for sysem eergy esmao sys (mw) sys (mw) o (mw) * *.33 power () sys o o = k V f k f cpu = o me 3 4 gure 5: oal sysem power cosumpo durg execuo he sysem eergy for a ask a E s gve as: sys E = o o sys sys () gure 6 shows he esmaed eergy cosumpo for djpeg usg eq () ad exred parameers over all frequecy combaos ad compared hese esmaed eergy values wh he ually measured oes. he average error rae for djpeg s less ha 4% ad for oher applcaos he error rae s abou 3%. Eergy cosumpo [J] 4 3 measured esmaed requecy combao gure 6: Accuracy of he proposed models for power cosumpo ad execuo me 5. roposed DVS olcy 5. Scalg graulary he deal DVS s supposed o saaeously chage he volage/frequecy values. I realy however akes me o chage he CU frequecy/volage due o some fors such as he eral LL (phase lock loop) lockg me ad capaces ha exs he volage pah. or he XA55 processor he laecy for swchg he CU volage/frequecy s 5usec [4]. I order o safely gore hs scale overhead he mmum quaum of me for scalg he CU frequecy/volage mus be a leas wo o hree orders of magude larger ha hs swchg laecy. A he same me we would lke o mmze he overhead of he volage/frequecy scalg as far as he OS s cocered. Correspodgly we use he sar me of a (OS) quaum (approxmaely 6msec Lux) used by he OS o schedule

6 processes as DVS decso pos ha s each me he OS vokes he scheduler o schedule processes he ex quaum we also make a decso so as o wheher or o he CU volage/frequecy s chaged ad f so we he scale he volage/frequecy of he CU. 5. Calculag he Average O-chp CI We calculaed he W o ad W of a program a ru me by usg he processor s MU. he MU u cosss of a clock couer ad wo oher couers each of whch ca moor oe of 5 dffere eves cludg cache h/mss LB h/mss ad umber of execued srucos. he overhead for accessg he MU (for boh read ad wre operaos) s less ha usec [6] ad ca hus be gored. Our approach s smlar o [7] where umber of memory bus rasos ad execued sruco cou were used o accuraely esmae he ochp CU. Sce he MU XA55 does o provde suppor for coug he umber of memory bus rasos we have used he followg hree eves based o exesve expermes: () umber of srucos beg execued (ISR) ad () umber of sall cycles due o daa depedecy (SALL) () umber of D-cache mss (DMISS). A he ed of every quaum ISR ad SALL eve sascs alog wh he umber of clock cous a quaum (CC) whch s gve by he clock couer are read from he MU. rom hese values we calculae he average CU clock cycles per sruco (CI ) as CC/ISR. Smlarly average umber of salls per sruco (SI ) s calculaed. SI accous for boh he o-chp salls (SI o) ad he -chp salls (SI ). gure 7 shows he plo wh SI of each quaum o he x-axs ad he CI o he y-axs for gzp applcao. rom hs fgure we ca easly see ha CI s learly relaed o SI as follows: CI = k SI c (3) where k s he slope (~). oce ha he y-ercep c s equal o he average o-chp CI whou ay sall cycles CI m o. CI gzp CI o m CI o SI max SI m CI o gure 7: Coour plos of CI versus SI for dffere clock frequeces combaos o oba CI o we eed o exr SI o from SI. o do hs we cosder he y-ercep of he above le he CI whe o daasalls occur as he lower boud for he o-chp CI (CI m o). he CI a he lowes SI value (SI m ) s cosdered as he upper boud (CI max o). he CI o s esmaed from boh CI m o ad CI max o alog wh he values of DMISS of he quaum. he uo for usg DMISS o calculae CI o s ha f he umber of daa cache msses s hgh mos of he salls are -chp salls. herefore f he value of DMISS s hgh (low) he a CI value close o CI m o (CI max o) s chose. Le DI deoes D-cache mss cou per sruco defed as DMISS/ISR. We equally dvded he rego from CI max o o CI m o o sub-regos ad each rego s seleced wh he repored DI value whch resuls CI o = CI m CI (DI) where CI (DI) s CI value for he correspodg DI ad creases (decreases) as he DI value decreases (creases). Our DVS approach requres hree eves: ISR SALL ad DMISS. Sce XA55 s MU ca oly provde wo eve sascs a a me he MU mus be read wce every quaum: (ISR SALL) par s read durg he frs half whereas (ISR DMISS) par s read durg he secod half of every quaum. 5.3 Deermg he Opmal requecy Seg I he proposed DVS polcy a opmal frequecy s deermed cosderg boh he mg cosras ad mmum sysem eergy cosumpo. As a mg cosra for o real-me applcaos we used performace loss ( loss ) whch s defed as he creased execuo me of a program due o lowered clock frequecy ad gve as [6][7]: where ad max ad max loss = ( ) max max (4) s he bes performace frequecy combao.e. 7 max are he oal ask execuo me a frequecy combao of respecvely. Afer obag he CI value for he curre quaum CI o we calculae o-chp ad -chp execuo mes for hs quaum o ad as follows: o CIo o = = cpu (5) f where s he umber of execued srucos ad f cpu are he execuo me ad he CU frequecy durg he quaum respecvely. W o ad W are derved from he calculaed values of o ad based o defo eq.() ad eq.(). I s assumed ha W o ad W are equal o W o ad W respecvely. A opmal frequecy se for he quaum op s deermed as followg:. Ψ = { 9 } Γ = {φ } ad E m =. for every frequecy seg Ψ 3. f ( Z4: ( loss ) ) 7 4. Γ = Γ ; 5. for every frequecy seg Γ 6. calculae E from eq.() sys 7. f ( E E m ) sys 8. E m = E ; op = ; sys where Z4: s he expeced execuo me of quaum a ad s he execuo me of quaum a 7. ) 7 6. Expermeal Resuls We mplemeed he proposed polcy o he BsyX plaform whch rus Lux (v.4.7). recsely speakg we wroe a sofware module mplemeg he proposed polcy. hs module s ed o he lux OS scheduler order o allow volage scalg o occur a every coex swch. o show he effecveess of he proposed DVS mehod cosderg sysem eergy (SE-DVS) we also mplemeed he DVS mehod used [7] whch cosders CU eergy oly (CE-DVS) ad compared he resuls each oher. o measure he power cosumpo of he sysem we sered a.5 ohm precso ressor bewee he exeral power source (~V) ad he sysem power le. he ual power cosumpo a ru me was measured by usg a daa acquso sysem whch operaes up o KHz samplg frequecy by readg volage drop across he precso ressor [6]. Our expermes are performed o a umber of

7 applcaos cludg a commo UIX uly program gzp ad four represeave bechmark programs avalable o he web [7]. gure 8 represes he measured performace degradao wh arge performace loss ragg from % o 5% a seps of % for boh CE-DVS ad SE-DVS. As see hs fgure usg CE-DVS case (a) we obaed ual performace loss values very close o he arge values for all programs (.e. ual average wh.5% of he arge) whereas performace loss values obaed usg SE-DVS are sauraed o % ad % for CU-esve ad memory-esve applcaos respecvely eve wh 5% arge. hs s due o sgfca fxed power he arge sysem ad s beer o fsh ask as soo as possble erms of oal sysem eergy s. gure 9 shows he acheved sysem eergy s wh (a) CE-DVS ad (b) SE-DVS rug bechmark programs a varous performace loss values. Sysem eergy s s calculaed by comparg measured sysem eergy applyg DVS mehod wh ha of whou ay DVS mehod case whch programs were ru a 7. rom hs fgure s foud ha sysem eergy creased for all applcaos by applyg CE- DVS whereas here are eergy ss for mah crc ad gzp programs case of SE-DVS ad lle chages he sysem eergy are observed djpeg ad qsor. hese resuls are correspodg o daa gure 4. or example he frequecy se for mmum eergy cosumpo of djpeg s 6 ad CU frequecy of 6 4MHz s he same as 7. CE-DVS does o cosder he sysem eergy bu oly cocers mg cosra. So as arge performace creases less frequecy se s chose by CE-DVS resulg sysem eergy crease. hs s o he case SE-DVS so ha mmum sysem eergy s maaed by usg SE-DVS. gure depcs he power cosumpo waveform of he BsyX sysem whe rug gzp wh 3% arge performace degradao for usg: (a) CE-DVS ad (b) SE-DVS. I case (a) usg CE- DVS he average power s less ha ha of case (b) sce ve power s reduced. Bu due o creased fxed eergy by lowered frequecy oal sysem eergy creased case of CE-DVS. or hs applcao SE-DVS requres.4% less sysem eergy ha ha of CE-DVS. or oher applcaos wh dffere performace arge values are show gure ad abou % o 8% of oal sysem eergy s reduced by usg SE-DVS compared wh he resuls of usg CE-DVS. rom hese measuremes we coclude ha our proposed SE-DVS echque s que helpful o exed he whole sysem lfeme. 7. Cocluso I hs paper a DVS polcy for he ual sysem eergy reduco was proposed ad mplemeed o a XA55-based plaform. I he proposed DVS approach a program execuo me ad sysem eergy requred for he program are que accuraely esmaed usg workload decomposo whch execuo me of he program s decomposed o o-chp compuao ad -chp access laeces. Sysem power s also decomposed o varable ad fxed power ad very accuraely esmaed usg decomposed execuo me. he CU volage/frequecy s scaled based o he rao of he o-chp ad chp laeces for each process such ha boh a gve performace degradao for ad mmal eergy cosumpo are sasfed. hs rao s gve by a regresso equao whch s dyamcally updaed based o rume eve moorg daa provded by a embedded performace moorg u. hrough ual curre measuremes hardware we demosraed ha up o % less eergy s was acheved wh he proposed DVS compared wh he resuls he prevous DVS echques. or boh CU ad memory-boud programs gve mg cosras were also sasfed. Acual performace [%] Acual performace [%] arge loss % % 3% 4% 5% mah crc djpeg qsor gzp (a) coveoal DVS (CE-DVS) arge loss % % 3% 4% 5% mah crc djpeg qsor gzp (b) proposed DVS (SE-DVS) gure 8: Acual performace: CE-DVS ad SE-DVS Sysem eergy s [%] Sysem eergy s [%] mah crc djpeg qsor gzp arge loss % % 3% 4% 5% (a) CE- DVS mah crc djpeg qsor gzp arge loss % % 3% 4% 5% (b) SE- DVS gure 9: Sysem eergy s: SE-DVS ad CE-DVS

8 ower cosumpo [mw] ower cosumpo [mw] gzp wh 3% arge loss. power : 69mW 6.53sec Eergy : 7.5J me [sec] (a) CE- DVS gzp wh 3% arge loss. power : 7.3mW 5.568sec Eergy : 5.47J me [sec] (b) SE- DVS gure : Acual power cosumpo of wo DVS mehods Sysem eergy dfferece [%] 3 arge loss % % 3% 4% 5% mah crc djpeg qsor gzp gure : Sysem eergy dfferece: SE-DVS vs. CE-DVS 8. REERECES [] Developer maual: Iel 8 rocessor Based o Iel XScale Mcroarchecure hp://developer.el.com/desg/o/mauals/734.hm [] Cruso SE rocessor M58 Daa Book v. hp:// mly.hml. [3]. Yao A. Demers ad S. Sheker Schedulg model for reduced CU eergy IEEE Aual oudaos of Compuer Scece pp [4] Y. Sh ad K. Cho ower coscous fxed prory schedulg for hard real-me sysems roc. of he 36 h Aual Desg Auomao Coferece pp [5] I. Hog G. Qu M. okojak ad M. B. Srvasava Syhess echques for low-power hard real-me sysems o varable volage processor roc. of he 9 h IEEE Real-me Sysems Symposum pp [6]. Ishhara ad H. Yasuura Volage schedulg problem for dyamcally varable volage processors roc. of he Ieraoal Symposum o Low ower Elecrocs ad Desg Moerey pp.97- Aug [7] G. Qua ad X. Hu Mmum eergy fxed-prory schedulg for varable volage processors roc. of Desg Auomao ad es Europe pp Mar.. [8] D. Sh J. Km ad S. Lee Low-eergy ra-ask volage schedulg usg sac mg aalyss roc. of Desg Auomao Coferece pp [9] S. Lee ad. Sakura Ru-me power corol scheme usg sofware feedback loop for low-power real-me applcaos roc. of Asa-acfc Desg Auomao Coferece pp [] M. Weser B. Welch A. Demers ad S. Sheker Schedulg for reduced CU eergy roc. of he s Symposum o Operag Sysems Desg Implemeao pp [] K. Govl E. Cha ad H. Wasserma Comparg algorhms for dyamc speed-seg of a low power CU roc. of he s ACM I l Coferece o Moble Compug ad eworkg pp [] C. Hsu ad U. Kremer Compler-dreced dyamc volage scalg for memory-boud applcaos echcal Repor DCS-R-498 Deparme of Compuer Scece Rugers Uversy Aug.. [3] C. Hsu ad U. Kremer Sgle rego vs. mulple regos: A comparso of dffere compler-dreced dyamc volage schedulg approaches roc. of Workshop o ower-aware Compuer Sysems eb.. [4] D. Marculescu O he use of mcroarchecure-drve dyamc volage scalg roc. of Workshop o Complexy-Effecve Desg Ju.. [5] S. Ghas J. Casmra ad D. Gruwald Usg IC varao workloads wh exerally specfed raes o reduce power cosumpo roc. of Workshop o Complexy Effecve Desg Ju.. [6] A. Wssel ad. Bellosa rocess Cruse Corol CASES Greoble race Oc.. [7] K. Cho R. Soma ad M. edram e-graed dyamc volage ad frequecy scalg for precse eergy ad performace rade- based o he rao of -chp access o o-chp compuao mes roc. of Desg Auomao ad es Europe 4. [8] K. Cho R. Soma ad M. edram Off-chp laecy-drve dyamc volage ad frequecy scalg for a MEG decodg roc. Of Desg Auomao Coferece 4. [9]. Mar Balacg baeres power ad performace: Sysem ssues CU speed-seg for moble compug hd hess Carege Mello Uversy 999. []. L. Mar D.. Seworek ad J. M. Warre A CU speed-seg polcy ha accous for odeal memory ad baery properes roc. 39 h ower Sources Coferece pp.5-55 Ju.. [] J. ouwelse K. Lagedoe ad H. Sps Dyamc volage scalg o a low-power mcroprocessor he 7 h Aual Ieraoal Coferece o Moble Compug ad eworkg pp [] hp:// [3] hp://dowload.mcro.com/pdf/daashees/dram/sdram/56msdram_g.pdf [4] Developer s maual: Iel XScale Mcroarchecure for he XA55 rocessor hp:// hm [5] User s maual: Iel XScale Mcroarchecure for he XA55 rocessor hp:// hm [6] hp:// [7] hp://