RESOLVER (D/R) CONVERTERS

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1 HIGH POWER 1-BIT digital-to- RESOLVER (D/R) CONVERTERS FEATURES Make sure the next Card you purchase has... VA Drive Capacity 8-Bit/-Byte Double Buffered Transparent Latch Resolution: 1 Bits Accuracy: to 1 Minute Power Amplifier Uses AC Reference or DC Supplies BIT Output DESCRIPTION The is a 1 bit, pin triple DIP Digital-to-Resolver converter with VA drive capability. It features a power amplifier that may be driven by a standard ±1 VDC power supply or by the reference source (when used with the optional power transformer DDC/PN 90). The provides compatibility with microprocessors through its 8-bit -byte transparent input latch. Data input is natural binary angles in TTL compatible parallel positive logic format. The is comprised of a high accuracy Digital-to-Resolver converter and a dual power amplifier stage that has high accuracy and low scale factor variation. In addition, a standard BIT circuit provides a digital overcurrent signal output. A logic 0 BIT output indicates an overcurrent condition in the sine or cosine outputs. Reference inputs are scalable with external resistors. Loss of the reference signal will not damage the converter. APPLICATION The can be used where digitized shaft angle data must be converted to an analog format for driving control transformers. With its built-in input latches, the is especially compatible with a microprocessorbased system including flight simulators, flight instrumentation, fire control systems, radar and navigation systems, and air data computers. 10 Wilbur Place Bohemia, New York Fax: 1--8 FOR MORE INFORMATION CONTACT: Technical Support: DDC- ext. 1 All trademarks are the property of their respective owners. 198, 1999

2 R H R L LA LM +1 V DC -1 V DC +V OR +1 -V OR -1 D/R CONVERTER HIGH ACCURACY LOW SCALE FACTOR VARIATION S C DUAL HI POWER AMPLIFIERS SIN COS OPTIONAL SCOTT-T TRANSFORMER BIT 1-1 BIT TRANSPARENT LATCH LOGIC "0" INDICATES OVER CURRENT TRANSPARENT LATCH BITS 1-8 BITS 9-1 LL FIGURE 1. BLOCK DIAGRAM SYNCHRO OUTPUT

3 table 1. drc-100 specifications Apply over temperature range power supply ranges reference voltage and frequency range and 10% harmonic distortion in the reference. PARAMETER RESOLUTION ACCURACY AND DYNAMICS Output Accuracy Without Scott-T With Scott-T P/N90 Differential Linearity Output Settling Time DIGITAL INPUT/OUTPUT Logic Type Logic Voltage level Load Current Timing REFERENCE INPUT Type Voltage Frequency Input Impedance Single Ended Differential ANALOG OUTPUT Type Output Current Max Output Voltage (tracks reference input voltage) 1 bits VALUE ±1 or ± minutes ±10 minutes (1. VA min for CT load) ±1 minutes ( VA min for CT load) ±1 LSB Less than 0 µsec for any digital input step change Natural binary angle parallel positive logic CMOS and TTL compatible. Inputs are CMOS transient protected. Logic 0 = 0 to +0.8 V Logic 1 = V to 1/ of VDD + 10% 0 µa max (bit 1-1) µa max (LL LM LA) See Timing Diagram (FIGURES A&B ). (Note ) Differential. V rms Higher voltages are scaled by adding series resistors DC to 1 khz 1 kω ±0.% kω ±0.% Resolver 00 ma rms min ( VA min) (NOTE ).8V rms max line-to-line ±1% (SEE NOTE ) NOTES for Table 1: 1) 00ma per P/S is in relationship to driving torque loads. Large step torque loads can cause converter to pull max current. For these conditions the converter seat sink protection is very important. A solution to combat large step torque loads is to convert the large steps in position change to occur over smaller steps which will decrease peak P/S currents. ) Output voltage can be scaled by lowering reference voltage. Factory set for fixed factor of. Example:.V Ref x "scale factor" =.8V Output. ) Power calculation examples for SIN/COS VA total output power: Example to calculate the load for SIN/COS VA as follows. At, Sin = Cos VA = 1VA (Sin) + 1VA (Cos) SIN = 0.0, COS = x (Output Voltage).8V =.8 V 1VA/.8V =.08A.8V/.08A = ohms (Load Impedance) At 0, 90, etc., when either sin or cos is maximum amplitude, the maximum current for a VA load is:.8v/ ohms =.9A Example for 80 The load impedance is.1 ohms: Sin dissipates V * (1.1808V/.1ohms) =.0VA Cos dissipates.9v * (.9V/.1ohms) = 1.9VA Total = = VA Scale Factor Variation DC Offset (each line to ground) Protection Simultaneous amplitude variation in all output lines as function of digital angle is ±0.1% max. ±1 mv max varies with input angle. Output is protected from overcurrent short circuits and voltage feedback transients. At 90 degree, sin=1, cos=0, sin(90)*.8*a=va >max current for sin signal=/.8=0.9a, no current for cos signal Z=.8/.9=.1ohm TECHNICAL INFORMATION INTRODUCTION POWER SUPPLIES Voltage Voltage Limits Max Voltage Without Damage Current Peak Current At Power Turn On or Short Circuit (when using Transformer) TEMPERATURE RANGES Operating (-xx) (-1xx) Storage PHYSICAL CHARACTERISTICS Package Type Size Weight +1V -1V +V -V +% +% 0 V peak max V above output voltage min. +18V -18V +V -V 0 ma 0 ma load dependent max max 00 ma max (*See Note 1) 0 C to +0 C case - C to +1 C case - C to +1 C pin triple DIP 1.1 x 1. x 0.18 inch (9 x x mm) 1.1 oz ( g) The is a digital-to-resolver (D/R) converter which has an inherently high accuracy and low scale factor variation. The circuit is based on an algorithm whose theoretical math error is only ±. arc seconds and whose theoretical scale factor variation with angle is less than ±0.01%. Therefore accuracy and scale factor are limited only by the physical components, not by the algorithm. The digital inputs are CMOS double buffered transparent latches (FIGURE 1). Angular output is determined by adding bits in the logic 1 state. Power SUPPLY CYCLING Power supply cycling of the DDC converter should follow the guidelines below to avoid any potential problems. Strictly main-

4 tain proper sequencing of supplies and signals per typical CMOS circuit guidelines: - Apply power supplies first (+1, -1V and ground). - Apply digital control signals next. - Apply analog signals last. The reverse sequence should be followed during power down of the circuit. scaled by calculating the value of the scaling resistor with the following equation: REF INPUT R REF R REF R H R L REFERENCE LEVEL ADJUSTMENT The input is specified for operation at a reference level of.v rms; however, reference levels other than.v rms may be (V REF -.) R REF =. x 1k ( -.) eg., if V REF = V rms, then R REF = x 1k. 00 ns min. TRANSPARENT LATCHED DATA 1-1 BITS 1 ns min. With LA set Lo = 1 ns min. With LL, LM, LA tied together = 00 ns min. Data Changing Data Stable FIGURE A. LL, LM, LA TIMING DIAGRAM (1 BIT) LA 00 ns min. 00 ns min. 00 ns min. LM Bits (1-8) 00 ns min. LL Bits (9-1) DATA 1 ns min. 1 ns min. 1 ns min. 1 ns min. LA, LM, LL Transparent = Hi Latched = Lo Data Changing Data Stable FIGURE B. LL, LM, LA TIMING DIAGRAM (8 BIT)

5 The output is.8v rms line-to-line resolver format signal which may be converted into a synchro format of 11.8V Iine-to-line with the companion Scott-T transformer module available as DDC P/N 90. DRIVING THE POWER AMPLIFIER WITH THE REFERENCE The high power amplifier stage can be driven by a standard ±1V DC supply or with a high efficiency pulsating power supply derived from the reference voltage source. A companion power transformer DDC P/N 90, designed to implement the pulsating power source for the, is also available (FIGURE ). The will not be damaged by sequencing order in the ±1V, V L supplies or the reference input. OUTPUT PROTECTION AND BIT The output is protected from overcurrent, short circuits and voltage feedback transients. The BIT circuit detects overcurrent conditions in the sine or cosine resolver output. A logic 0 is used for overcurrent detection. Normal operation is logic 1. The BIT line is normally at logic 1. An overload or short circuit will cause the BIT line to drop after 1 sec when the output current exceeds a peak level of approximately 0 ma. OUTPUT PHASING AND OUTPUT SCALE FACTOR The analog output signals have the following phasing: sin = (R h -R l ) A o [1 + A (θ)] sin θ cos = (R h -R l ) A o [1 + A (θ)] cos θ The output amplifiers simultaneously track reference voltage fluctuations because they are proportional to (R H -R L ). The amplitude factor A o is for.8v rms L-L output. The maximum variation in A o from all causes is 0.%. The term A (θ) represents the variation of the amplitude with the digital input angle. A (θ), which is called the scale factor variation, is a smooth function of θ without discontinuities and is less than ±0.1% for all values of θ. The total maximum variation in A o [1 + A (θ)] is therefore ±0.%. Because the amplitude factor (R H -R L ) A O [1 + A (θ)] varies simultaneously on all output lines, it will not be a source of error when the is to drive a ratiometric system such as a resolver or synchro. However, if the outputs are used independently, as in x-y plotters, the amplitude variations must be taken into account. TABLE. PIN CONNECTIONS pin function pin function pin function N.C. N.C. 1 (LSB) COS SIN +V -V 1 (MSB) LM LL Rl Rh 1-1 V GND LA +1 V BIT N.C.. Vrms REFERENCE SOURCE 00 Hz 1 T Vrms C.T. D1 D PARTS LIST FOR 00 Hz For T1 and T see Ordering Information D1, D, D, and D = 1N C-1 and C- = µf, V DC capacitor D D C-1 + V DC C- + R L +V GND -V R H DIGITAL INPUT +SIN +COS ±1 V 1.8 Vrms S T- R *99 RESOLVER figure. typical connection diagram utilizing pulsating power source for synchro output S 1 (SYNCHRO ONLY) S S (RESOLVER ONLY) S

6 THERMAL CONSIDERATIONS The power stage consists of two power amplifiers: one for the sine output and one for the cosine output. Maximum power stage junction temperature rise occurs at 0 and 180 for the sine output and 90 and 0 for the cosine output. Maximum power dissipation for the hybrid occurs at the interquadrant points:, 1,, and 1. At these points the total power dissipation of each amplifier is 0.0 max. Therefore, the total power dissipation is 1.1 times the max for any one amplifier. The thermal resistance junction to the outside of the case is 10. C/W. For a VA purely inductive load and ±1 VDC power supplies, the junction temperature rise is C. For a real inductive load (one that has some power dissipation) and using pulsating supplies, the power dissipated is cut in half. The temperature rise is also halved to 1 C MAX (.) 0.90 MAX (.8) 0.10 TYP (.81) 0.00 ±0.010 (1. ±0.) 0.00 (.) (1) ±0.00 (0. ±0.1) 0.00 ±0.010 (1.8 ±0.) BOTTOM VIEW () () () () () 0.09 TYP (.1) 0.00 TYP (1.) TYP (.) TOL NON-CUM (1) () () () 1.90 MAX (8.) (.18 0.) (0. 0.) BOttOM VIEW () () () 0.0 TYP (0.1) 0.00 TYP (1.) TYP 0.0 (.08) 0.0 (10.1) 0.90 MAX (.8) (8) (1. 0.) () TERMINALS 0.00 ±0.00 (0.1 ±0.0) x 0.18 MIN LG. BRASS SOLDER PLATED -0 INSERT INTERNAL THREADS TYP (.) TOL NON-CUM TERMINALS ( ) x 0.18 MIN LG. BRASS SOLDER PLATED PIN 8, 99 ONLY -0 INSERT INTERNAL THREADS side VIEW 0. MAX (1.1) SIDE VIEW 0. MAX (1.1) FIGURE. POWER TRANSFORMER (90, 90) MECHANICAL OUTLINE FIGURE. OUTPUT SCOTT-T TRANSFORMERs (90, 9) Mechanical outline Freq. Range TABLE. TRANSFORMER INFORMATION POWER TRANSFORMER SCOTT-T TRANSFORMER Hz ±10% for all transformers Drive VA for all transformers Input (1-) V 11V.8V.8V.8V Output see note 1 see note 1 Synchro 11.8 V L-L Resolver 11.8 V L-L Synchro 90 V L-L Phase Shift note note Rated Load (over - to +1 C) Dielectric withstanding volt. (between windings) 1.1 VA min;.0 VA 1 min 0 0 Hz 00 0 Hz 00 0 Hz.0 VA min 00 0 Hz 1.1 VA min 00 0 Hz Weight 1 oz. 1 oz..0 oz..0 oz..0 oz. Notes: 1. (--) 0.8 volts Centertapped,.% Regualtion over temperature range. (-). volts, % Regulation over temperature range.. Max from winding 1- to - is for ambient temperature - to +1 C.

7 Table. ANGLES IN DEGREES CROSS REFERENCED TO A 1-BIT DIGITAL WORD degrees (hex) 0 (0000) 1 (0AAB) 0 (1) (000) 0 (AAB) () 90 (000) 10 () 1 (000) 180 (8000) 0 (AAAB) 0 (C000) 8 (CAAB) 00 (D) 1 (E000) 0 (EAAB) (F) 9 (FFFF) 1 bit digital word (φ) (1 = MSB, 1 = LSB) (8.9) (.8) MIN (.) 0.1 MAX (.) 1.0 (.0) 1 EQ. SP = 1.00 TOL NUN-CUM (. = 8.1) ±0.00 (.0 ±0.0) 0.10 ±0.00 (.0 ±0.0) BOTTOM VIEW NOTES: 1. Dimensions shown are in inches (millimeters). Lead identification numbers are for reference only.. Lead cluster shall be centered within ±0.010 (±.) of outline dimensions. Lead spacing dimensions apply only at seating plane.. Pin material meets solderability requirements of MIL-PRF-8, Method 00.. Tol ±0.00 (±0.1) unless otherwise noted ±0.00 DIA (TYP) (0. ±0.0) SIDE VIEW FIGURE 8. MECHANICAL OUTLINE ( PIN TRIPLE DIP)

8 ORDERING INFORMATION -XXXX Supplemental Process Requirements: S = Pre-Cap Source Inspection L = Pull Test Q = Pull Test and Pre-Cap Inspection Blank = None of the Above Accuracy: = Minutes = Minutes = 1 Minute Process Requirements: 0 = Standard DDC Processing, no Burn-In (See table below.) 1 = MIL-PRF-8 Compliant = B* = MIL-PRF-8 Compliant with PIND Testing = MIL-PRF-8 Compliant with Solder Dip = MIL-PRF-8 Compliant with PIND Testing and Solder Dip = B* with PIND Testing = B* with Solder Dip 8 = B* with PIND Testing and Solder Dip 9 = Standard DDC Processing with Solder Dip, no Burn-In (See table below.) Temperature Grade/Data Requirements: 1 = - C to +1 C (Case) = -0 C to +8 C (Case) = 0 C to +0 C (Case) = - C to +1 C (Case) with Variables Test Data = -0 C to +8 C (Case) with Variables Test Data 8 = 0 C to +0 C (Case) with Variables Test Data *Standard DDC Processing with burn-in and full temperature test see table below. These products contain tin-lead solder finish as applicable to solder dip requirements. Standard ddc processing For Hybrid and Monolithic Hermetic Products test INSPECTION SEAL TEMPERATURE CYCLE CONSTANT ACCELERATION BURN-IN Method(s) 101 (note 1), 100 (note ) 000g TABLE 1 Notes: 1. For Process Requirement "B*" (refer to ordering information), devices may be non-compliant with MIL- STD-88, Test Method 101, Paragraph.. Contact factory for details.. When applicable MIL-STD , 010, 01, and 0 condition(s) A and C C 8

9 The information in this data sheet is believed to be accurate; however, no responsibility is assumed by for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications are subject to change without notice. Please visit our web site at for the latest information. 10 Wilbur Place, Bohemia, New York 111- For Technical Support DDC- ext. 1 Headquarters, N.Y., U.S.A. - Tel: (1) -00, Fax: (1) -8 United Kingdom - Tel: +-(0) , Fax: +-(0)1- France - Tel: +-(0)1-1-1-, Fax: +-(0) Germany - Tel: +9-(0) , Fax: +9-(0) Japan - Tel: +81-(0)-81-88, Fax: +81-(0) World Wide Web - U RE GIS T E R E D FIR M 9 DATA DEVICE CORPORATION REGISTERED TO ISO 9001:000 FILE NO. A9 PRINTED IN THE U.S.A.

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