An Analytical Approach to Efficient Circuit Variability Analysis in Scaled CMOS Design
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1 An Analyical Approach o Efficien Circui ariabiliy Analysis in Scaled CMOS Design Samaa Gummalla, Anupama R. Subramaniam, Yu Cao, Chaiali Chakrabari School of Elecical, Compuer and Energy Engineering, Arizona Sae Universiy, Tempe, AZ 8587, USA ycao@asu.edu, sgummall@asu.edu, anupama.r.subramaniam@asu.edu Absac CMOS scaling has led o increasingly high variabiliy in device and circui performance. To improve design robusness, i is imporan o consider variaion in e design flow. In is paper a closed-form soluion is proposed o predic e variabiliy in gae iming, which significanly reduces compuaion cos in saisical analysis. The proposed model covers bo nominal delay and is variabiliy across a wide range of device sizes, load capaciances and inpu ansiion imes. Sack effec, such as a in NAND and NOR gaes, is aken ino accoun ereby making e model sensiive o e swiching paerns. For ISCAS'85 benchmark circuis, implemened using a 45nm library, e model demonsaes high accuracy wi less an 3.5 error for nominal delay and wiin 5ps variaion of e criical pa. Finally, use of e proposed model in design flow is demonsaed for seup ime violaions. eywords Timing model, variaion, saisical analysis, criical pa.. Inoducion As CMOS echnology nodes shif owards 45nm and below, process variaions increase significanly causing high variabiliy in circui performance and us reducing manufacuring yield. To improve design robusness e effec of variabiliy should be accouned for during e design flow. Conservaive design for an approimaed wors case performance is no recommended because high variabiliy in scaled echnologies leads o over designing. Analyzing variabiliy in comple circuis rough SPICE simulaions consumes enormous run ime. Wha is needed is an accurae analyical model o predic variabiliy very fas so a i could be inegraed ino e design flow. There are many analyical models [-6] o predic delay under nominal condiions. Bu ese models do no ake ino accoun e effec of variabiliy, which is criical in fuure echnology nodes [7]. Also mos of e work done on variabiliy analysis has been confined o inverer; oer gaes are simplified ino equivalen inverers rough logical effor [8-9]. This approach, ough simple, is no accurae and canno be easily eended o comple gaes. In is paper, a closed form soluion o esimae nominal delay and delay variabiliy due o variaions in reshold volage, is proposed. The model is verified eensively wi SPICE Mone Carlo simulaion resuls a 45nm wi Predicive Technology Models (PTM [0]. In is paper, This work was suppored in par by NSF CSR /0/$ IEEE An accurae analyical delay model is derived for CMOS inverer as a funcion of gae wid, load capaciance and inpu ansiion ime (Secion..The analysis is eended o NAND and NOR gaes o accoun for sacking effec (Secion.. Analyical model, for esimaing delay variabiliy due o reshold volage variaions, is developed for inverer and NAND gaes (Secion 3. The model shows good correlaion wi SPICE simulaions. The accuracy of e model is demonsaed rough small circuis like XOR as well as comple ISCAS 85 benchmark circuis. For e benchmark circuis, nominal delay for criical pas is prediced wiin 5 error compared o Synopsys prime ime esimaed value using 45nm echnology library [] (Secion 4.. Use of e proposed model ino e design flow is demonsaed. I is shown how possible iming errors due o variabiliy can be easily idenified (Secion Nominal Delay Model.. Timing Model for Inverer To derive e nominal delay model for a basic inverer a scaled echnologies, e sandard curren equaions using Shockley s MOSFET model or Alpha-Power law MOSFET model canno be used. This is because as e sauraion curren is no consan for echnology nodes below 50nm due o channel leng modulaion. The following curren equaion from [] which considers channel leng modulaion, is used o develop e analyical delay model. 0, ( GS : cuoff, I D βl ( in DS, ( DS < : linear, β S ( in [ + ( DS ], ( DS : sauraion ( is e velociy sauraion inde and is considered o be for e echnology nodes considered. is e empirical channel leng modulaion facor. is e reshold volage of e NMOS device. I D0 is e drain curren a GS DS. is e drain sauraion volage a GS. Since e operaing range of is very small for echnologies under 45nm and does no vary much in is range, is also considered o be e sauraion volage for all GS as in []. The delay model is developed for oupu high o low (H delay: T phl for an inverer and e same model is applicable for oupu low o high (H delay as well. Inpu of e inverer, in is considered o be a linear rising ramp 3 In l Symposium on Qualiy Eleconic Design
2 wave driven by an acive driver, wi ansiion ime r. So a ime, in ( (/ r. Similar o [] e discharging behavior of oupu node can be divided ino differen regions: Region. in < : Here NMOS is in e cu-off region and oupu is a. Region. < in : Here NMOS is in sauraion. Unlike [], coupling capaciance beween gae and drain is no considered because is effec is significan only for sharp inpu edges and can be ignored for pracical circuis. Shor circui curren is also ignored since, in an inverer, bo PMOS and NMOS conduc only when < in < - (p, (p is reshold volage of PMOS, and for scaled echnologies, - (p - is very small. If C is e load capaciance and I n is e curren rough e NMOS device, en e oupu volage ou is given by, dou C I ( n d By subsiuing sauraion curren equaion from (, we ge + y ( in ou ( e + (3 β s y C + ( and e consan is found from e boundary condiion when in. ou is en and /. Region 3. > r, in : In is region NMOS is sill in sauraion and PMOS is in cu-off. The oupu coninues o discharge o 0.5. The oupu volage is given by z ou ( e + (4 βs( z C and e consan is found from e boundary condiion r. + ( y z ( e e + For scaled devices, ansiion imes can no longer be ignored in e delay equaions. Propagaion delay is defined by e difference of imes when in 0.5 (a is 0.5 r and when, ou 0.5. ou reaches half of in eier Region or Region 3 depending on e value of inpu ansiion ime and oupu load capaciance. For slow inpu or small load capaciance, ou reaches half in Region. Tphl is obained from equaion (3 and is given by. T phl [ + ] log (5 Where 0.5 log ln y For fas inpu or large load capaciance, ou reaches half in Region 3. Tphl is obained from equaion (4 and is given by T phl ln z ( 0.5 / Figure : Inverer H delay wi varying device wid, load capaciance and inpu ansiion ime a 45nm echnology. Model alidaion: The model is validaed for a wide range of ansisor wids, load capaciances and ansiion imes wi SPICE simulaions. Firs, wid is varied from wice e minimum leng o 0 imes e minimum leng and for is case, fanin and fanou are fied a FO4. Ne load capaciance is varied by sweeping from FO4 o FO0 and keeping fanin a FO4. Here wid of NMOS ansisor is fied o be 4 imes e minimum leng. Then inpu ansiion ime is varied by sweeping fanin of e gae wi fanou fied a 0. Here e NMOS wid is se o 4 imes a of e minimum leng. Figure shows H delay values prediced by e model and SPICE simulaions for 45nm echnology. As seen from e figure, delay is almos consan wi varying wid. Delay is proporional o load capaciance and i is also proporional o ansiion ime for small ansiion imes bu sauraes for large ansiion imes. The figure also shows a model is coninuous beween Region and Region 3. A 45nm node, e analyical model for nominal delay maches e SPICE values wi average error of.08 when wid is wid is varied..95 error when load capaciance is varied and.83 when inpu ansiion ime is varied. A 3nm node, e average errors are 0.7, 4.58 and 3.5 wi varying wid, load capaciance and inpu ansiion imes, respecively. Thus e model is also accurae for lower echnology nodes... Timing Model for NAND and NOR gaes The delay mode derived for an inverer is eended o handle sacked ansisors in NAND and NOR gaes. Here e oupu volage discharge characerisics depends on e ansisor sack placed beween e swiching inpu and e oupu. Transisors placed beween swiching inpu and supply nodes do no affec e oupu and hence e delay. For insance, in Figure, when inpu is given o A, oupu (6
3 depends only on ansisor M, as, when e inpu is given o A, oupu depends on bo ansisors M and M. The wo cases are considered separaely as follows. Figure : Schemaic of NAND gae. Case : Inpu given o e boom ansisor in e sack: Inpu volage is a linear ramp, in ( (/ r. Iniially when inpu volage is a 0, oupu volage is a. The volage a node X in Figure is a (M. (M is e reshold volage of M. According o Elmore s law, delay is proporional o R (C +C X + R C (7 C is e load capaciance and C X is e capaciance a node X. The firs erm in equaion (7 is v R (C +C X, which is e ime o discharge C and C X rough M. The second erm in equaion (7 vou R C, is e ime o discharge load capaciance rough M. So, e oal H propagaion delay of NAND gae when inpu is given o e boom ansisor is given by Tphl v + vou (8 Derivaion of v : As inpu o M increases, M shifs from cu-off region o sauraion and en o linear region. e vf be e final volage a X when ou reaches half. So ime aken o discharge C + C X rough M can be spli ino wo: Time aken for o discharge from (M o a sa. Here M is in sauraion. Time aken o discharge from o vf. Here M is in linear region. From equaion (5, sa + (9 log log ln y Depending on inpu ansiion ime, sa and v can be less an or more an r. v < r : In is case inpu is sill rising when reaches f M is in linear region wi rising inpu and ou is solved wi I n in e linear region is given by ou e r + C (0 βs [ + ( ] C ( + The consan C is found using e boundary condiion when ou is equal o a sa. The ime when ou reaches f is ln( f + C r v + ( sa C ln( + sa < r, v r : During e ime from sa o r, M is in linear region wi rising inpu and volage a is given by equaion (0. e e volage a reach, r when r. Then e ime aken o discharge from, r o f is given as R C X. ln(, r / f, DS R I D0 [ βs ( + ( ]( Thus f v + ln RC ( ( sa > r : Here inpu volage has already reached before reached. So ime aken o discharge from o f is given by R C X. ln( / f. Thus v is given by v sa + ln RC (3 f DS R I β + D0 [ ( ( ]( s Derivaion of vou : During e discharge of oupu node as well as X node, M is in linear region. So i acs as a simple resisor whose resisance can be derived from linear curren equaion in (. DS R (4 I D0 [ β s ( + ( ]( Here is e reshold volage of M or M depending on wheer e inpu has fas or slow ansiion ime. When inpu has fas ansiion edge ( r < sa, curren rough M is large, curren rough M is limied by M, so (M. If inpu has slow ansiion edge, curren rough M is small and curren rough M is limied by M, so. The ime o discharge C from o half is given by 0.69R (5 vou C Case. Inpu given o op ansisor in e sack: When inpu is given o op ansisor, is already discharged. So only ou has o discharge from o half rough e sack. This is equivalen o an inverer bo M and M are ogeer considered o be a single ansisor of approimaely half e wid. The delay is given by 3
4 equaions (5 or (6 depending on inpu slew rae. Noe a e H delay for NAND gaes and H delays for NOR gaes follow e eac same equaions for inverer because ansisors are no sacked here and are equivalen o inverers. Figure 3: NAND gae H delay wi varying device wid, load capaciance, inpu ansiion ime a 45nm node when inpu is given o M. Model alidaion: Figure 3 shows e characerisic behavior of NAND gae using e proposed model and SPICE simulaions, when e inpu is given o M (boom ansisor. Delay values wi respec o varying ansisor wids, load capaciances and ansiion imes are shown. Similar o IN delay, delay in NAND gae is also almos invarian o wid, varies linearly wi C and r for fas ansiions and sauraes for slow ansiions. The average error when inpu is given o M and varying e wid is - 0.6, when varying C e error is -0.7 and for varying r e error is.7. The parameers required in e model are given in Table I. The parameers,,, I D0 and are eaced from device characerisics. The parameers load capaciance and final volage f, a node X reaches are parameers from e circui level. All oer parameers like, y, z, log, and C are derived from e parameers in Table I. Table I: Parameers used in e model and eir eacion deails. (7 r TP For an inverer wi fas rising inpus or large load capaciance, inverer delay follows equaion (6 and variabiliy is given by TP [ S + S( S3 S4 ] (8 S S z Parameer I D0 C f 0.5 ln, S ln ( z y ( in βs z ( e ( + ( S4 e 3 y, Eacion Informaion for echnologies considered Circui characerisics Circui characerisics The consans y, z, and, are funcions of C and r and I D0 and are defined in Secion.. C 3. Delay variabiliy model 3.. ariabiliy in inverer ariaion in delay due o reshold volage is analyzed in is secion. Here reshold volage variaion is assumed o follow Gaussian disibuion hence, e delay variaion should also follow Gaussian disibuion wi sandard deviaion, [3]. (6 T phl TP For an inverer wi slow rising inpu or small load capaciance, inverer delay follows equaion (5 and variabiliy in such a case is given by Figure 4: Inverer H delay variaion wi varying device wid, oad capaciance and inpu ansiion ime a 45nm echnology. Model alidaion: The analyical delay and delay variabiliy is compared wi SPICE Mone Carlo simulaions. Figure 4 shows e variaion in (H delay wi respec o variable ansisor wids, load capaciances and inpu ansiion imes for 45nm echnology node. Here e 4
5 baseline volage variaion in a ansisor is 50m corresponding o wice e minimum leng and e reshold volage varies wi wid as W, / W is wid of e ansisor. Our observaions are as follows. varies in proporion o, as shown in Figure 4a. This is o be epeced since varying wid does no have any effec on nominal delay (see Figure, varies linearly wi C, as shown in Figure 4b. This is jusified using equaion (8. According o is equaion S and S are proporional o / z, z is proporional o /C. S 3 and S 4 vary almos similarly canceling each oer s effec. is proporional o r as seen in Figure 4c. This feaure is modeled very well by equaion (7. The maimum difference beween SPICE and model esimaed / is 0.68 when wid is varied, 0.47 when C is varied and.09 when r is varied for H delays a 45nm echnology. Here, / simulaed by SPICE is 4.5. Table II: Delay variaion of NAND gae wi variaion on one of e ansisors. Inpu / Oupu SPICE Analyical Model condiions / / B-lh, O-lh B-hl, O-hl A-lh, O-lh A-hl, O-hl ariabiliy in NAND and NOR gaes Delay variaions in NAND and NOR gaes are also derived using equaion (6. Delay variaion for NAND depends on wheer inpu is given o op ansisor or boom ansisor of e sack. Case. Inpu given o boom ansisor in e sack: When inpu is given o boom ansisor (M of Figure, variaion in any of e op or boom ansisors affecs delay variaion. The delay of NAND is given by equaion (8 and i is a funcion of bo (M and (M ( (M in NAND delay equaions. So parial derivaive of (8 wi respec o (M or gives delay variaion because of reshold volage variaion in M or M, respecively. Case. Inpu given o op ansisor in e sack: When inpu is given o op ansisor, delay depends only on of op ansisor. So variaion in delay is given by inverer delay variaion, as in equaions (7 or (8 depending on e region when ou reaches half. So variaion in boom ansisor should have almos no effec on e delay in is case. Figure 5: Schemaic of XOR circui Table II shows variaion when inpu is given o op (M and boom (M ansisors. In each case of only M or M is varied. NAND gae is loaded wi FO0 and fanin is se a FO4. SPICE and model resuls show a, when inpu is given o M, of M has song effec on delay variabiliy while of M has very lile effec. Bu when inpu is given o M, of bo M and M affec delay variabiliy. SPICE resuls closely mach wi model esimaed values. For NAND3 gae, delay variabiliy depends on variaion of op and boom ansisors when inpu is given o boom ansisor. I does no depend on middle ansisor because variaions in middle ansisor are easily compensaed by eier op or boom ansisor. When inpu is given o middle ansisor, variaions in op and middle ansisors affec delay variabiliy. When inpu is given o op ansisor variaions in op ansisor alone affec e delay variaions. Table III: SPICE versus model esimaed delay variaion of XOR gae. Inpu ariion SPICE Analyical Model / / M M M M 4. alidaion wi benchmark circuis 4.. XOR gae The analyical model is applied o XOR gae. The esimaed delay values are compared wi SPICE values. The nominal delays of all e sages are added o compue e delay of e circui. ariabiliy is also found for each sage and since variaions in each ansisor are considered o be independen, equaion (8 is used o esimae oal circui variabiliy. M M (9 pa gae The circui of XOR gae is shown in Figure 5. The H delay, when inpu A is se o 0 and B swiches from o 0 is considered. The H delay, when B swiches back from 0 o is considered. The oer paern is when B is 0 and A is swiching since ese acivae criical pas. Resuls are summarized in Table III. The maimum difference beween SPICE and model prediced / percenage is less an. Such an accurae predicion of nominal delay and delay 5
6 variaion has been possible because e model considers load capaciance, ansiion imes and sacking effec. 4.. Model validaion for ISCAS 85 benchmark circuis Seup: The model has been uned o mach e Nangae 45nm echnology library []. I is verified for gaes wi X drive seng in e library. Here inpu ansiion imes ranges from 7.5ps o 600ps and load capaciance range from 0.4fF o 5.6fF. 0 ISCAS benchmark circuis wi number of gaes varying from 60 o 35 are considered [4]. To be able o simulae e circuis wi e library in [], larger gaes like NAND8, NAND9 are replaced wi funcionally equivalen smaller gaes available in e library. Synopsys primeime /pamill ools were used o eac criical pas and relaed SPICE deck from e ISCAS circuis. arious criical pa informaion are eaced from e oupu iming file of Synopsys primeime and en e proposed model esimaes e nominal delay and delay variabiliy of each gae in e eaced pas. The nominal delay is summed up and variaion is calculaed according o equaion (9. Table I: Comparison of nominal delay esimaion for ISCAS 85 benchmark circuis. Gaes in SPICE Analyical ISCAS Toal Error criical nominal nominal circui Gaes pa delay delay C C C C C Comparison of nominal delay a 45nm: For ISCAS benchmark circui, e nominal delay esimaed for criical pas using e model and spice simulaions are shown in Table I. Model predicion of nominal delay is wi maimum percenage error being 3.5 compared o a of spice simulaion. While e resuls here are for Nangae library [], e model can easily be applied o oer sandard libraries. ariaion predicion wi e model: The delay variabiliy of criical pas for five of e ISCAS benchmark circuis are also esimaed. ±3 variaion ( for a ansisor according o 4m is added wi wid wice e minimum leng W. Table summarizes e delay / variaion for e benchmark circuis. The model prediced average variaion is wiin ps - 5ps accuracy compared o a of SPICE simulaion, depending on e circui opology, inernal node capaciance and e ansiion ime. The ime aken o esimae variabiliy wi e model is a very small fracion of e ime aken o run SPICE simulaions. Though channel leng variaion conibues o significan porion of process variaion, for a firs order approimaion variaion model can quickly help idenify criical pa delay variaion in early sage of design flow. Table : Comparison of delay variaion for ISCAS 85 benchmark circuis. ISCAS circui SPICE Analyical Model / / C C C C C The run ime for e proposed analyical model is muliple orders less an a of e ime aken for HSPICE simulaion o esimae e variaion. Run ime aken for 00 Mone Carlo simulaions in HSPICE is abou hours for a circui wi 0 gaes and is abou 4 hours for a circui wi 3 gaes. Thus, for designs wi larger number of gaes, e run ime can be oo large for pracical applicaions. In e analyical model, e major conibuor for run ime is e ime aken o eac e capaciance of e nodes in e criical pa and idenify e criical pa iself. Ye, for a circui of abou 500 gaes, e runime is less an approimaely 0s. The calculaion of mean and delay variaion is only few milliseconds. Hence e run ime is negligible and as e analyical model predics variaion wi reasonable accuracy, i can be inegraed ino e design flow for robus design Analyical model usage in design flow The proposed analyical model can be used o idenify possible iming violaions in e early sage of e design flow. Seup violaions are caused by delay variaions in criical pas. ariabiliy is low in ese pas because of e averaging effec. However, pas wi slighly smaller delay can have larger variabiliy and can become criical [5-6]. Figure 6 shows e delay disibuion graph for e C880 Figure 6: Delay disibuion curve for C880 benchmark circui for nominal delay and wi variaions. 6
7 benchmark circui a nominal condiions and wi variaion. As i can be seen from e graph, e disibuion widens because of variaion and e number of criical pas increases. Some of e noncriical pas a nominal condiions have now become criical. The number of shores pas also increases. The minimum delay decreases and is can cause a hold violaion. Similar end is seen in anoer circui ISCAS C775. Here e criical pa has a nominal delay of 885.4ps and pas wi 5 less an criical pa delay are also considered as criical pas. Consider Pa- wi a delay of 787.3ps, a is 5. smaller an e criical pa and so no considered o be criical. Now wi a sligh variaion of 0m (for a ansisor wi wid wice e minimum leng and / varying wi e relaion W, e wors case delay (+3 of e criical pa is 900.5ps and e delay of Pa- is 806.8ps, which is wiin 5 of e criical pa delay. Hence Pa- becomes criical as well. Similarly, Pa-3 wi nominal delay of 777.7ps becomes criical for 30m. Figure 7: Non-criical pas approaching criical pas in ligh of variaion. Figure 7 shows e wors case delays of ese pas as a funcion of. The plo also shows a as increases, e number of criical pas increases. The proposed model can us help easily idenify pas a may become criical due o variaions, early in e design phase and wiou having o do ime consuming Mone Carlo simulaions. 5. Conclusion An analyical model for predicing nominal delay and delay variabiliy of CMOS gaes has been proposed. The resuls closely mach ose generaed by ime consuming Mone Carlo simulaions for a wide range of gae size, load capaciance and ansiion imes. The model is simple and can be used o accuraely predic iming variabiliy during design phase. Hence i can be easily inegraed ino e design flow o idenify iming violaions due o variaions and helps enable robus design implemenaion during early sages of e design. 6. References [] T. Sakurai and A. Newon, Delay analysis of series conneced MOSFET circuis, IEEE J. Solid-Sae Circuis, vol. 6, pp. 3, Feb 99. [] S. N.. Bisdounis and O. oufopavlou, Analyical ansien response and propagaion delay evaluaion of e CMOS inverer for shor-channel devices, IEEE J. Solid-Sae Circuis, vol. 33, pp , Feb 998. [3] A. Hamoui and N. Rumin, An analyical model for curren, delay, and power analysis of submicron CMOS logic circuis, IEEE Trans. Circuis and Sysems II, vol. 47, pp , Oc 000. [4] J. Rossello and J. Segura, An analyical charge-based compac delay model for submicromeer CMOS inverers, IEEE Trans. Circuis and Sysems I, vol. 5, pp. 30 3, July 004. [5] T. Sakurai and A. Newon, Alpha-power law MOSFET model and is applicaion o CMOS inverer delay and oer formulas, IEEE J. Solid-Sae Circuis, vol. 5, pp , April 990. [6] Y. Wang and M. Zwolinski, Analyical ansien response and propagaion delay model for nanoscale CMOS inverer, IEEE Inernaional Symposium on Circuis and Sysems, pp , May 009. [7] Y. Ye, S. Gummalla, C. Wang, C. Chakrabari, and Y. Cao, Random ariabiliy Modeling and is Impac on Scaled CMOS Circuis, J. Compuaional Eleconics, pp. 08 3, 00. [8] G. P. M. Alioo and M. Pennisi, Undersanding e effec of process variaions on e delay of saic and domino logic, IEEE Transacions on ery arge Scale Inegraion (SI Sysems, vol. 8, pp , May 00. [9] P. iu and Y. im, An accurae iming model for nano CMOS circui considering saisical process variaion, IEEE Inernaional SoC Design Conference(ISOCC, pp. 69 7, 007. [0] PTM. hp://pm.asu.edu/. [] Nangae. hp:// [] P. iu, Y. im, and Y. ee, An accurae analyical propagaion delay model of nano CMOS circuis, IEEE Inernaional SoC Design Conference(ISOCC, pp , 007. [3] S. R. Sarangi, B. Greskamp, R. Teodorescu, J. Nakano, A. Tiwari, and J. Torrellas, arius: A model of process variaion and resuling iming errors for microarchiecs, IEEE Transacions on Semiconducor Manufacuring, vol., pp. 3 3, 008. [4] ISCAS 85. hp://dropzone.amu.edu/_iang/iscas.hml [5] J. Xiong,. Zoloov, C. isweswariah, and N. enkaeswaran, Criicaliy compuaion in parameerized saisical iming, Design Auomaion Conference (DAC, pp , July 006. [6]. Iyengar, J. Xiong, S. enkaesan,. Zoloov, D. ackey, P. Habiz, and C. isweswariah, ariaion-aware performance verificaion using a-speed sucural es and saisical iming, Inernaional Conference on Compuer- Aided Design (ICCAD, pp 405-4, November
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