DESIGN OF CMOS ANALOG INTEGRATED CIRCUITS

Transcription

1 DESIGN OF CMOS ANALOG INTEGRATED CIRCUITS Franco Maloberti Integrated Microsistems Laboratory University of Pavia Continuous Time and Switched Capacitor Filters F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/

2 OUTLINE Electrical Filters Single op-amp realization Cascade and multiple loop feedback Switched capacitor technique Biquadratic SC filters SC N-path filters Finite gain and bandwidth effects Layout consideration Noise F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/2

3 ELECTRICAL FILTERS Electrical filters is an interconnection network of electrical components which operates a modification of the frequency spectrum of an applied electrical signal. The network is linear and time invariant. FILTER DESIGN PROCEDURE: Filter specifications Design of the network that implements the specifications Component values evaluation F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/3

4 Filter specification: Is usually defined by a mask which specifies the range of allowed frequency responses. The frequency range is divided into: Pass band Stop band 0 db Pass band Stop band F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/4

5 Usually, they are specified: Ripple in the pass band Attenuation in the stop band Specification of the phase response: Usually linear phase response Type of filters: Low pass, low pass notch High pass, high pass notch Band pass, band reject All pass Φ() f = kf ( f 0 ) F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/5

6 Networks: Filter specifications are met with linear networks which determine a transfer function of the form: Hs ( ) = P m ( s) Q n ( s) P m (s) and Q n (s) are polynomial of order m and n respectively. The zeros of P m (s) are the zeros of the transfer function. The zeros of Q n (s) are the poles of the transfer function. Always n m. The number of poles gives the order of the filter. The ripple in the pass-band and the transition between the stop-band and the pass-band determine the order of the filter F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/6

7 Transmission zeros in the stop-band help in getting a sharper transition H H Very elementary specifications are met with first order or second order filters. First order: H LP = src f f in R out in C out C R H HP src = src LOW PASS Second order filter or biquadratic (biquad) filter: HIGH PASS F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/7

8 s 2 s ω z ω Z Q z Hs ( ) = k s 2 s ω = ω 0 Q 0 p 0 sp s 2 p s 2 s ω ω 0 Q 0 Low pass response: 2 ω z k ( p 0 ω z ) p 0 = p = 0 p 2 = 0 High pass response: Low pass notch response: High pass notch response: p 0 = p = 0 p 2 = 0 ω z = 0 p 0 = 0 ω 2 > ω F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/8

9 Band pass response: p = 0 ω 2 < ω p All pass response: p 0 0 p k ω z = = p 2 = 0 Q z 2 ω 0 p 0 = ω 0 p = p 2 = Q 0 F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/9

10 Active realization of biquadratic transfer functions: Z3 R2 C C2 Vin Z - R V - V0 Z2 sc V = Y V in Y 3 V 0 ( s G 2 )V 0 = Y 2 V in G 3 V Eliminating V it results: F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/0

11 V V in = sc Y 2 G Y sc ( s G 2 ) G Y 3 Note that, for stability reasons, the inverter and a dumping (R 2 or dissipative Z 3 ) are requested around the loop The admittances Y, Y 2 and Y 3 have usually the form Y = GsC Z3 R2 sc V = Y V in Y 3 V 0 C C2 ( s G 2 )V 0 = Y 2 V in G V V in Z V R - V 0 V V in = sc Y 2 G Y sc ( s G 2 ) G Y 3 Z2 F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/

12 SINGLE OP-AMP REALIZATION Sallen and Key filter: Z' Vin Z Z Vout 2 Z' 2 Hs ( ) V out ( s) = = V in ( s) Z Z ( Z Z 2 Z 2)Z Z Z 2 F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/2

13 For low pass response: C Z = Z 2 = R Z Z 2 = s = sc Vin R R C2 Vout Hs ( ) = sR s 2 R 2 C For maximally flat response: Z 2 2 ; ; = C = 2 f p = πR Key features: The op-amp is in buffer connection, input swing must be equal to the output swing. In the pass-band no current flows on the resistances (even if they are non linear, non harmonic distortion results). F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/3

14 Rauch filter Z 3 Z' 2 Vin Z Z 2 V out Z' Hs ( ) V out ( s) = = V in ( s) Z Z 2 Z Z Z Z Z 3 2 Z Z 2 Z 3 F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/4

15 For low pass response: 3 Z = R Z 2 = R 2 Z 3 = R 3 R R 2 V in - V ou Z = Z 2 sc = s C Hs ( ) For maximally flat response: = R R s R R R s 2 R R 2 C R 3 ; R 3 R = R 3 = 2R 2 = 2R C = 4 = 4C f p = πR F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/5

16 Key features: The op-amp has the non inverting input referred to the ground. In the pass-band there is a current flowing into the resistors. Low pass Sallen and Key filter with real op-amp: 2C Vin R R vi - Vout C gm vi R0 C0 A real op-amp used in CMOS monolithic S&K filter is a transconductance op-amp F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/6

17 With the above equivalent scheme: Hs ( ) = 2sC g m 2s 2 R g m α sβ s 2 γ s 3 δ α = β 2RC R 0 C 0 2R 0 C 4RC = A 0 γ = 2R ( 4RR A 0 CC ( C 0 ) 2R 2 ) δ 2 R2 = g 0 C m A 0 = g m R 0 0 The transfer function has two zeros and three poles. If k = Rg m >> the zeros are practically complex conjugates and are located at ω 0 = g m 2R = ω p k The extra-pole is real and is located around the GBW of the op-amp. A 0 F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/7

18 log f f T f T2 f T3 : f T /f p = : f /f = 20 T p 3: f /f = 4 T p K= 40 A low value of k = Rg m determines a shift of the poles of the S & K filter with respect to the designed position normalized module of poles (%) K=00 K=0 K= f T /f p F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/8

19 Q factor (nominal value 0.707) 0,9 0,8 0,7 0,6 K=00 K=0 K= f /f T p Design criteria: Use an op-amp with f T > 20 f p Use resistances R > 40/g m F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/9

20 Low pass Rauch filter with real op-amp: Hs ( ) = sr ( R 0 )C ( A 0 ) α sβ s 2 γ s 3 δ 2R C α = A 0 Vin 2R 4C R Vout β 4RR 0 C 0 R 0 C 3RC = A 0 g m v i R 0 C 0 γ 8R 2 6RR 0 CC 0 2RR 0 8R 2 = δ 8 R2 R 0 C 0 = A A 0 g A m 0 = g m R 0 The transfer function has one zero and three poles. The zero is far away from f p if A 0 >> F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/20

21 The extra-pole is around the unity gain frequency of the op-amp 20 0 : f /f = 00 T p -20 2: f /f = 20 T p Gain (db) : f /f = 4 T p K= log(f) The two other poles are shifted with respect to the designed location odule of poles (% ) normalized module of poles (%) K=00 K=0 K= f T /f p f T /f p F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/2 nom inalvalue 0.707) Q factor (nominal value 0.707) 0,8 0,7 0,6 0,5 K=0 K=00 K=3

22 Effect of the integrated resistors: Y = sc R sinh src R Y Y P Y P Y P = Y( cosh( src ) ) 0 0 Gain (db) log(f) 2 3 : f /f = 00 T p 2: f /f = 20 T p 3: f /f = 4 T p K= 40 Gain (db) log(f) 2 3 : f /f = 00 T p 2: f /f = 20 T p 3: f /f = 4 T p K= 40 F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/22

23 HIGH ORDER FILTERS There are several way to realize high order ( > 2 ) filters. We will consider: Cascade realization Multiple loop feedback Cascade realization: RS v in H (s) H (s) 2 H (s) N RL Z in, Z out, Z in,2 Z out,2 Z in,n Z out,n Consists in the cascade connection of isolated biquad sections. H i (s) is the biquad transfer function. F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/23

24 For getting isolation it must be: R s «Z in «, Z out, i Z in, i Z out, N R L «Hs ( ) V out ( s) = = H V in ( s) i ( s) i = A given specification is met with a rational transfer function: N Fs ( ) a 0 a s a 2 s 2... a m s m = b 0 b s b 2 s 2... b n s n = a m b n m i = m i = ( s ) s zi ( s ) s pi s zi and s pi are the zeros and the poles of F(s) (real or complex conjugate) F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/24

25 Design problem: group together pole and zero pairs (pole-zero pairing): it affects the dynamic range and the sensitivity. Unfortunately there are not general and consistent rules for the pole-zero pairing in order to minimize the sensitivity. Two opposite approaches are suggested in the literature: Pair the high-q poles with far away zeros Pair the high-q poles with closed zeros The only solution is to try different pairing and to compare them with Monte Carlo analysis. For order > 6 the cascade design is inherently more sensitive to component variation than multiple-loop feedback realizations. F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/25

26 MULTIPLE LOOP FEEDBACK REALIZATIONS Several topologies: Follow the leader feedback (FLF) Inverse follow the leader (IFLF) Generalize follow the leader feedback (GFLF) Primary resonator block (PRB) Leapfrog feedback (LF) Modified leapfrog feedback (MLF) Coupled biquad (CB) Minimum sensitivity feedback(msf) F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/26

27 LEAPFROG TOPOLOGY Simulate passive ladder networks, via signal flow graph I 0 R S L 2 L 4 V V 3 V 5 V out V in I 2 I 4 I 6 C C 3 C 5 R 6 I 0 = ( V in V ) R s V = ( I sc 0 I 2 ) I 2 = ( V sl V 3 ) 2 F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/27

28 V 3 = ( I s I 4 ) 3 I 4 = ( V sl 3 V 5 ) 4 V 5 = ( I sc 4 I 6 ) 5 I 6 = V 5 R 6 V out = V 5 If we multiply each current by an arbitrary resistance R, we define new dummy voltage variables V 0 = RI 0 V 2 = RI 2 V 4 = RI 4 V 6 = RI 6 F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/28

29 The equations becomes: V 0 = R ( V in V ) R s V = ( V src 0 V 2 ) V 2 = R ( V sl V 3 ) 2 V 3 = ( V sr V 4 ) 3 V 4 = R ( V sl 3 V 5 ) 4 V 5 = ( V src 4 V 6 ) 5 V 6 = R V R 5 6 F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/29

30 The original set of equations and the modified one can be represented with the signal flow graphs: V in V V V 3 5 /R s /sc /sl 2 /sc 3 /sl 4 /sc 5 /R 6 I 0 I 2 I 4 I 6 V in V V V 3 5 R/R s /s t /s t /s t 3 /s t 4 /s t 5 R/R 6 V s V 2 V 4 V 6 F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/30

31 Scaling of the flow graph: V V3 V V3 V3 V3 /sl 2 R/sL 2 /s t 3 /s t3 I2 /R V2 /R V 2 V V 4 2 V 4 V3 V3 V 3 V 3 /sc3 /src3 /s t k/s 3 t 3 I2 I4 V 2 V 4 V 2 V 4 V 2 /k /k V 4 Variable transformation Scaling by constants F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/3

32 The scaling of the flow graph is used in order to obtain realizable active implementations Inverting integrators Inverters Summators V in V V 3 V 5 R/R s /s t /s t /s t /s t 3 4 /s t 2 5 R/R 6 V s V 2 V 4 V 6 Interconnection of second order loops (R R s R 6 ) in t t t t 3 t out F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/32

33 The scaling is also useful for dynamic range optimization: V is too small V 2 is too high V K V V 2 V K 2 Gain (db) H Hout H2 f Result: all the op-amp saturate (at different frequency) with the same input level. Perform a SPICE simulation of the active (or passive) network in order to determine the scaling factors. F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/33

34 If the passive prototype has transmission zeros at the finite (elliptic filters), it has the form (low pass). C 4 V V 3 V 5 R S L 2 L 4 V out V in C C 3 C 5 R 6 Before to describe the network and sketch the flow diagram it is worth to remove the bridging capacitors and C 4 through the use of the Thevenin s theorem C2 V L2 V3 V L2 V3 C C2 C3 C2 C C3 a V3 a2 V a =C2 /(C C2 ) a2 =C2 /(C3 C2 ) F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/34

35 Similar modification follows if C 4 is removed R S L 2 L 4 V V3 V5 V out V in CC2 C2C3C4 C 4 C 5 R 6 a V3 a 2 V a 3 V 5 a 4 V3 a =C2 /(CC2 ) a 2 =C2 /(C3C2) a 3 =C 4 /(C 3 C 4 ) a 4 =C 4 /(C 5 C 4 ) The equations concerning the state variables V, V 3 and V 5 change: V V ( I sc s I 2 ) 3 C = C C = C V 3 = ( I sc 2 I 4 ) 3 V 5 = ( I sc 4 I 6 ) 5 V V 5 C C C 3 C 3 C 4 V 3 C C 5 C 3 = C 3 C 4 C 5 = C 4 C 5 F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/35

36 After scalings, aimed to the active realization: a 2 a 4 V 3 V in V a a V 5 3 R/R s /s t /s t 3 /s t 4 t /s t 2 /s 5 R/R 6 V s V 2 V 4 V 6 in out - t t t t 3 t 5 4 F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/36

37 SWITCHED CAPACITOR TECHNIQUE An active filter is made of op-amps, resistors and capacitors. The accuracy of the filter is determined by the accuracy of the realized time costants since the capacitors and resitors are realized by uncorrelated technological steps δτ τ 2 = δr R δc C 2 In CMOS technology δr R 40% ; δc C 30% ; hence %, τ unacceptable for most of the applications Hybrid realization with functional trimming δτ F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/37

38 Problems for a fully integrated realization Accuracy Values of capacitors and resistors: for 70 nm oxide thickness pf -- > 2000 µ 2 ; 0 pf is a large capacitance. To get τ = 0-4 sec R = 0 7 Ω The above problems are solved by the use of simulated resistors made of switches and capacitors. MOS technology is suitable because: Offset free switches Good capacitors Satisfactory op-amps F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/38

39 Simple SC structures I V V Φ Φ2 C Φ Φ 2 V2 I V2 Φ Φ 2 T T C Q = C (V - V 2 ) every t = T F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/39

40 Q = i t = V V T R V V 2 I I T The two SC structures are (on average) equivalent to a resistor R eq = T C t If the SC structures are used to get an equivalent time constant τ eq = R eq it results: τ eq T = C F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/40

41 Its accuracy depends on the clock and on the capacitor matching accuracy If τ eq =40 T = 40 C (acceptable spread) regardless of the value of τ eq A more complex SC structure: V Φ Φ2 V2 Q = 2C ( V V 2 ) Φ2 Φ The charge is transferred twice per clock period T or we assume as clock period half of the period of phases Φ and Φ 2. F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/4

42 SC INTEGRATOR R Starting from the continuous-time circuit of the Integrator, we can obtain a SC integrator by replacing the continuous-time resistor with the equivalent resistances as follows: F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/42

43 Φ Φ2 C Φ Φ2 Φ C Φ Φ C Φ2 Φ2 Φ2 Φ Φ F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/43

44 We consider the samples of the input and of the output taken at the same times nt (the end of the sampling period). Structure : taking the z-transform: V out [( n )T] = V out ( nt) C V in ( nt) V out ( z) V in ( z) = C z Structure 2: taking the z-transform: V out [( n )T] = V out ( nt) C V in ( n )T ] F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/44

45 V out ( z) V in ( z) = C z z Structure 3: V out [( n )T] = V out ( nt) taking the z-transform: C { V in [( n )T] V in ( nt) } V out ( z) V in ( z) = C z z Remember that for the continuous-time integrator: V out ( s) V in ( s) = sr Comparing the sampled-data and continuous-time transfer functions we get: F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/45

46 Structure : R T s C -- ( z ) T FE approximation Structure 2: R T s C -- ( z ) T z BE approximation Structure 3: R T s 2C ( z ) T( z ) Bilinear approximation It does not exist a simple SC integrator which implement the LD approximation. Note: the cascade of a FE integrator and a BE integrator is equivalent to the cascade of two LD integrators. F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/46

47 C2 ' C ' C2 Φ Φ 2 C Φ 2 Φ The key point is to introduce a full period delay from the input to the output The same result is got with: C2 ' C2 Φ Φ2 Φ2 Φ C ' C F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/47

48 STRAY INSENSITIVE STRUCTURE The considered SC integrators are sensitive to parasitics. Toggle structure: The top plate parasitic capacitance C t, is in parallel with C It is not negligible with respect to C and it is non linear Φ Ct, C Φ2 Cb, The top plate parasitic capacitance C t, acts as a toggle structure Φ Φ 2 C C t, C b, F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/48

49 Bilinear resistor: Both the parasitic capacitances C t,, C b, act as toggle structures. Their values are different (of a factor 0) and they are non linear. Stray insensitivity can be got for the first two structures if one terminal is switched between points at the same voltage. Ct, Φ C Φ 2 Φ 2 Φ Cb, C Φ Φ 2 Φ Φ 2 C Φ Φ Φ 2 Φ 2 Virtual ground Virtual ground F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/49

50 The right-side parasitic capacitor is switched between the virtual ground and ground (note: even in DC V v.g. must equal V ground ) The left side capacitor is connected, during phase, to a voltage (or equivalent) source. The charge injected into virtual ground is important, not the one furnished by the input source. Structure A is equivalent to the toggle structure, but the injected charge has opposite sign. Equivalent negative resistance allows to implement non inverting integrators. It is possible to easily realize a stray insensitive bilinear resistor with fully differential configuration. F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/50

51 SC BIQUADRATIC FILTERS Consider a (continuous-time) biquadratic transfer function Hs ( ) = p 0 sp s 2 p s 2 s ω ω 0 If the bilinear transformation is applied, it results a z-biquadratic transfer function Q 0 where the coefficients are: Hs ( ) = a 0 za z 2 a b 0 zb z 2 b 2 2 a 0 = p 0 -- p T p T 2 2 F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/5

52 8 a = 2p p 2 T a 2 = p 0 -- p T -----p 2 T b 0 ω 0 -- ω 0 = T Q T b = 2ω T b 2 ω 0 -- ω 0 4 = T Q T 2 F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/52

53 F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/53 All the stable z-biquadratic transfer functions are realized by the topology: - - G D E C A B F I J H F F2 Vin t V0 V 02

54 Features: Loop of two integrators one inverting and the other noninverting. Damping around the loop provided by capacitor F or (and) capacitor E (usually only E or F are included in the network). Two outputs available V 0, V 0,2. Denominator of the transfer function determined by the capacitors along the loop (A, B, C, D, E, F). Transmission zeros (numerator) realized by the capacitors (G, H, I, J). Input signal sampled during Φ and held for a full clock period Charge injected into the virtual ground during Φ. F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/54

55 Minimum switch configuration: C C C2 C2 Cn Cn E C G D A F B H I J F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/55

56 Charge conservation equations: DV 0, (n) = DV 0, (n) - GV in (n) HV in (n) - CV 0,2 (n) - E[V 0,2 (n) - V 0,2 (n)] (B F)V 0,2 (n) = BV 0,2 (n) AV 0, (n) - IV in (n) JV in (n) Taking the z-transform and solving, it results: V H 0, = = V in ( IC IE GF GB)z 2 ( FH BH BG JC JE IE)z( EJ BH) ( DB DF)z 2 ( AC AE 2DB DF)z ( DB AE) V H 02, 2 = = V in DIz 2 ( AG DI DJ)z( DJ AH) ( DB DF)z 2 ( AC AE 2DB DF)z ( DB AE) 0 Capacitors 6 Equations a 0, a, a 2, b 0, b, b 2 Dynamic range optimization F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/56

57 Scaling for minimum total capacitance in the groups of capacitors connected to the virtual ground of the op-amp and the op-amp 2. Since there are 9 conditions, one capacitor can be set equal to zero E = 0 F type F = 0 E type Firstly the 6 equations are satisfied. Later capacitors D and A are adjusted in order to optimize the dynamic range. Finally all the capacitor connected to the virtual ground of the op-amp are normalized to the smaller of the group. F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/57

58 Scaling for minimum total capacitance C C n C 3 C 4 Assume that C 3 is the smallest capacitance of the group. In order to make minimum the total capacitance C 3 must be reduced to the smallest value allowed by the technology (C min ) Multiply all the capacitors of the group by k = C min C 3 F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/58

59 All these design steps can be performed with a suitable computer program Equivalences for input structures: G-H G H H G G H-G for G>H for G=H for G<H F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/59

60 SC LADDER FILTERS Orchard s observation Doubly-terminated LC ladder network that are designed to effect maximum power transfer from source to load over the filter passband feature very low sensitivities to value component variation. Syntesis of SC Ladder Filters: Symple approach Replace every resistance R i in an active ladder structure with a switched capacitor C i = T/R i. Use a full clock period delay along all the two integrator loop (it results automatically verified in single ended schemes). It results an LD equivalent, except for the terminations. F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/60

61 Quasi LD transformation: Attenuation A pb DESIRED SPECIFICATION A sb w w pb w sb Attenuation A pb PREWARPED SPECIFICATION A sb sin( w pb T/2) sin( wsb T/2) Prewarp the specifications using sin(ωt/2) w F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/6

62 Effect of the terminations: R C3 R C2 C H DI ( s) R 3 = if R = T/ C and R 3 = T/C 3 we get: H s R R 3 R DI ( s) = C st C 3 V out ( n ) ( C 3 ) = V out ( n) C V in ( n) F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/62

63 Taking the z-transform we get: zv out ( C 3 ) = V out C V in H DI ( z) C = = ( z ) zc 3 C z ( z 2 z 2 ) z 2 C 3 along the unity circle z=e jωt H DI e jωt ( ) C e jωt 2 = ( e jωt 2 e jωt 2 ) e jωt 2 = C 3 C e jωt ωt ωt 2j( C 3 ) sin C 2 3 cos The half clock period delay will be used in the cascaded integrator in order to get the LD transformation The termination is complex and frequency dependent. The integrating capacitor must be replaced by C 3 /2. F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/63

64 Complex termination: C3 C C2 F Note: the output voltage changes during Φ Taking the z-transform: 2 V out ( n ) = V out ( n) C C V in ( n) 3 C zv out V out C = C C 3 V in F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/64

65 H DI ( z) C = = C ( z ) 2 C C 3 along the unity circle z=e jωt C z ( z 2 z 2 ) z 2 C C 3 H DI e jωt ( ) = C e jωt j C2C3 C 3 sin ωt C 3 ωt cos C 3 2 The imaginary part of the contribution of the termination is negative The integrating capacitor must be replaced by C2C3 C 3 F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/65

66 Example: 5th order filter I S R S L 2 L 4 V V 3 V 5 V out Passive prototype V in I 2 I 4 I 6 R 6 C C 3 C 5 Flow diagram V in V V 3 V 5 R/R s /s τ /s τ /s τ 2 3 /s τ 4 /s τ 5 R/R 6 V s V 2 V 4 V 6 implementa- SC tion τ T - τ2 T - τ3 T - τ4 T - τ5 T - F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/66

67 EXACT DESIGN OF SC LADDER FILTERS A continuous-time network is exactly transformed into a sampleddata network through the mapping z = exp(st). We can assume that an exact transformation is realized even through the LDI or the bilinear mapping, provided that the required pre-warping is made. The exact LD design of ladder filter is not possible because of the error given by terminations. The exact bilinear design is realizable through a suitable scaling. Let us define the complex variables: γ -- z 2 z 2 = ( ) = -- ( e st 2 e st 2 ) = s T 2 2 sinh -- 2 µ -- z 2 z 2 = ( ) = -- ( e st 2 e st 2 ) = s T 2 2 cosh -- 2 F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/67

68 λ z 2 z 2 z = = z z 2 = tanh s T -- 2 z 2 They are related by the relationships: λ = γ µ µ 2 = γ 2 z 2 = µ γ Note: the γ plane is the LDI plane and the λ plane is the bilinear plane (2/T normalized to ) To implement an exact LD equivalent s should be replaced by γ To implement an exact bilinear equivalent s should be replaced by λ Unfortunately, SC circuits having transfer function of the form /λ can not be realized in stray-insensitive form Solution: suitable scaling of the ladder network (or equivalently the flow diagram): if we divide all impedance of a network by the same scaling factor, the transfer function remains unchanged F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/68

69 Scaling of bilinear elements by µ: R R --- µ λc µλc = γc λl λl µ λµl γl = = γ 2 = Scaling changes: A resistor into a frequency dependent element A bilinear capacitor into an LD capacitor µ γ γl L A bilinear inductance into parallel of L - LD inductance with a /L - LD capacitor F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/69

70 Consider a 5th order elliptic filter (bilinear) /λc2 /λc4 R S λl 2 λl4 V out Vin RL /λc /λc3 /λc5 After scaling by µ L 2 /γ L 4 /γ /λ /λc 4 R S /µ λ/l 2 λ/l 4 V out V in /λc /λc 3 /λc 5 R L /µ F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/70

71 After the elimination of the bridging capacitors RS/µ γl2 γl4 Vout V in RL /µ /γc /γc 3 /γc 5 α V3 α2 α3 V V5 α 4 V3 C, = C L 2 C 3, = C 3 C 4 L 2 L 4 C 5, = C 4 C 5 L 4 α = ( L 2 ) ( C L 2 ) α 3 = ( C 4 L 4 ) ( C 3 C 4 L 4 ) α 2 = ( L 2 ) ( C 3 L 2 ) α 3 = ( C 4 L 4 ) ( C 5 C 4 L 4 ) F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/7

72 The network is the same as an LD equivalent ladder filter with the exception of the frequency dependent terminations γ C ( V α V 3 ) = µ ( V in V ) I 2 R s µ γ C 5 ( V 5 α 4 V 3 ) = I V 5 R L V = µ V R in γ V3 I s L µ γ C R s I 4 γ C V3 L 4 V 5 = µ γ C R L F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/72

73 After the dimensional scaling by R, (β s = R/R s, β e = R/R L ) β V s µv in γτ 2 V 3 V 2 = γτ β s µ V V 4 γτ 4 V 3 5 = γτ 3 β e µ If we remember the z-transfer function of the dumped integrator C3 C C2 F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/73

74 H DI ( z) C z 2 C ( µ γ) = ( z 2 z 2 ) C 3 z 2 = = 2 γ C 3 ( γ µ ) The denominators can be realized The only design problem come from the input β s µ V in µv in = -- ( z 2 z 2 )V 2 in It is necessary to inject two samples per period T Simple solution (stray sensitive) C ( µ γ) ( 2 C 3 )γ C 3 µ Φ Φ 2 C/2 C/2 Φ 2 Φ 2 F Φ F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/74

75 Stray insensitive solution: C/2 Φ 2 C Φ2 Φ Φ Φ2 Use of a S/H: C/2 Φ 2 Φ Φ 2 Φ C/2 Φ 2 Φ 2 Φ Φ F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/75

76 SWITCHED CAPACITOR N-PATH FILTERS Narrow-band (high Q) filters can not be realized with conventional design techniques Required gain A Q max ; Q pole (ω 0 B/2)/2 σ j ω Sensitivities to finite gain and capacitance variation proportional to Q max σ F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/76

77 Solution with N-path circuits; are a number of identical low pass filters multiplexed at the input and the output Φ LP Φ Φ Φ 2 LP Φ 2 Φ 2 Φ 3 Φ N LP Φ N Φ N Sampling period of the input signal: T; sampling period in each LP filter: NT F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/77

78 i V in () t = V in ()δt t ( nt it) n = N V in, NP () t = V in () t i = i In the z-domain N V outnp () t = V out () t i = i NP z ( ) V out,np ( z) = = ( ) V in, NP z N i = i V in N i = ( z)h LP ( z) i V in ( z) H NP ( z) = H LP ( z) F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/78

79 The z-transfer function of the N-path and the one of the low pass are the same, but the sampling frequencies are one N times the other z LP e snt ( ) st N ( e ) = = = The N-path filter realizes the transformation z In the transfer function of the low pass filter. The gain requirement and the sensitivities are the one posed by the low-pass filter specifications z N z N Implementation: C2 First order prototype: C C F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/79

80 C2 C Parallel implementation: C - 2 C - C 2 Φ Φ2 Φ 3 ΦN C2 C N C - N Φ C (N) Φ Note that the op-amp work only during a small period. They can be multiplexed. Φ - C (2) C () Φ Ν Φ 2 Φ Φ Φ 2 Φ 3 F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/80

81 In order to have same LP transfer function all the integrating capacitors C (), C (2),..., C (n) must be matched. This requirement is overcame with the analog RAM-type scheme. C Φ Analog RAM Φ Ν C Φ Ν ' ' Φ Φ Φ Φ' Φ' Φ C Φ Φ Φ' 2 Φ' 2 F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/8

82 C Or better: Analog RAM Φ Φ Φ N C Φ 2 C Φ Φ Φ Φ Φ Φ Φ 2 C Φ C Φ Φ Φ 3 Problem: Clock feedthrough noise appears at /T Solutions: Pseudo N-path with circulating memory Use of high-pass prototype and z >z -N transformations F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/82

83 FINITE GAIN AND BANDWIDTH EFFECT C If the op-amp has finite gain A 0 the virtual ground voltage is V 0 /A 0 z-transforming: V 0 ( n ) C V n = ( ) V in ( n ) A 0 A 0 V 0 ( n ) A 0 Hz ( ) V o ( z) = = V in ( z) C z C C ( z ) z A 0 A 0 F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/83

84 Comparing H(z) with the transfer function with A 0 H id ( z) = C z ( z ) Hz ( ) H id ( z) H id ( z) = = = C z C A C 0 2 A 0 z A C 0 2 A 0 z 2 2 Substituting z = e st, on the imaginary axis He jωt ( ) H id ( e jωt ) = = C C j A 0 2 A 0 2 A 0 tan( ωt 2) H id ( z) C C A 2C 0 2 A z A 0 z H id ( e jωt ) m( ω) jθ( ω) Magnitude error m( ω) = A 0 C Phase error θω ( ) = C A 0 tan( ωt 2) C A 0 ωt F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/84

85 For the noninverting integrator C2 C V 0 ( n ) C V n = ( ) C V ( n ) in z-transforming and solving Hz ( ) Same magnitude and phase error result A 0 V o ( z) = = V in ( z) A 0 C C C ( z ) z A 0 A 0 V 0 ( n ) A 0 F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/85

86 Effect of the finite bandwidth: C2 C gm vi g m vi C out inpulse response inpulse response e -t/τ e -t/τ =0 C time time τ τ τ C = = ω 0 F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/86

87 Since the charge is injected when the capacitor C is connected to the virtual ground, during this phase the output will display a considerable transient. During the phase when C is disconnected a residual transient is performed by the output. This transient does not correspond to any charge transfer into (off course). If T/2 is comparable with τ or τ 2 we have two effects: Incomplete charge transfer 2 Virtual ground voltage shift, which totally (in real situations) disappears during the successive half clock period value before the charge injection Virtual ground voltage V out immediately after the closure of the switch F F 2 the virtual ground is not settled error due to the incorrect charge transfer time ideal response F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/87

88 If we sample the output during Φ 2 we have only a magnitude error If we sample the output during Φ we have an additional voltage error that will be forgotten. It corresponds to a phase error For inverting and non inverting integrators: m( ω) = e ω C C 0 T 2 2 θω ( ) = e ω C C 0 T cosωt C sinωt C Φ 2 Φ 2 Φ Φ Φ 2 F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/88

89 m( ω) = e C ω C C 0 T 2 2 C2 C Φ 2 Φ Φ 2 θω ( ) 0 Φ Φ 2 Reduction of the finite gain effect: The effect of the finite gain can be reduced with techniques based on principles that similar to the autozero used in comparators. The virtual ground voltage must be sampled and held without changing the output voltage. F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/89

90 During the S/H of the virtual ground voltage the integrating capacitor must be disconnected in order to preserve its stored charge. Φ Φ 2 Φ A simple unity gain closed loop connection destroys the output dependent virtual ground voltage. Φ 2 Φ 2 Φ Cs Φ A slave capacitor C s previously charged to the output voltage helps in solving the problem C2 Φ Φ F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/90

91 The output voltage changes only of the global offset (if C s is not required to integrate charge during Φ 2 ) Φ 2 Φ C s Three solutions: C Φ C s is required to discharge the injecting capacitor C to the global input offset. C s is required to discharge an extra-capacitor, which, during Φ acts as a battery, creating a virtual ground at the node N. Φ Φ Φ 2 N C Φ 2 Φ 2 C I Φ C s Φ 2 Φ Φ Φ F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/9

92 The slave capacitor C s is precharged at (V out -V in ). During Φ 2 if C = C s the charge redistribution between C and C s is such that Vout does not change. Φ Φ A Φ 2 C Φ 2 Φ Cs Φ Notes: The parasitic capacitance of the node A acts as a toggle SC which inject charge into the small C s during Φ 2. Only inverting integrator F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/92

93 Circuit Magnitude error Phase error # = #2 = #3 = Magnitude error is reflected into a frequency error Phase error is reflected into a Q error Same circuit solutions can be applied do SC amplifiers and converters. F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/93

94 FULLY DIFFERENTIAL CIRCUITS Fully differential configurations reduce the clock feedthrough noise and increase the dynamic range. They allow an increase design flexibility C (Φ 2 ) Φ 2 Φ Φ Φ 2 Φ 2 (Φ) Simple integrator (inverting and non inverting) F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/94

95 Immediate sampling (inverting and non inverting) integrator: V in -V in -V in V in Φ Φ2 Φ 2 Φ Φ2 Φ 2 Φ Φ Φ Φ Delayed sampling (inverting and non inverting) integrator: V in -V in Φ Φ2 Φ 2 Φ 2 -V in Φ Φ V Φ in 2 Φ2 Φ 2 Φ F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/95

96 It is possible to reduce the op-amp finite bandwidth dependence by the use of delayed sampling inverting and non inverting integrators along a second order loop. Φ Φ 2 Φ2 Φ Φ Φ2 Φ2 Φ Φ2 Φ Φ Φ2 Φ2 Φ Φ Φ2 F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/96

97 The peaking in the frequency response due to the phase error is strongly reduced It is easy to realize bilinear integrators Vin Φ C Φ Φ2 Φ2 C Vin Φ 2 Φ Φ Φ 2 C2 F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/97

98 LAYOUT CONSIDERATIONS IN SC CIRCUITS A SC circuit is the interconnection of Op-amp Switches Capacitors We have different lines of interconnections: Signal Bias Clock General rules: Separate as far as possible, clock lines and signal lines Top plate of capacitors connected to virtual ground Maximum area switch and, when possible, only one transistor to realize the switch (minimum clock feedthrough) F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/98

99 FLOOR PLANING FOR SINGLE ENDED CIRCUITS CLOCKS SWITCHES CAPACITORS DIGITAL SIGNAL BIAS ANALOG OP-AMPS BIAS Choose the dimension of the capacitor s array in order to fit the opamps dimension Input and output of the op-amps in the proper position F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/99

100 FLOOR PLANING FOR DIFFERENTIAL CIRCUITS CLOCKS SWITCHES CAPACITORS SIGNAL BIAS ANALOG OP-AMPS CAPACITORS SWITCHES DIGITAL CLOCKS F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/00

101 SWITCHES LAYOUT CAPACITOR LAYOUT Use parallel connection of unity capacitors The residual capacitance must have the same perimeter/area ratio as the unity capacitors Common centroid only if is effectively necessary F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/0

102 NOISE IN SC CIRCUITS The noise sources in a SC network are: Clock feedthrough noise Noise coupled from power supply lines and substrate kt/c noise Noise generators of the op-amp The first two sources are the same as in mixed analog-digital circuits. kt/c noise: Consider the simple network: In the on state the switch can be modeled with a noisy resitor v in S C F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/02

103 Noise equivalent circuit: R on 4kTR on f S C The white spectrum of the on resistance is shaped by the low pass action of the R on C filter. The noise voltage across the capacitor C has spectrum: S n,c 2 v nc, = = 4kTR on Hf () 2 f = 4kTR on f ( 2πfR on C) 2 F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/03

104 F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/04 When the switch is turned off the noise voltage v n,c is sampled and held onto C The folding of the spectrum in band-base gives a white spectrum. f S f v n,c f CK/2 *

105 It power (the dashed area) is equal to the integral of S n,c 2 4kTR on f 4kT kt = ( 2πfR on C) 2 df = ( atanx) 2πC 0 = C v nc, 0 Procedure for the noise calculation in SC networks: Assume all the noise sources uncorrelated Neglect the direct coupling input-output Consider, in the sampled-data domain, the contribution to the output of each noise source (SC structures op-amps) Superpose quadratically all the contributions F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/05

106 Low-frequency noise reduction techniques: Chopper-stabilization technique Correlated double sampling A F. Maloberti: Design of CMOS Analog Integrated Circuits - Continuous Time and Switched Capacitor Filters 8/06