Performance Evaluation and Review of System Protection Scheme Design with the help of Synchrophasor Measurements

Transcription

1 Performance Evaluation and Review of System Protection Scheme Design with the help of Synchrophasor Measurements P. Mukhopadhyay V. Pandey Rajkumar Anumasula Chandan Kumar Sunil Patil Srinivas Chitturi Malla Mahendranath NASPI Work Group meeting and first International Synchrophasor Symposium 1

2 Outline WAMS in India Progress Update System Protection Schemes in India Case Studies- Performance Evaluation and Review of SPS Summary 2

3 WAMS in India 2015 Integration of PMUs Regional Level National Level Substations : 62 PDCs : 11 PMUs : 62 3

4 WAMS in India 2016 Integration of PMUs State Level Regional Level National Level Substations : 103 PDCs : 13 PMUs : 154 4

5 System Protection Schemes (SPS) in India Total Number of SPS in India : 129* Wide Impact SPS in WR Grid Control Actions Total Percentage Load Rejection 20 59% NR Grid NER Grid Generation Rejection 7 21% Generation and Load Rejection 6 18% HVDC Control 1 3% Local Impact SPS in WR Grid Control Actions Total Percentage Load Rejection 34 92% Generation Rejection 3 8% WR Grid Total SPS : 71* SR Grid ER Grid *Upto Dec-15 Source: SPS in India (POSOCO) 5

6 Performance Evaluation and Review of SPS Case Study-I 6

7 Assessing Speed of the SPS Two Analog, Six Digital Inputs U#1 Bus-A 1 Bus-B Ckt 1 Trip Ckt 2 Trip Gen > P 1 MW SPS Action : Trip U#4 SPS-1 U#2 2 3 Bus-C Combination of any 2 of 6 ckts Trips Ckt 5 P Ckt 6 P SUM Gen > P 1 MW >P 2 MW SPS Action : Unloading of U#4 and other unit SPS Action : Unloading of U#4 and other unit SPS-2 SPS-3 U#3 U#4 U#5 PMU Bus-D 7

8 Assessing Speed of the SPS contd. U#1 U#2 Bus-A Bus-B Bus-A Bus-B Bus-A Bus-B U#1 U# Bus-C U#2 Bus-C U# Bus-C U#3 4 U#3 4 U#3 4 U#4 5 Bus-D U#4 5 Bus-D U#4 5 Bus-D U#5 6 U#5 6 U#5 6 t=0 Occurrence of an Event t 1 =11 min 13 sec 3 msec SPS-2 criteria satisfied Envisaged Action : Units unloading t 2 =11 min 13 sec 724 msec SPS-3 criteria satisfied Envisaged Action : Units unloading 8

9 Assessing Speed of the SPS contd. Delay observed in Unit Unloading Observation through PMU 9

10 Revised SPS Design & Performance SPS Logic Modified Delay in unit unloading is rectified Any 2 ckts Trips P 1 < Gen > P 2 MW SPS Action : Trip U#4 SPS-1 Performance of Modified SPS Successful Operations : 7 Unsuccessful Operations : 0 Unnecessary Operations : 0 Number of Failures : 1 Any 1 ckt Trips P 1 < Gen > P 2 MW SPS Action : Unloading of U#4 SPS-2 Any 2 ckt Trips Any 1 ckt Trips Remote 2 ckt Trips Gen > P 2 MW Gen > P 2 MW Gen > P 2 MW SPS Action : Trip U#4 & Unloading of other Unit SPS Action : Unloading of U#4 & other Unit SPS Action : Unloading of U#4 & other Unit SPS-3 SPS-4 SPS-5 * Upto Dec-15 10

11 Performance Evaluation and Review of SPS Case Study-II 11

12 Assessing Dependability of the SPS One Analog, Two Digital Inputs Grid 1 Direct Link PMU S/C ckt in service P >=400 MW/second SPS Actions Wide Band 765 kv S/C P SPS Actions Generation Rejection in Grid 1 Load Rejection in Grid 2 Wide Band PMU Grid 2 Communication Link 12

13 Assessing Dependability of the SPS contd. Number of Operations : 24* Successful Operations : 23 Unsuccessful Operations : 0 Unnecessary Operations : 1 Failures : 0 SPS is disabled SPS triggered irrespective of power flow direction *Up to Dec-15 13

14 Performance Evaluation and Review of SPS Case Study-III 14

15 Assessing Dependability of the SPS Two Analog Inputs Ckt I P SUM >=1500 MW Delay 2.5s Direct Link PMU Grid 1 Ckt II P >=2000 MW SPS Actions Wide Band kv D/C SPS Actions Generation Rejection in Grid 1 Load Rejection in Grid 2 Wide Band PMU Grid 2 Communication Link 15

16 Assessing Dependability of the SPS contd. Number of operations : 15 Successful Operations : 15 Unsuccessful Operations : 0 Unnecessary Operations : 0 Failures : 0 Introducing time delay reduced frequent operation of SPS *Up to Dec-15 16

17 SPS Design Case Study-IV 17

18 SPS Design Bus-A Tripping of any one of four Ckts, oscillations are observed in Grid Tripping of other Ckt on Power Swing 1 2 U#1 Bus-B U#3 Bus-C U#4 U#2 Voltage Level 1 3 4Voltage Level 2 Bus-D Bus-E 18

19 Four Analog, Four Digital Inputs SPS Design Contd. Ckt 1 Trip Ckt 2 Trip Power Swing on Ckt 1 or Ckt 2 SPS Actions Ckt 3 Trip Ckt 4 Trip Power Swing on Ckt 3 or Ckt 4 SPS Actions SPS Actions Trip any one Unit Blocking tripping of other line on Power Swing 19

20 Synchrophasor measurements aided in assessing performance of SPS Synchrophasor measurements helped System Operator in reviewing SPS Synchrophasor measurements assisted in taking corrective actions to prevent undesirable or delayed SPS actions Using Synchrophasor measurements characteristics of SPS Dependability Speed Sensitivity are Evaluated Summary 20

21 References [1] System Protection Schemes In Power Networks, CIGRE Task Force, June 2001 [2] Industry Experience with Special Protection Schemes, IEEE Transactions on Power Systems, Vol. 11, No. 3, August 1996 [3] Deployment of System Protection Schemes for Enhancing Reliability of Power System, International Conference on Power System 2011, IIT Madras, Dec 2011 [4] Synchrophasors Initiative in India, June 2012, POSOCO [5] Synchrophasors Initiatives in India December 2013, POSOCO [6] Report on System Protection Schemes, May 2015, POSOCO [7] 21

22 srinivasch@posoco.in WRLDC, Mumbai