Impact of Device Scaling on Deep Sub-Micron Transistor Reliability - A Study of Reliability Trends Using SRAM

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1 Impct of Device Scling on Deep Sub-Micron rnsistor Relibility - A Study of Relibility rends Using SRAM Mrk White,, Bing Hung, Jin Qin, Zvi Gur, Michel lmor,, Yun Chen, Json Heidecker, Duc Nguyen, Joseph Bernstein Jet Propulsion Lbortory, Cliforni Institute of echnology, Psden, CA 99 University of Mrylnd, College Prk, MD 74 Phone: Emil: Mrk.White@jpl.ns.gov Abstrct. As microelectronics re scled in to the deep sub-micron regime, users of dvnced technology CMOS, prticulrly in high-relibility pplictions, should ressess how scling effects impct long-term relibility. An experimentl bsed relibility study of industril grde SRAMs, consisting of three different technology nodes, is proposed to substntite current ccelertion models for temperture nd voltge life-stress reltionships. his relibility study utilizes Step-Stress techniques to evlute memory technologies (.5um,.5um, nd.3um embedded in mny of tody s high-relibility spce/erospce pplictions. wo ccelertion modeling pproches re presented to relte experimentl FI clcultions to Mfr s qulifiction dt. I. Introduction. he desire to ssess the relibility of emerging technologies through fster relibility trils nd more ccurte ccelertion models is the precursor for further reserch nd experimenttion in this field. Rmpvoltge nd constnt-voltge stress tests to determine voltge-to-brekdown nd time-to-brekdown, coupled with temperture ccelertion cn be effective methods to identify nd model the criticl stress levels nd relibility of emerging deep-sub micron microelectronics. While trget product lifetimes for mil-product re generlly yers t mximum rted junction temperture, leding edge commercil-off-the-shelf (COS microelectronics my be somewht less due to reduced cost consumer electronics nd reduced sfety mrgins, including design life, s result of incresed power nd therml densities, incresed performnce chrcteristics, nd device complexity. [] his relibility study utilizes Step-Stress techniques to evlute some of the more recent memory technologies (.5um,.5um, nd.3um embedded in mny of tody s high-relibility spce/erospce pplictions to substntite current ccelertion models for temperture nd voltge life-stress reltionships. he purpose of this study is to develop better understnding of the impct of deep submicron technology scling trends on microelectronics relibility. It lso provides n independent ssessment nd vlidtion of current ccelertion models for users of scled CMOS devices. II. Filure Mechnisms & Modeling. Accelerted life testing of memories in this experiment is bsed on the ssumption tht vrious filure mechnisms re ccelerted when elevted stress levels re pplied to the operting component. he primry wer-out filure mechnisms include electromigrtion (EM, stress migrtion (SM, timedependent-dielectric-brekdown (DDB, therml cycling (C, nd negtive bis temperture instbility (NBI. he elevted prmeters of concern re the mbient temperture [] nd the component operting voltge [V]. he models for evluting the ccelertion fctors include Arrhenius for temperture, nd Inverse Power or Exponentil for voltge. [] he ccelertion models nd prmeters for vrious filure mechnisms remin uncertin for dvnced technology CMOS devices, e.g. linerity, interctions between the stresses etc. Prior work by Srinivsn [3] nd others re tbulted in ble, which shows the reltive dependencies on temperture, voltge, nd feture size of the primry wer-out filure mechnisms of interest. ble. Summry of EM, SM, DDB, nd C dependencies on temperture, voltge, nd feture size. he reltionship between EM nd temperture is given by the following reltionship [4]: EM E EM n k ( J e ( where J is the current density in the interconnect, E is the ctivtion energy for EM, k is Boltzmnn s constnt, nd is bsolute temperture in Kelvin. Higher operting tempertures will be seen with smller technology nodes, therefore ccording to eqution, more EM filures cn be expected. he reltionship between SM nd temperture is given by the following reltionship [4]: SM o m ESM k e (

2 where is the bsolute temperture in Kelvin, o is the stress free temperture of the metl (the metl deposition temperture, nd m nd E re mteril dependent constnts. emperture ffects stress migrtion filure rte in two wys:. here is n exponentil dependence on temperture which is detrimentl to relibility.. here is the - o -m term in eqution which hs positive effect on relibility. he exponentil term overshdows the other term, which mens SM decreses, nd therefore relibility decreses, with incresing temperture. he reltionship between DDB nd temperture is given by [4]: DDB b Y X + + Z k e (3 V where is the bsolute temperture in Kelvin,, b, X, Y, nd Z re fitting prmeters, nd V is the voltge. Decresing gte oxide thickness with scling decreses relibility due to incresing gte lekge nd tunneling current, I lek. he men-time-to-filure due to gte oxide brekdown is directly proportionl to the vlue of I lek. nd increses by one order of mgnitude for every.nm reduction in gte oxide thickness [4]. As result, if gte oxide thickness reduces by t ox with scling then DDB reduces by tox/. where the reduction in gte oxide thickness, t ox, is expressed in nnometers. For ultr-thin gte dioxides (< few nnometers, DDB is inversely proportionl to the totl gte oxide surfce re. According to eqution 3, DDB is lso dversely ffected by temperture, in which the dominting term is the exponentil. Permnent dmge ccumultes every time there is cycle in temperture in VLSI devices, eventully leding to filure. Ftigue due to therml cycling hs the most impct t the pckge nd die interfce. he pckge goes through two types of therml cycles: lrge cycles which occur t low frequency (due to powering up nd down, nd smll cycles which occur t much higher frequency (due to vritions in ppliction behvior. he effect of smll therml cycles hs not been well studied nd vlidted models re not vilble [4]. he reltionship between lrge therml cycles nd temperture is given by [4]: C verge mbient q (4 where mbient is the mbient temperture in Kelvin, verge mbient is the verge lrge therml cycle structure on the chip experiences, nd q is the Coffin-Mnson exponent, n empiriclly determined mteril-dependent constnt. Like EM nd SM, the min impct of scling on C is the impct of temperture. Scling hs no other direct impct on therml cycling. NBI is n effect tht surfced s gte oxide thickness ws scled. Gte oxide thickness for the 3-nm technology node hs lredy resulted in sensitivity to NBI. As the scling of MOSFEs continues, NBI becomes more prominent issue in more current VLSI technology. It my become one of the ultimte limiting fctors since NBI is more severe thn hot crrier stress for ultr-thin oxides t low electric fields [5]. he NBI effect is more severe for PMOS FEs thn NMOS FEs due to the presence of holes in the PMOS inversion lyer tht re known to interct with the oxide sttes [6]. In CMOS devices, the NBI-induced threshold voltge shift will occur over period of months or yers, depending on the operting conditions of the device. Clerly, this mens serious relibility issues for devices in terms of endurnce nd retention. NBI is most problemtic for high-performnce or high-relibility devices, nd nlog/mixed-signl devices re more susceptible thn digitl devices. III. Experimenttion. Memory devices re excellent cndidtes for experimenttion to demonstrte the ccurcy nd ppropriteness of nlyticl models tht hve been proposed to chrcterize the life-stress reltionship of present-dy microelectronic devices. Voltile Sttic Rndom Access Memory (SRAM devices re rrnged in mtrix rry nd storge of dt occurs within memory cells. hese cells typiclly include between 4-6 trnsistors tht form the inverter circuits nd flip-flops, which re cpble of ssuming two sttes. Becuse the mtrix rry is designed for repetitive write-red cycles, lrge mounts of performnce relibility dt my be obtined through experimenttion with reltively smll quntities of commercil SRAM devices; technologies my be compred nd contrsted with experimenttion of rnge of technology nodes. A step-stress ccelerted test technique ws implemented to evlute Mb (.5um, 4Mb (.5um nd 6Mb (.3um SRAM devices of similr cell designs configured in 8K x 8b, 56K x 6b, nd M x 6b words respectively. Reference bles nd 3. Devices were subjected to repetitive Write/Red cycles consisting of four dt vlues for ech memory cell or ddress t ech stress step. Voltge ws held constnt while temperture ws steppedup, nd then temperture ws held constnt while voltge ws stepped-up. As stress conditions incresed (voltge nd temperture, bit filure times were red nd recorded until devices ctstrophiclly filed.

3 Underlying gols of this experiment were to: Clculte the FI bsed on the test sttistics without the physicl models Vlidte the models nd prmeters upon filure investigtion Segregtion nd dt nlysis Clculte the FI using those models Compre nd contrst to Mfr s FR dt Determine if experimentl results support lifetime relibility predictions cross scled technologies A comprison of the results will then introduce more ccurte sttisticl models nd/or dt fitting into existing physicl filure model pproches, e.g. Inverse Power, Exponentil, etc. ble. Step-Stress Conditions ( Stress Conditions emp [ C] V/Vnom ime [hrs] stress level stress level stress level stress level stress level stress level stress level stress level ble 3. Step-Stress Conditions (b Stress Conditions emp [ C] V/Vnom ime [hrs] stress level stress level stress level stress level stress level stress level stress level IV. Discussion & Results. ble 4 shows expected bit filure rtes compring Inverse Power nd Exponentil Voltge ccelertion models nd the mnufcturer s life test dt. Cumultive weighted test times were clculted for ll stress opertion levels. otl equivlent operting times were clculted for both Exponentil nd Power Lw Models, nd filure rte ( ws clculted t 55 C nd nominl operting voltge. Evlution of the filure rte ws conducted t 6% confidence using Relisoft Alt softwre for mximum likelihood estimtion with the ssumption of constnt filure rte. Cumultive weighted times were clculted to represent ll the stress opertion levels. wo bsic ssumptions were mde: Cse reflects the ssumption tht there is only one dominting filure mechnism nd the others re neglected; Cse reflects the ssumption tht there is no dominting filure mechnism, nd tht ll re eqully likely. According to the ssumptions outlined in Cse nd Cse, two models were pplied: ( Multipliction of s (temp. nd voltge using both Exponentil nd Power Lw Models: = t * v(e nd = t * v(p; nd (b A proposed weighted sum model of the s where 3 = (t + v(e/ nd 4 = (t + v(p/. hese equtions re expnded s follows: E = V (, V k γ (, V = = exp exp( ( V V (5 (, V E (6 = = = exp ( V / V k V (, V k (7 (, V E 3 = = ( + V / = (exp + exp( ( V V / (, V k γ (8 (, V E 4 = = ( + V / = (exp + (, V k ( V / V / k Equtions (7 nd (8 my be expnded for n independent filure mechnisms where nd LFMi represents the i th filure mode t ccelerted conditions, nd usefmi represents the i th filure mode t norml conditions. then my be expressed s (9 ssuming filure modes hve equl frequency of occurrence during the use conditions [7]: + (9 use FM use FM use FMn n i= = usefm + use FM use FMn he proposed weighted sum Exponentil Model (7 best correltes the mnufcturers published dt (7- FI to the experimentl dt (9.48 FI, normlized to 55C nd nominl Vdd operting conditions. Reference ble 4. he ccurcy of n estimte is given by its stndrd error nd confidence intervl. he estimtes pproximte the true prmeter vlues nd the confidence intervls for model prmeters indicte the uncertinty in the sttisticl estimtes by their width. Sttisticl confidence bounds do not ccount for model uncertinty. herefore, sensitivity nlysis is importnt in ny quntittive nlysis involving uncertinty nd for ssessing the effects of model uncertinty. In this experiment, model uncertinty ws ddressed by nlyzing different model ssumptions nd different models to determine the best fit scenrio between the test results, prior SRAM test results, nd the mnufcturer s filure rte qulifiction dt. Mximum Likelihood methods were used to provide the estimtes nd confidence limits for the model prmeters. = n n i 3

4 ble 4. Step-Stress Accelerted est Results Compred to Mnufcturer s Dt 65 Mb -.5um SRAMs est level Cumulted test time Equivlent op. voltge Cse (Multipliction v Exp. Model ( v Power lw ( Cse (Weighted Sum v Exp. Model ( v Power lw ( stress level stress level stress level stress level stress level stress level E stress level E+ 9.4E stress level E+.8578E otl equiv. time: E E Filure &Vnom (FI Filure rte reported by Mnuf: 7 FI Cse refers to ssumption. Cse refers to ssumption b. ( - Voltge Accelertion Fctor ccording to Exponentil. Model (γ = 7 ( - Voltge Accelertion Fctor ccording to Power Lw Model (k=34 (3 Mfr s FI reported t 6% CL. AL comprison lso t 6% CL. Cummultive Filures (% VRtio emp C ime (Hrs Figure. ime-to-fil (.% s function of Vrtio nd emp (C Exmintion of the component filure times show tht t specific times, lrge numbers of bit filures were recorded. he filures tht were recorded t the sme time represent single filure event which ws reflected on multiple ddresses nd therefore, counted s single filure for relibility evlution. Hrd nd soft filures were treted eqully in the relibility evlution becuse once soft filure hs occurred in high-relibility, remote ppliction, e.g. n un-repirble system, the ddress corresponding to the filure re circumvented nd not used in future write cycles. ble 5 shows technology node nd stress conditions vs. ccumulted time to filure of.% of the bits in device. Cummultive Filures (% VRtio emp C e e-4.5e-5 4Mb -.5um SRAMs ble 5. echnology node nd stress conditions vs. time to filure of.% of the bits in device. ech. Node Vrtio (Vpp/Vnom emp C ime (Hrs to.% Device- Bit Filures / Filure rte, Vrtio stress, nd temperture re plotted over time in Figures, nd 3 for three different technology nodes. Cummultive Filures (% V Rtio emp C ime (Hrs Figure. ime-to-fil (.% s function of Vrtio nd emp (C Mb -.3um SRAMs ime (Hrs Figure 3. ime-to-fil (.% s function of Vrtio nd emp (C V. Conclusion. An experimentl bsed relibility study of industril grde SRAMs consisting of three different technology nodes ws conducted to substntite current ccelertion models for temperture nd voltge life-stress reltionships. wo different ccelertion models were tested 4

5 to relte experimentl FI clcultions to Mfr s qulifiction dt; the weighted sum exponentil model best correlted. While time-to-fil cross technology nodes were generlly of similr mgnitudes, the V stress rtio (incresed V dependency ppers to be primry filure mechnism driver with smller technology nodes. Experimentl results do support reduced lifetime relibility predictions s technologies re scled. Filure nlysis to identify root cuse filure mechnisms nd further experimenttion with 9 nd 65-nm technology nodes is wrrnted. VI. Acknowledgements. he work described in the pper ws conducted t the Jet Propulsion Lbortory, Cliforni Institute of echnology in collbortion with the University of Mrylnd. REFERENCES [] White, M, et l., Impct of Junction emperture on Microelectronics Device Relibility nd Considertions for Spce Applictions, IEEE IRW (3. [] Meeker W. nd Escobr L., Sttisticl Methods for Relibility Dt, John Wiley nd Sons, c 998. [3] Srinivsn, Adve, Bose, Rivers. "he Impct of echnology Scling on Lifetime Relibility." Interntionl Conference on Dependble Systems nd Networks. June 4. [4] "Filure Mechnisms nd Models for Semiconductor Devices." JEDEC Publiction JEP-A,. [5] Zhu, Suehle, Bernstein, nd Chen. "Mechnism of Dynmic NBI of pmosfes." Integrted Relibility Workshop Finl Report, 4 IEEE Interntionl, 4. [6] Peters, Lur. "NBI: A Growing hret to Device Relibility." Semiconductor Interntionl. [7] lmer, et l. Competing Filure Modes in Microelectronic Devices nd Accelertion Fctors Modeling, Intl. Symposium on Stochstic Models in Relibility, Sfety, Security nd Logistics, Feb. 5 Proceedings, Isrel. 5

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