Hardware Implementation of Multiple Vector Quantization Decoder

Transcription

1 54 IJCSNS Internatonal Journal of Computer Scence and Networ Securty, VOL.8 No., November 008 Hardware Implementaton of Multple Vector Quantzaton Decoder Nortaa Shge, Hrom Myajma, Shngo Hashguch, Mchharu Maeda, Lxn Ma Kagoshma Unversty, Kagoshma, Japan Fuuoa Insttute of Technology, Fuuoa, Japan Unversty of Shangha for Scence and Technology, Shangha, Chna Summary Vector Quantzaton (VQ) s successfully appled to data compresson. In mage compresson, Multple-VQ wth Index Inference (MVQII) can provde a much better restored mage qualty than conventonal VQ methods. However, the ndex nference ncreases the computatonal complexty of the decodng process n proporton to the number of weghts. In ths paper, n order to accelerate the decodng process of MVQII, we present three types of dgtal crcut desgn for the decoder. The presented desgns are mplemented on FPGAs and are evaluated n terms of operatng speed, processng tme. The results show that two versons acheve good mprovement n processng speed at reasonable expenses of crcut sze and that the fastest verson s nearly ten tmes faster than a software mplementaton on a modern standard computer. Key words: Vector quantzaton, decoder, multple vector quantzaton, dgtal crcut, FPGAs.. Introducton Vector Quantzaton (VQ) s a process for approxmatng a large set of nput vectors by a smaller set of weght vectors. VQ s a useful technque n many applcatons such as data compresson, data mnng and pattern recognton [,,4]. VQ s successfully appled to data compresson [8]. However, the qualty of the restored data greatly depends on the number of weghts (codeboo sze) and the dmenson of weghts (bloc sze). One of the methods relaxng the trade-off s Multstage Resdual VQ (MRVQ), n whch multple quantzers are concatenated n seres []. In MRVQ, the frst stage quantzer operates on the nput vectors, and the second stage operates on the errors between the nput vector and the frst stage output. MRVQ s a seral approach. On the other hand, we have proposed multple-vq (MVQ) as a parallel approach [3]. The MVQ method performs ndependently multple VQ processes, and combnes the ndependent low qualty results nto a hgh qualty one. We have shown that, wth the useful technque ndex nference, MVQ wth Index Inference (MVQII) s effectve n data compresson [5,6]. However, the ndex nference ncreases the computatonal complexty of decoder n proporton to the codeboo sze. For example, when decoders wth κ codeboo vectors are mplemented on a CPU, an MVQII decoder has κ tmes lower throughput than conventonal VQ decoders. Dgtal crcut mplementaton s effectve n terms of processng speed and power consumpton when compared wth software mplementaton on a general purpose PC. Some systems based on VQ have been mplemented n dgtal crcuts [9,0,]. In [9], a speaer dentfcaton system based on VQ has been mplemented n FPGAs. In [0], a processor for self-organzng map (SOM), whch s one of VQ methods[4], has been mplemented n FPGAs. In [], a systolc archtecture of SOM has been proposed and also mplemented n FPGAs. In ths paper, n order to accelerate the decodng process of MVQII, we study hardware mplementaton of MVQII decoders. Specfcally, we present three types of dgtal crcut desgn for the decoder. The frst one s a nave mplementaton, and the second and thrd ones are mproved versons, respectvely, wth ppelne and parallelzaton. The presented desgns are mplemented n FPGAs and are evaluated n terms of operatng speed, processng tme and crcut sze. The results show that the last two versons acheve good mprovement n processng speed at reasonable expenses of crcut sze and that the parallel verson s nearly ten tmes faster than a software mplementaton on a modern standard computer. The rest of ths paper s organzed as follows. Secton descrbes VQ, MVQ and MVQII, and shows some smulaton results for performance comparson. Secton 3 presents our proposed dgtal crcut desgns for MVQII decoder. Secton 4 shows the performance evaluaton results. Fnally, secton 5 concludes the paper and presents future wors.. Vector Quantzaton and Multple Vector Quantzaton. Vector Quantzaton Vector Quantzaton (VQ) s to approxmate a large set of nput vectors X = { x, L, xν } by a smaller set of weght n vectors W = { w, L, wκ }, where x, w R j are n- dmensonal Eucldean vectors and X s a random sample from a probablty densty functon (PDF) p( x ). W and Manuscrpt receved November 5, 008 Manuscrpt revsed November 0, 008

2 IJCSNS Internatonal Journal of Computer Scence and Networ Securty, VOL.8 No., November w j are also referred to, respectvely, as codeboo and codeboo vector. In VQ, an nput vector x X s replaced wth a weght vector w wn W such that d( xw, wn ) = m n {, L, κ} d( xw, ), where d ( xw, ) = x w. In other word, the VQ process dvdes n the nput space R nto κ sub-spaces S, L, such that n S = { x R d( xw, ) d( xw, l ), l}. The approxmaton accuracy of VQ s evaluated n terms of the average dstorton error E = ( xw, ). x ν S κ d {, L, κ} S A fundamental method mnmzng the error E s Compettve Learnng (CL), whch s based on gradent descent [4]. The CL procedure terates a smple adaptaton step. At t-th teraton, the CL procedure calculates the closest weght (called wnner) w to a gven nput vector x X, and then updates w wn as follows: w w ()( ), wn + ε t x w wn wn where d( xw, wn ) = mn {, L, κ} d( xw, ) and ε ( t) s a learnng rate decreasng wth t.. VQ based Image Compresson Ths secton descrbes sngle-vq based data compresson (SVQ). We assume G-bt gray mages of G M N pxels. Let p, j {0, L, } ( {, L, M}, j {, L, N} ) be the gray level of the pxel at coordnates (, j ). Then an mage s represented as an M N matrx P =. The algorthm SVQ s as follows. ( p, j ) Algorthm SVQ Step (Input Preparaton) Gven an nput mage P. The M N pxels n P are dvded nto ( M N)/( J K) blocs of sze J K. The blocs are represented as JK-dmensonal vectors x, L, xmn/( JK). Step (Vector Quantzaton) The set of weght vectors W = { w, L, wκ }, called codeboo, s traned by usng the set of vectors X = { x, L, xmn /( JK )} as nput data. The tranng s performed by Eq.. Step 3 (Index Calculaton) For each {, L, MN / ( JK)}, the ndex number l s calculated, where d (, w ) = n d( x, w ) End of SVQ. wn x l m j {, L, κ} j. The compressed data s composed of the codeboo W and the ndex sequence L = ( l, L, l MN /( JK )). From W and L, an mage s restored. In the restored mage, each bloc x X n the orgnal mage s replaced wth w l. The qualty of the restored mage s evaluated n terms of mean square error (MSE) as follows: MSE( X, W, L) = d ( x, ) {,, MN/ ( JK)} w L l MN.3 Multple-VQ based Image Compresson In ths subsecton, we descrbe multple-vq (MVQ) and ndex nference for mage compresson. The fundamental dea of MVQ s that a hgh qualty mage can be created by averagng multple low qualty mages that ndependently restored from dfferent pars of codeboo and ndex sequence. The MVQ algorthm for compresson phase s as follows. Algorthm MVQ Step (Input Preparaton) From the nput mage P, two nput data sets and X are generated as follows: ( c) ( c) MN X = { x {, L, }} for c {0,}, JK c c ( c) x = ( pφ(, c,), ψ(, c,), L, pφ(, c, J ), (,,), c ψ c pφ(, c,), ψ(, c,), L, pφ(, cj, ), (,,), c ψ c L p, L, p ), φ(, c,), ψ(, ck, c) φ(, cj, c), ψ (, ck, c) X where M φ ( c,, j) = ((( )mod ) Jc + c+ j ) modm + Jc and M ψ (, c, j) = (( d )/ t Kc + c+ j ) modn +. Fg. s a Jc ( ) schematc explanaton of x c. Step (Vector Quantzaton) Perform VQ twce to generate two codeboos W by usng data sets X and X, respectvely. The tranng s performed by Eq.. Step 3 (Index Calculaton) The ndex sequence L = ( l, L, l MN /( J 0 K 0) ) s calculated from W. End of MVQ. In Step, two codeboos W and W are generated from dfferent nput data sets X and X, respectvely. The use of dfferent data sets s an essental requrement for obtanng a good qualty [4]. ()

3 56 IJCSNS Internatonal Journal of Computer Scence and Networ Securty, VOL.8 No., November 008 (a) For X. Now, after ndex nference, we have W, W, L and L = ( l, L, l MN J K ). Next, two mages P % and /( ) P % are ndependently restored from two pars ( W, L ) and ( W, L ), respectvely. And then, a restored mage P% = ( p% j, j ) s generated by combnng the two restored mages as follows. p%, j= ( p%, j+ p%, j ), (3) ( c) ( c) where P% = ( p%, j ) for c {0,}. In the followng, the method descrbed n ths secton s referred as MVQ wth Index Inference (MVQII). (b) For X. Fg. Segmentaton of P for generatng ( c) X In Step 3, only L s calculated, and the compressed data are W, W and L. If, n addton to the compressed data, L s used, a better qualty mage can be restored. However, n ths case, the compressed data sze sgnfcantly ncreases, and as a result, the restored mage qualty s too low for a fxed data sze. Instead, the lost data L s restored by a decoder sde technque ndex nference []. The algorthm s as follows. Algorthm MVQ wth Index Inference Step (Image Restoraton by SVQ) Restore an mage P% = ( p%, j ) from W and L. Step (Input Preparaton for Inference) From the restored mage P %, an nput data set X % = { x%, L, x% MN /( J K) } s generated as n Eq. (). Step 3 (Index Calculaton) For each {, L, MN / ( JK)}, the ndex number l s calculated, where d ( x%, w% ) = mn j {,, κ} d( x% L, wj ). End of Index Inference. l (a) Lena Fg. Test mages..4 Performance Comparson (b) Goldhll In order to demonstrate the effectveness of MVQII, we show some smulaton results on SVQ, MRVQ (Multstage Resdual VQ) and MVQII. SVQ s the algorthm descrbed n Sect... MRVQ s performed by a software pacage QccPac[7]. For MRVQ, the number of stages s two and each stage uses the same codeboo sze. MVQII s performed wth J0 K0 = 4 4, J K = and κ0 = κ. The used test mages are shown n Fg.. The two mages conssts of 5 5 pxels of 56 gray level, that s M = N = 5. The smulaton results are shown n Fg. 3, where the compresson rate s the rato of the orgnal data sze ( bts) to the compressed data sze (the total sze of codeboos and ndex sequence). For all mages, MVQII acheves the best performance among all the methods when the compresson rate s hgh.

4 IJCSNS Internatonal Journal of Computer Scence and Networ Securty, VOL.8 No., November MSE MSE SVQ MRVQ MVQII SVQ MRVQ MVQII Compresson rate (a) For Lena Compresson rate (b) For Goldhll. Fg. 3 MSE versus compresson rate for SVQ, MRVQ and MVQII. 3. Hardware Implementaton of MVQII Decoder MVQII descrbed n the prevous secton requres O( κ) tmes as more tme as SVQ method, because unle SVQ, MVQII requres fndng nearest weghts for W as n Step 3. In ths secton, n order to accelerate the decodng process of MVQII, we present ts hardware mplementaton. 3. MVQII Algorthm for Hardware Implementaton In ths subsecton, we rewrte the MVQII algorthm nto a form sutable for hardware mplementaton. As a prelmnary step, we gve some defntons. ( c) x% = ( p% φ(, c,), ψ(, c,), L, p% φ(, c, J ), (,,), c ψ c p% φ(, c,), ψ(, c,), L, p% φ(, cj, ), (,,), c ψ c L p%, L, p% ), φ(, c,), ψ(, ck, c) φ(, cj, c), ψ(, ck, c) where P% = ( p% j, j ) s the matrx that wll store the fnal restored mage. When J = J0 = J and K = K0 = K, the rewrtten verson s gven as follows. Algorthm MVQII for Hardware Implementaton Input: W = { w, L, w }, W = { w, L, w }, κ0 L = ( l, L, l MN /( JK )) Output: P% = ( p% j, j ) : For : = to M / J do : x% wl 3: End for 4: For j: = to N / K do 5: x% jm / J + wl jm / J + 6: For = to M / J do 7: x% w jm / J + l jm / J + 8: * Fnd w W such that 9: d( x% w ( x% 0: * x% jm / J + ( x% jm / J + +w ) : End for : End for κ * ) jm / J +, ) = mn d w W jm / J+, w) The dfference between two versons s that the above verson does not explctly calculate the ndex sequence L. Although we assume J 0 = J and K0 = K, the algorthm can be generalzed by modfyng lnes 5 and 7 to f statements. The statements from lnes 7 to 0 can be processed n ppelne fashon. 3. MVQII Hardware Desgn We mplement the proposed MVQII algorthm on FPGA. We present three dfferent crcut desgn: (I), (II) and (III). Crcut Desgn (I) The top vew of desgn (I) s shown n Fg. 4. In the fgure, a box wth > means a synchronous crcut bloc and the other boxes are combnatoral crcut blocs. Note that a synchronous crcut bloc must be connected wth a cloc lne and some control sgnal lnes, whch are omtted for smplcty n the fgure. The desgn conssts of a

5 58 IJCSNS Internatonal Journal of Computer Scence and Networ Securty, VOL.8 No., November 008 counter, four RAMs, combnatoral crcut unts Average and Fnd Nearest. Four RAMs store L, W, P % and W, respectvely. The Counter sequentally outputs memory addresses of l L, w W, x% and x%. The unt Fnd Nearest outputs the closest weght * w W to x%, after w, L, wκ are nputted. That s, for a gven x%, the calculaton requres κ clocs. Ths unt, whch s a ey module n our desgn, wll be * explaned n detal later. And then, the average of w and x% s calculated and wrtten to RAM P %. Fg. 5 shows the nsde of the unt Fnd Nearest for desgn (I). The unt DIST calculates d = x% w by performng subtracton and squarng. The unt CMP performs the comparson between d and d mn. If d < dmn then CMP sets f =. Otherwse t sets f = 0. The sgnal f s used as the enable sgnal of two regsters. That s, f f = then the two regsters latch d mn and w. The operatng speed of the desgn (I) s domnated by the unt DIST. Because the unt performs subtracton and squarng and nvolves the longest combnatoral logc path among all logc blocs n the desgn. Fg. 6 The unt Fnd Nearest for desgn (II). Fg. 7 The parallelzed Fnd Nearest n desgn (III). Fg. 4 The top vew of desgn (I). Fg. 5 The unt Fnd Nearest for desgn (I). Crcut Desgn (II) In order to mprove the processng speed, we consder dvdng the most complex logc, DIST, n the desgn (I) nto two parts. The unt Fnd Nearest for the mproved verson, the desgn (II), s shown n Fg. 6. In ths desgn, the unt DIST n desgn (I) s dvded nto two logc blocs SUB & ABS and SQ. The unt SUB & ABS calculates d = ( x w, L, x w ), where x% = ( x, L, ) and κ κ w = ( w,, w ) L κ. The unt SQ calculates dd. Although ths modfcaton can mprove the crtcal path delay n the crcut, two clocs are needed to calculate d = x% w. In order to hde the ncreased step, an addtonal regster REG () s added. Wth REG (), the unt Fnd Nearest operates n ppelne fashon. Its ppelne operaton calculates m closest weghts n m κ + clocs. Crcut Desgn (III) In order to reduce the number of clocs for calculatng the closest weght, we consder the parallelzaton of the unt Fnd Nearest. The parallelzed crcut s shown n Fg. 7. In the crcut, the weght set W s dvded nto two sub-sets W = { w, L, w } and = { w, L w }, whch 0 κ / W κ/+, κ are stored n RAM W 0 and RAM W, respectvely. Two Fnd Nearest unts calculate the closest weghts x κ

6 IJCSNS Internatonal Journal of Computer Scence and Networ Securty, VOL.8 No., November w wn0 W0 and w wn W to x% n parallel. Ths calculaton completes n κ /+ clocs. Note that each Fnd Nearest unt s same as n Fg. 6. The unt SEL outputs wwn = w wn0 for d0 < d and otherwse wwn = w wn. That s, w wn s the closest weght n W. The number of clocs requred for processng Q vectors are summarzed n Table, where Q corresponds to MN /( J ) K. The dfference of requred clocs between desgns (I) and (II) s just one cloc. Desgn (III) needs only about half the number of clocs requred for desgn (I). Table The number of clocs requred for processng Q vectors. Desgn Number of clocs (I) Q( κ + ) + (II) Q( κ + ) + 3 (III) Q( κ /+ ) Implementaton Results We mplement the proposed desgns on FPGA and evaluate ther operatng frequency, processng tme and crcut sze. The desgn envronment s Xlnx ISE Desgn Sute 0., the targeted devce s Spartan E XCS300E, and the desgn s coded n VHDL. Major specfcatons of the mplemented crcuts are summarzed n Table. Table Specfcatons of the mplemented MVQII. Item Spec. Numerc codng 8 bts nteger Dmenson of vectors J =, K = or J =, K = Number of weght κ = 6 vectors The evaluaton results on operatng frequency are shown n Table 3. For any vector dmenson, each desgn operates at almost the same frequency, and the desgn (II) acheves the hghest operatng frequency among all the desgns. Fg. 8 compares our three desgns and a software mplementaton n terms of the processng tme requred for processng Q vectors. The processng tme for each desgn s calculated by dvdng the number of clocs n Table by the operatng frequency n Table 3. Soft ndcates the processng tme (CPU tme) for software mplementaton, where the program compled wth the GNU Compler GCC 4. runs on a GNU/Lnux PC wth.6.4 ernel, Intel Core Quad CPU Q6600 (.40GHz) and 4GB of RAM. Ths result shows that the desgn (III) s the fastest among all the methods. The desgn (III) s about fve tmes, twce and ten tmes faster than (I), (II) and Soft, respectvely. The evaluaton results on crcut sze are summarzed n Table 4. The number of Slce Flp Flops (SFFs) corresponds to the crcut sze of regsters and counters, and the number of 4 nput LUTs (4LUTs) corresponds to the crcut sze of combnatoral logc crcuts. For each desgn type, the extenson from J =, K = to J =, K = ncreases SSFs and LUTs by.67~.95 tmes, because the number of bts for representng the weght vectors s doubled. For each dmenson of vectors, the desgns (II) and (III) use approxmately twce and 4 tmes as many SFFs as the as the desgn (I), respectvely. On the other hand, the desgn (II) uses fewer 4LUTs than the desgn (I), and the desgn (III) uses.69~.78 tmes as many 4LUTs as the desgn (I). Fnally, we menton the dfference between the proposed desgns and a nave mplementaton of algorthm MVQII descrbed n subsecton.3. The algorthm MVQII ntally restore a whole mage P% = ( p%, j ) from W and L, and then calculates the ndex sequence for W. Therefore, the nave mplementaton requres about twce as much clocs as the desgns (I) and (II). Table 3 Maxmum operatng frequency of mplemented crcuts. Desgn J =, K = J =, K = (I) 8.9 MHz 5.38 MHz (II) 75. MHz 7.86 MHz (III) 7.5 MHz 7.38 MHz Table 4 Numbers of slce Flp Flops and 4 nput LUTs for mplemented crcuts. Dm.of # of Slce Flp # of 4 nput Desgn vectors Flops LUTs J (I) 7 04 = (II) 43 7 K = (III) J (I) = (II) K = (III)

7 60 IJCSNS Internatonal Journal of Computer Scence and Networ Securty, VOL.8 No., November 008 Processng tme [sec] (I) (II) (III) Soft 5. Conclusons Number of processed vectors Q Fg. 8 Processng tme for J =, K =. In ths paper, we have presented three types of dgtal crcut desgns for Multple-VQ wth Index Inference (MVQII) decoders. The frst one, whch s a nave mplementaton, s of the smallest crcut sze, but ts operatng speed s slow due to ts long combnatoral path. The second and thrd ones mprove the processng tme by ntroducng ppelne and parallelzaton, respectvely. The latter two versons acheve the good mprovement n processng speed at a reasonable expense of crcut sze. In partcular, the desgn (II) and (III) are about.87 tmes and 5.3 tmes faster than the desgn (I), respectvely, whle the desgns (II) and (III) requre about twce and four tmes larger crcuts than the desgn (I), respectvely. Further, the processng speed of the crcuts (I), (II) and (III) s about.7 ~ 9.5 tmes faster than a software mplementaton on a modern standard computer. Another problem related to MVQII s the tranng process of codeboos, whch s performed n the compresson phase. The computatonal complexty for MVQII s twce larger than for SVQ. One of our future wors s to develop effectve dgtal crcut desgn for the tranng process. [] A. Gersho and R.M. Gray, Vector Quantzaton and Sgnal Compresson, Kluwer Academc Publshers, 99. [3] N. Shge, H. Myajma and M. Maeda, A Multple Vector Quantzaton Approach to Image Compresson, Proc. of Internatonal Conference on Natural Computaton, Lecture Notes n Computer Scence, Vol.36, pp , 005. [4] T. Kohonen, Self-Organzng Maps, Sprnger-Verlag, Berln Hedelberg, New Yor, 997. [5] N. Shge, H. Myajma, M. Maeda and L. Ma, Compresson Rate Improvement of Multple Vector Quantzaton Based Image Compresson, Proc. of Internatonal Conference on Intellgent Technologes, pp.33-40, 005. [6] N. Shge, H. Myajma and M. Maeda, Learnng Algorthm for Multple Vector Quantzaton Based on Image Compresson, Proc. of Internatonal Symposum on Nonlnear Theory and ts Applcatons, pp , 006. [7] J. E. Fowler, QccPac: An Open-Source software Lbrary for Quantzaton, Compresson, and Codng, n Applcatons of Dgtal Image Processng XXII (Proc. SPIE 45), A. G. Tescher, ed., pp.94-30, 000. [8] C. Amerjcx, J.-D. Legat, M. Verleysen, Image Compresson Usng Self-Organzng Maps," Systems Analyss Modellng Smulaton, 43, pp , 003 [9] F.A. Elmsery, A.H. Khalel, A.E. Salama, F. El-Geldaw, "An FPGA Based VQ for Speaer Identfcaton," The 7th Internatonal Conference on Mcroelectroncs, pp.30-3, 005. [0] J.J. Raygoza-Panduro, S. Orega-Csneros, E. Boemo, "FPGA mplementaton of a synchronous and self-tmed neuroprocessor," Proc. of the 005 Internatonal Conference on Reconfgurable Computng and FPGAs, 005. [] I. Manolaos, E. Logaras, "Hgh Throughput Systolc SOM IP Core for FPGAs," Proc. of IEEE Internatonal Conference on Acoustcs, Speech and Sgnal Processng, Vol., pp.6-64, 007. Acnowledgments Ths research s partly supported by the Grant-n-Ad for Scentfc Research (C) (No ) of the Mnstry of Educaton, Culture, Sports, Scence and Technology of Japan. References [] R.M. Gray, Vector Quantzaton,'' IEEE ASSP Magazne, pp.4-9, 984.

8 IJCSNS Internatonal Journal of Computer Scence and Networ Securty, VOL.8 No., November Nortaa Shge receved the B.E., M.E., D.E. degrees from Kagoshma Unversty, Japan, espectvely, n 99, 994, and 997. He s an Assstant Professor n the Dept. of Electrcal & Electronc Eng. at Kagoshma Unversty. Hs research nterests nclude neural networs, dgtal crcut desgn, moble agent system, and energy effcent communcaton n sensor networs. He s a member of the IEEE, the ACM and the IEICE. Hrom Myajma receved the B.E. degree n electrcal engneerng from Yamanash Unversty, Japan, n 974, and the M.E. and D.E. degrees n electrcal and communcaton engneerng from Tohou Unversty, n 976 and 979, respectvely. He s currently a Professor n the Department of Electrcal & Electroncs Engneerng at Kagoshma Unversty. Hs current research nterests nclude fuzzy modelng, neural networs, quantum computng, and parallel computng. Shngo Hashguch receved the B.E. and M.S. degrees n electrcal and electroncs engneerng from Kagoshma Unversty n 006 and 008, respectvely. Hs research nterests have been dgtal crcut desgn and dgtal wreless communcaton system. Currently, he s worng at Fujtsu Mcroelectroncs Lmted, Japan. Mchharu Maeda receved the B.E. and M.S. degrees n theoretcal physcs n 990 and 99, respectvely, and the Ph.D. degree n nformaton and computer scence n 997, from Kagoshma Unversty, Japan. He s currently an Assocate Professor n the Department of Computer Scence & Engneerng at Fuuoa Insttute of Technology. Hs research nterests nclude computatonal ntellgence, mathematcal & physcal computaton, and sgnal processng. Lxn Ma receved the D.E. degree n System Informaton Engneerng from Kagoshma Unversty, Japan n 999. He s currently a Professor at College of Computer and Electrcal Engneerng n Unversty of Shangha for Scence and Technology. Hs research nterests nclude neural networs, fuzzy theory and ts ndustral applcatons.