In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

Size: px
Start display at page:

Download "In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below."

Transcription

1 Important notice Dear ustomer, On 7 February 07 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of or use Instead of sales.addresses@ or sales.addresses@ use salesaddresses@nexperia.com ( ) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - NXP N.V. (year). ll rights reserved or Koninklijke Philips Electronics N.V. (year). ll rights reserved Should be replaced with: - Nexperia.V. (year). ll rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia

2 Rev. 4 august 0 Product data sheet. General description The provides low-power, low-voltage configurable logic gate functions. The output state is determined by eight patterns of -bit input. The user can choose the logic functions MUX, ND, OR, NND, NOR, inverter and buffer. ll inputs can be connected to V or GND. This device ensures a very low static and dynamic power consumption across the entire V range from. V to. V. The is designed for logic-level translation applications with input switching levels that accept.8 V low-voltage MOS signals, while operating from either a single. V or. V supply voltage. The wide supply voltage range ensures normal operation as battery voltage drops from. V to. V. This device is fully specified for partial power-down applications using I OFF. The I OFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across the entire V range.. Features and benefits Wide supply voltage range from. V to. V High noise immunity ESD protection: HM JESD-4F lass exceeds 000 V MM JESD-- exceeds 00 V DM JESD-0E exceeds 000 V Low static power consumption; I =. (maximum) Latch-up performance exceeds 00 m per JESD 78 lass II Inputs accept voltages up to. V Low noise overshoot and undershoot < 0 % of V I OFF circuitry provides partial power-down mode operation Multiple package options Specified from 40 to+8 and 40 to+

3 . Ordering information Table. Type number 4. Marking Ordering information Package Temperature range Name Description Version GW 40 to + S-88 plastic surface-mounted package; leads SOT GM 40 to + XSON plastic extremely thin small outline package; no leads; terminals; body.4 0. mm GF 40 to + XSON plastic extremely thin small outline package; no leads; terminals; body 0. mm GN 40 to + XSON extremely thin small outline package; no leads; terminals; body mm GS 40 to + XSON extremely thin small outline package; no leads; terminals; body mm SOT88 SOT89 SOT SOT0 Table. Marking Type number GW GM GF GN GS Marking code ar ar ar ar ar. Functional diagram 4 00aad987 Fig. Logic symbol ll information provided in this document is subject to legal disclaimers. NXP.V. 0. ll rights reserved. Product data sheet Rev. 4 august 0 of 0

4 . Pinning information. Pinning GND V GND 4 V 4 00aah840 GND V 4 00aah84 00aah89 Transparent top view Transparent top view Fig. Pin configuration SOT Fig. Pin configuration SOT88 Fig 4. Pin configuration SOT89, SOT and SOT0. Pin description Table. Pin description Symbol Pin Description data input GND ground (0 V) data input 4 data output V supply voltage data input 7. Functional description Table 4. Function table [] Input Output L L L H L L H H L H L L L H H L H L L H H L H L H H L H H H H L [] H = HIGH voltage level; L = LOW voltage level. ll information provided in this document is subject to legal disclaimers. NXP.V. 0. ll rights reserved. Product data sheet Rev. 4 august 0 of 0

5 7. Logic configurations Table. Function selection table Logic function Figure -input MUX (inverting) see Figure -input NND see Figure -input NOR with one input inverted see Figure 7 -input ND with one input inverted see Figure 7 -input NND with one input inverted see Figure 8 -input OR with one input inverted see Figure 8 -input NOR see Figure 9 uffer see Figure 0 Inverter see Figure V V aad99 00aad99 Fig. -input MUX (inverting) Fig. -input NND gate V V aad99 00aad994 Fig 7. -input ND gate with input inverted or -input NOR gate with input inverted Fig 8. -input OR gate with input inverted or -input NND gate with input inverted V V aad99 00aad99 Fig 9. -input NOR gate Fig 0. uffer ll information provided in this document is subject to legal disclaimers. NXP.V. 0. ll rights reserved. Product data sheet Rev. 4 august 0 4 of 0

6 V 4 00aad997 Fig. Inverter 8. Limiting values Table. Limiting values In accordance with the bsolute Maximum Rating System (IE 04). Voltages are referenced to GND (ground = 0 V). Symbol Parameter onditions Min Max Unit V supply voltage V I IK input clamping current V I <0V 0 - m V I input voltage [] V I OK output clamping current V O <0V 0 - m V O output voltage ctive mode and Power-down mode [] V I O output current V O =0 VtoV - 0 m I supply current - +0 m I GND ground current 0 - m T stg storage temperature +0 P tot total power dissipation T amb = 40 to + [] - 0 mw [] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. [] For S-88 package: above 87. the value of P tot derates linearly with 4.0 mw/k. For XSON packages: above 8 the value of P tot derates linearly with 7.8 mw/k. 9. Recommended operating conditions Table 7. Recommended operating conditions Symbol Parameter onditions Min Max Unit V supply voltage.. V V I input voltage 0. V V O output voltage ctive mode 0 V V Power-down mode; V =0V 0. V T amb ambient temperature 40 + ll information provided in this document is subject to legal disclaimers. NXP.V. 0. ll rights reserved. Product data sheet Rev. 4 august 0 of 0

7 0. Static characteristics Table 8. Static characteristics t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter onditions Min Typ Max Unit T amb = V T+ positive-going threshold V =. V to.7 V V voltage V =.0 V to. V V V T negative-going threshold V =. V to.7 V V voltage V =.0 V to. V V V H hysteresis voltage (V H = V T+ V T ) V =. V to.7 V V V =.0 V to. V V V OH HIGH-level output voltage V I = V T+ or V T I O = 0 ; V =. V to. V V V I O =. m; V =. V V I O =. m; V =. V V I O =.7 m; V =.0 V V I O = 4.0 m; V =.0 V. - - V V OL LOW-level output voltage V I = V T+ or V T I O = 0 ; V =. V to. V V I O =. m; V =. V V I O =. m; V =. V V I O =.7 m; V =.0 V V I O = 4.0 m; V =.0 V V I I input leakage current V I = GND to. V; V = 0 V to. V I OFF power-off leakage current V I or V O = 0 V to. V; V = 0 V I OFF additional power-off V I or V O = 0 V to. V; leakage current V =0Vto0.V I supply current V I = GND or V ; I O = 0 ; - -. V =. V to. V I input capacitance V = 0 V to. V; V I = GND or V pf O output capacitance V O = GND; V = 0 V pf T amb = 40 to +8 V T+ positive-going threshold V =. V to.7 V V voltage V =.0 V to. V V V T negative-going threshold V =. V to.7 V V voltage V =.0 V to. V V V H hysteresis voltage (V H = V T+ V T ) V =. V to.7 V V V =.0 V to. V V ll information provided in this document is subject to legal disclaimers. NXP.V. 0. ll rights reserved. Product data sheet Rev. 4 august 0 of 0

8 Table 8. Static characteristics continued t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter onditions Min Typ Max Unit V OH HIGH-level output voltage V I = V T+ or V T V OL LOW-level output voltage V I = V T+ or V T I O = 0 ; V =. V to. V V V I O =. m; V =. V V I O =. m; V =. V V I O =.7 m; V =.0 V V I O = 4.0 m; V =.0 V. - - V I O = 0 ; V =. V to. V V I O =. m; V =. V V I O =. m; V =. V V I O =.7 m; V =.0 V V I O = 4.0 m; V =.0 V V I I input leakage current V I = GND to. V; V = 0 V to. V I OFF power-off leakage current V I or V O = 0 V to. V; V = 0 V I OFF additional power-off V I or V O = 0 V to. V; leakage current V =0Vto0.V I supply current V I = GND or V ; I O = 0 ; - -. V =. V to. V I additional supply current V =. V to.7 V; I O = 0 [] V =.0 V to. V; I O = 0 [] - - T amb = 40 to + V T+ positive-going threshold V =. V to.7 V V voltage V =.0 V to. V V V T negative-going threshold V =. V to.7 V V voltage V =.0 V to. V V V H hysteresis voltage (V H = V T+ V T ) V =. V to.7 V V V =.0 V to. V V V OH HIGH-level output voltage V I = V T+ or V T I O = 0 ; V =. V to. V V V I O =. m; V =. V V I O =. m; V =. V V I O =.7 m; V =.0 V V I O = 4.0 m; V =.0 V V V OL LOW-level output voltage V I = V T+ or V T I O = 0 ; V =. V to. V V I O =. m; V =. V V I O =. m; V =. V V I O =.7 m; V =.0 V V I O = 4.0 m; V =.0 V V I I input leakage current V I = GND to. V; V = 0 V to. V ll information provided in this document is subject to legal disclaimers. NXP.V. 0. ll rights reserved. Product data sheet Rev. 4 august 0 7 of 0

9 Table 8. Static characteristics continued t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter onditions Min Typ Max Unit I OFF power-off leakage current V I or V O = 0 V to. V; V = 0 V I OFF additional power-off V I or V O = 0 V to. V; leakage current V =0Vto0.V I supply current V I = GND or V ; I O = 0 ; - -. V =. V to. V I additional supply current V =. V to.7 V; I O = 0 [] V =.0 V to. V; I O = 0 [] - - [] One input at 0. V or. V, other input at V or GND. [] One input at 0.4 V or. V, other input at V or GND.. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure. Symbol Parameter onditions 40 to + Unit Min Typ [] Max Min Max (8 ) Max ( ) V =. V to.7 V; V I =. V to.9 V t pd propagation delay,, to ; see Figure [] L = pf ns L = 0 pf ns L = pf ns L = 0 pf ns V =. V to.7 V; V I =. V to.7 V t pd propagation delay,, to ; see Figure [] L = pf ns L = 0 pf ns L = pf ns L = 0 pf ns V =. V to.7 V; V I =.0 V to. V t pd propagation delay,, to ; see Figure [] L = pf ns L = 0 pf ns L = pf ns L = 0 pf ns V =.0 V to. V; V I =. V to.9 V t pd propagation delay,, to ; see Figure [] L = pf ns L = 0 pf ns L = pf ns L = 0 pf ns ll information provided in this document is subject to legal disclaimers. NXP.V. 0. ll rights reserved. Product data sheet Rev. 4 august 0 8 of 0

10 Table 9. Dynamic characteristics continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure. Symbol Parameter onditions 40 to + Unit V =.0 V to. V; V I =. V to.7 V t pd propagation delay,, to ; see Figure [] L = pf ns L = 0 pf ns L = pf ns L = 0 pf ns V =.0 V to. V; V I =.0 V to. V t pd propagation delay,, to ; see Figure [] L = pf ns L = 0 pf ns L = pf ns L = 0 pf ns T amb = PD power dissipation f i = MHz; V I = GND to V [] capacitance V =. V to.7 V pf V =.0 V to. V pf [] ll typical values are measured at nominal V. [] t pd is the same as t PLH and t PHL [] PD is used to determine the dynamic power dissipation (P D in W). P D = PD V f i N+ ( L V f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; L = output load capacitance in pf; V = supply voltage in V; N = number of inputs switching; ( L V f o ) = sum of the outputs. Min Typ [] Max Min Max (8 ) Max ( ) ll information provided in this document is subject to legal disclaimers. NXP.V. 0. ll rights reserved. Product data sheet Rev. 4 august 0 9 of 0

11 . Waveforms V I,, input V M V M GND t PHL t PLH V OH output V M V M V OL t PLH t PHL V OH output V M V M V OL 00aab9 Fig. Measurement points are given in Table 0. V OL and V OH are typical output voltage levels that occur with the output load. Input, and to output propagation delay times Table 0. Measurement points Supply voltage Output Input V V M V M V I t r = t f. V to. V 0. V 0. V I. V to. V.0 ns ll information provided in this document is subject to legal disclaimers. NXP.V. 0. ll rights reserved. Product data sheet Rev. 4 august 0 0 of 0

12 V V EXT G VI DUT VO kω RT L RL 00aac Fig. Test data is given in Table. Definitions for test circuit: R L = Load resistance. L = Load capacitance including jig and probe capacitance. R T = Termination resistance should be equal to the output impedance Z o of the pulse generator. V EXT = External voltage for measuring switching times. Test circuit for measuring switching times Table. Test data Supply voltage Load V EXT V L R [] L t PLH, t PHL t PZH, t PHZ t PZL, t PLZ. V to. V pf, 0 pf, pf and 0 pf k or M open GND V [] For measuring enable and disable times R L = k, for measuring propagation delays, setup and hold times and pulse width R L = M. ll information provided in this document is subject to legal disclaimers. NXP.V. 0. ll rights reserved. Product data sheet Rev. 4 august 0 of 0

13 . Package outline Plastic surface-mounted package; leads SOT D E X y H E v M 4 Q pin index c e b p w M L p e detail X 0 mm scale DIMENSIONS (mm are the original dimensions) UNIT bp c D E e e max H E Lp Q v w y mm OUTLINE VERSION REFERENES IE JEDE JEIT EUROPEN PROJETION ISSUE DTE SOT S Fig 4. Package outline SOT (S-88) ll information provided in this document is subject to legal disclaimers. NXP.V. 0. ll rights reserved. Product data sheet Rev. 4 august 0 of 0

14 XSON: plastic extremely thin small outline package; no leads; terminals; body x.4 x 0. mm SOT88 b L L 4x () e 4 e e x () D E terminal index area Dimensions (mm are the original dimensions) 0 mm scale Unit () b D E e e L L mm max nom min Outline version SOT Notes. Including plating thickness.. an be visible in some manufacturing processes. 0. References IE JEDE JEIT MO European projection Issue date sot88_po Fig. Package outline SOT88 (XSON) ll information provided in this document is subject to legal disclaimers. NXP.V. 0. ll rights reserved. Product data sheet Rev. 4 august 0 of 0

15 XSON: plastic extremely thin small outline package; no leads; terminals; body x x 0. mm SOT89 b L L 4 () e 4 e e () D E terminal index area DIMENSIONS (mm are the original dimensions) 0 mm scale UNIT mm max max b D E e e L Note. an be visible in some manufacturing processes L OUTLINE VERSION REFERENES IE JEDE JEIT EUROPEN PROJETION ISSUE DTE SOT Fig. Package outline SOT89 (XSON) ll information provided in this document is subject to legal disclaimers. NXP.V. 0. ll rights reserved. Product data sheet Rev. 4 august 0 4 of 0

16 XSON: extremely thin small outline package; no leads; terminals; body 0.9 x.0 x 0. mm SOT b (4 ) () L L e 4 e e ( ) () D E terminal index area Dimensions 0 0. mm scale Unit () b D E e e L L mm max nom min Outline version SOT Note. Including plating thickness.. Visible depending upon used manufacturing technology References IE JEDE JEIT European projection Issue date sot_po Fig 7. Package outline SOT (XSON) ll information provided in this document is subject to legal disclaimers. NXP.V. 0. ll rights reserved. Product data sheet Rev. 4 august 0 of 0

17 XSON: extremely thin small outline package; no leads; terminals; body.0 x.0 x 0. mm SOT0 b (4 ) () L L e 4 e e ( ) () D terminal index area E Dimensions 0 0. mm scale Unit () b D E e e L L mm max nom min Outline version SOT Note. Including plating thickness.. Visible depending upon used manufacturing technology References IE JEDE JEIT European projection Issue date sot0_po Fig 8. Package outline SOT0 (XSON) ll information provided in this document is subject to legal disclaimers. NXP.V. 0. ll rights reserved. Product data sheet Rev. 4 august 0 of 0

18 4. bbreviations Table. cronym DM MOS DUT ESD HM MM bbreviations Description harged Device Model omplementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human ody Model Machine Model. Revision history Table. Revision history Document ID Release date Data sheet status hange notice Supersedes v Product data sheet - v. Modifications: Package outline drawing of SOT88 (Figure ) modified. v. 00 Product data sheet - v. v Product data sheet - v. v Product data sheet - - ll information provided in this document is subject to legal disclaimers. NXP.V. 0. ll rights reserved. Product data sheet Rev. 4 august 0 7 of 0

19 . Legal information. Data sheet status Document status [][] Product status [] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [] Please consult the most recently issued document before initiating or completing a design. [] The term short data sheet is explained in section Definitions. [] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.. Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. ustomers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). ustomers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). ustomer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). NXP does not accept any liability in this respect. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IE 04) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the haracteristics sections of this document is not warranted. onstant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. ll information provided in this document is subject to legal disclaimers. NXP.V. 0. ll rights reserved. Product data sheet Rev. 4 august 0 8 of 0

20 Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors specifications such use shall be solely at customer s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors standard warranty and NXP Semiconductors product specifications. Translations non-english (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions..4 Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. 7. ontact information For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com ll information provided in this document is subject to legal disclaimers. NXP.V. 0. ll rights reserved. Product data sheet Rev. 4 august 0 9 of 0

21 8. ontents General description Features and benefits Ordering information Marking Functional diagram Pinning information Pinning Pin description Functional description Logic configurations Limiting values Recommended operating conditions Static characteristics Dynamic characteristics Waveforms Package outline bbreviations Revision history Legal information Data sheet status Definitions Disclaimers Trademarks ontact information ontents Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP.V. 0. ll rights reserved. For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com Date of release: august 0 Document identifier:

Low-power configurable gate with voltage-level translator

Low-power configurable gate with voltage-level translator Rev. 5 15 ugust 2012 Product data sheet 1. General description The provides low-power, low-voltage configurable logic gate functions. The output state is determined by eight patterns of 3-bit input. The

More information

Low-power 3-input EXCLUSIVE-OR gate. The 74AUP1G386 provides a single 3-input EXCLUSIVE-OR gate.

Low-power 3-input EXCLUSIVE-OR gate. The 74AUP1G386 provides a single 3-input EXCLUSIVE-OR gate. Rev. 6 31 July 2012 Product data sheet 1. General description The provides a single 3-input EXCLUSIVE-OR gate. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall

More information

Low-power configurable multiple function gate

Low-power configurable multiple function gate Rev. 8 23 September 2015 Product data sheet 1. General description The provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the

More information

Low-power buffer and inverter. The 74AUP2G3404 is a single buffer and single inverter.

Low-power buffer and inverter. The 74AUP2G3404 is a single buffer and single inverter. Rev. 1 22 August 2012 Product data sheet 1. General description The is a single buffer and single inverter. Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall

More information

The 74AXP1G04 is a single inverting buffer.

The 74AXP1G04 is a single inverting buffer. Rev. 1 25 August 2014 Product data sheet 1. General description The is a single inverting buffer. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This

More information

Low-power configurable multiple function gate

Low-power configurable multiple function gate Rev. 2 16 September 2015 Product data sheet 1. General description The is a configurable multiple function gate with Schmitt-trigger inputs. The device can be configured as any of the following logic functions

More information

Low-power dual Schmitt trigger inverter

Low-power dual Schmitt trigger inverter Rev. 1 9 October 2014 Product data sheet 1. General description The is a dual inverter with Schmitt-trigger inputs. It transforms slowly changing input signals into sharply defined, jitter-free output

More information

The 74AUP2G34 provides two low-power, low-voltage buffers.

The 74AUP2G34 provides two low-power, low-voltage buffers. Rev. 6 17 September 2015 Product data sheet 1. General description The provides two low-power, low-voltage buffers. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise

More information

The 74LVC1G11 provides a single 3-input AND gate.

The 74LVC1G11 provides a single 3-input AND gate. Rev. 7 4 July 2012 Product data sheet 1. General description The provides a single -input ND gate. The input can be driven from either. V or 5 V devices. This feature allows the use of this device in a

More information

Low-power 3-input AND gate. The 74AUP1G11 provides a low-power, low-voltage single 3-input AND gate.

Low-power 3-input AND gate. The 74AUP1G11 provides a low-power, low-voltage single 3-input AND gate. Rev. 4 3 ugust 2012 Product data sheet 1. General description The provides a low-power, low-voltage single 3-input ND gate. Schmitt trigger action at all inputs makes the circuit tolerant to slower input

More information

74HC2G16; 74HCT2G16. The 74HC2G16; 74HCT2G16 is a high-speed Si-gate CMOS device. The 74HC2G16; 74HCT2G16 provides two buffers.

74HC2G16; 74HCT2G16. The 74HC2G16; 74HCT2G16 is a high-speed Si-gate CMOS device. The 74HC2G16; 74HCT2G16 provides two buffers. Rev. 1 2 November 2015 Product data sheet 1. General description The is a high-speed Si-gate CMOS device. The provides two buffers. 2. Features and benefits 3. Ordering information Wide supply voltage

More information

Low-power buffer with voltage-level translator

Low-power buffer with voltage-level translator Rev. 1 28 November 2017 Product data sheet 1 General description 2 Features and benefits The provides the single buffer function. This device ensures a very low static and dynamic power consumption across

More information

74AUP1G04-Q100. The 74AUP1G04-Q100 provides the single inverting buffer.

74AUP1G04-Q100. The 74AUP1G04-Q100 provides the single inverting buffer. Rev. 1 18 November 2013 Product data sheet 1. General description The provides the single inverting buffer. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

More information

Low-power 2-input NAND gate. The 74AUP1G00 provides the single 2-input NAND function.

Low-power 2-input NAND gate. The 74AUP1G00 provides the single 2-input NAND function. Rev. 6 27 June 2012 Product data sheet 1. General description The provides the single 2-input NND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

More information

Temperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.

Temperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1. Rev. 01 3 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input OR function. Symmetrical output impedance

More information

2-input EXCLUSIVE-OR gate

2-input EXCLUSIVE-OR gate Rev. 01 7 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input EXCLUSIVE-OR function. Symmetrical output

More information

The 74LVC1G11 provides a single 3-input AND gate.

The 74LVC1G11 provides a single 3-input AND gate. Rev. 0 September 200 Product data sheet 1. General description 2. Features The is a high-performance, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The input

More information

XC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger

XC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger Rev. 01 31 ugust 2009 Product data sheet 1. General description 2. Features 3. pplications is a high-speed Si-gate CMOS device. It provides an inverting buffer function with Schmitt trigger action. This

More information

The 74LVC1G02 provides the single 2-input NOR function.

The 74LVC1G02 provides the single 2-input NOR function. Rev. 07 18 July 2007 Product data sheet 1. General description 2. Features The provides the single 2-input NOR function. Input can be driven from either 3.3 V or 5 V devices. These features allow the use

More information

Low-power 2-input NAND Schmitt trigger

Low-power 2-input NAND Schmitt trigger Rev. 5 29 June 2012 Product data sheet 1. General description The provides the single 2-input NND Schmitt trigger function which accept standard input signals. They are capable of transforming slowly changing

More information

2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device.

2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device. 74HC1G09 Rev. 02 18 December 2007 Product data sheet 1. General description 2. Features 3. Ordering information The 74HC1G09 is a high-speed Si-gate CMOS device. The 74HC1G09 provides the 2-input ND function

More information

Low-power triple buffer with open-drain output

Low-power triple buffer with open-drain output Rev. 2 5 October 2016 Product data sheet 1. General description The is a triple non-inverting buffer with open-drain output. The output of the device is an open drain and can be connected to other open-drain

More information

Low-power Schmitt trigger inverter

Low-power Schmitt trigger inverter Rev. 1 28 August 2014 Product data sheet 1. General description The is a single inverter with Schmitt trigger input. It transforms slowly changing input signals into sharply defined, jitter-free output

More information

Low-power buffer/line driver; 3-state

Low-power buffer/line driver; 3-state Rev. 6 15 ugust 2012 Product data sheet 1. General description The provides a single non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE).

More information

Dual supply configurable multiple function gate

Dual supply configurable multiple function gate Rev. July 0 Product data sheet General description Features and benefits The is a dual supply configurable multiple function gate with Schmitt-trigger inputs. It features three inputs (, and ), an output

More information

Single Schmitt trigger buffer

Single Schmitt trigger buffer Rev. 10 29 June 2012 Product data sheet 1. General description The provides a buffer function with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined

More information

Low-power 2-input AND gate with open-drain

Low-power 2-input AND gate with open-drain Rev. 5 29 September 2017 Product data sheet 1 General description 2 Features and benefits The provides the single 2-input ND gate with an open-drain output. The output of the device is an open-drain and

More information

Low-power dual supply translating buffer

Low-power dual supply translating buffer Rev. 5 4 September 2013 Product data sheet 1. General description The provides a single buffer with two separate supply voltages. Input is designed to track V CC(). Output Y is designed to track V CC(Y).

More information

Dual supply buffer/line driver; 3-state

Dual supply buffer/line driver; 3-state Rev. 1 21 December 2015 Product data sheet 1. General description The is a dual supply non-inverting buffer/line driver with 3-state output. It features one input (A), an output (Y), an output enable input

More information

Single D-type flip-flop; positive-edge trigger. The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop.

Single D-type flip-flop; positive-edge trigger. The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop. Rev. 12 5 December 2016 Product data sheet 1. General description The provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q-output on the LOW-to-HIGH

More information

74HC2G34; 74HCT2G34. The 74HC2G34; 74HCT2G34 is a high-speed Si-gate CMOS device. The 74HC2G34; 74HCT2G34 provides two buffers.

74HC2G34; 74HCT2G34. The 74HC2G34; 74HCT2G34 is a high-speed Si-gate CMOS device. The 74HC2G34; 74HCT2G34 provides two buffers. Rev. 01 6 October 2006 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The provides two buffers. Wide supply voltage range from 2.0

More information

Low-power dual PCB configurable multiple function gate

Low-power dual PCB configurable multiple function gate Rev. 2 2 December 2015 Product data sheet 1. General description The is a dual configurable multiple function gate with Schmitt-trigger inputs. Each gate within the device can be configured as any of the

More information

Bus buffer/line driver; 3-state

Bus buffer/line driver; 3-state Rev. 12 2 December 2016 Product data sheet 1. General description The provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE).

More information

Dual buffer/line driver; 3-state

Dual buffer/line driver; 3-state Rev. 2 8 May 2013 Product data sheet 1. General description The is a high-speed Si-gate CMOS devices. This device provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output

More information

Dual buffer/line driver; 3-state

Dual buffer/line driver; 3-state Rev. 2 8 May 2013 Product data sheet 1. General description The is a high-speed Si-gate CMOS devices. This device provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output

More information

The 74LV08 provides a quad 2-input AND function.

The 74LV08 provides a quad 2-input AND function. Rev. 4 8 December 2015 Product data sheet 1. General description The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC08 and 74HCT08. The provides a quad 2-input AND function.

More information

Dual supply configurable multiple function gate

Dual supply configurable multiple function gate Rev. 4 28 October 2016 Product data sheet 1. General description The is a dual supply configurable multiple function gate with Schmitt-trigger inputs. It features three inputs (A, B and C), an output (Y)

More information

2-input single supply translating NAND gate

2-input single supply translating NAND gate Rev. 1 22 November 2017 Product data sheet 1 General description 2 Features and benefits 3 pplications The is a single, level translating 2-input NND gate. The low threshold inputs support 1.8 V input

More information

Low-power inverter with open-drain output

Low-power inverter with open-drain output Rev. 8 12 February 2018 Product data sheet 1 General description 2 Features and benefits The provides the single inverting buffer with open-drain output. The output of the device is an open drain and can

More information

74LVC1G18 1-of-2 non-inverting demultiplexer with 3-state deselected output Rev. 3 2 December 2016 Product data sheet 1. General description

74LVC1G18 1-of-2 non-inverting demultiplexer with 3-state deselected output Rev. 3 2 December 2016 Product data sheet 1. General description 1-of-2 non-inverting demultiplexer with 3-state deselected output Rev. 3 2 December 2016 Product data sheet 1. General description The is a 1-of-2 non-inverting demultiplexer with a 3-state output. The

More information

Low-power inverter with open-drain output

Low-power inverter with open-drain output Rev. 7 28 June 2012 Product data sheet 1. General description The provides the single inverting buffer with open-drain output. The output of the device is an open drain and can be connected to other open-drain

More information

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate Rev. 7 2 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. Inputs include clamp diodes. This enables the use of current limiting resistors

More information

Low-power unbuffered inverter. The 74AUP1GU04 provides the single unbuffered inverting gate.

Low-power unbuffered inverter. The 74AUP1GU04 provides the single unbuffered inverting gate. Rev. 5 29 June 2012 Product data sheet 1. General description The provides the single unbuffered inverting gate. This device ensures a very low static and dynamic power consumption across the entire V

More information

74LVC1G General description. 2 Features and benefits. Single 2-input multiplexer

74LVC1G General description. 2 Features and benefits. Single 2-input multiplexer Rev. 8 31 October 2017 Product data sheet 1 General description 2 Features and benefits The is a single 2-input multiplexer which select data from two data inputs (I0 and I1) under control of a common

More information

74AUP1G04. 1 General description. 2 Features and benefits. Low-power inverter

74AUP1G04. 1 General description. 2 Features and benefits. Low-power inverter Rev. 9 8 June 2018 Product data sheet 1 General description 2 Features and benefits The provides the single inverting buffer. Schmitt trigger action at all inputs makes the circuit tolerant to slower input

More information

74LVC1G79-Q100. Single D-type flip-flop; positive-edge trigger. The 74LVC1G79_Q100 provides a single positive-edge triggered D-type flip-flop.

74LVC1G79-Q100. Single D-type flip-flop; positive-edge trigger. The 74LVC1G79_Q100 provides a single positive-edge triggered D-type flip-flop. Rev. 2 12 December 2016 Product data sheet 1. General description The provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q-output on the LOW-to-HIGH

More information

Single dual-supply translating 2-input OR with strobe

Single dual-supply translating 2-input OR with strobe Rev. 1 10 October 2018 Product data sheet 1. General description The is a single dual-supply translating 2-input OR with strobe inputs. It features two data input pins (A, B), two strobe input pins (STRA,

More information

4-bit magnitude comparator

4-bit magnitude comparator Rev. 6 21 November 2011 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a that compares two 4-bit words, A and B, and determines whether A is greater than

More information

Triple inverting Schmitt trigger

Triple inverting Schmitt trigger Rev. 5 7 February 2013 Product data sheet 1. General description The is a high-speed Si-gate CMOS device. This device provides three inverting buffers with Schmitt trigger action. This device is capable

More information

74HC4050-Q100. Hex non-inverting HIGH-to-LOW level shifter

74HC4050-Q100. Hex non-inverting HIGH-to-LOW level shifter Rev. 1 30 January 2013 Product data sheet 1. General description The is a hex buffer with over-voltage tolerant inputs. Inputs are overvoltage tolerant to 15 V which enables the device to be used in HIGH-to-LOW

More information

Single supply translating buffer/line driver; 3-state

Single supply translating buffer/line driver; 3-state Rev. 1 22 November 2017 Product data sheet 1 General description 2 Features and benefits 3 pplications The is a single, level translating buffer/line driver with 3-state output. The low threshold inputs

More information

74LVC1G125-Q100. Bus buffer/line driver; 3-state

74LVC1G125-Q100. Bus buffer/line driver; 3-state Rev. 2 8 December 2016 Product data sheet 1. General description The provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE).

More information

Temperature range Name Description Version 74AUP1G17GW -40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.

Temperature range Name Description Version 74AUP1G17GW -40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1. Rev. 11 8 June 2018 Product data sheet 1 General description 2 Features and benefits 3 Ordering information Table 1. Ordering information Type number The provides the single Schmitt trigger buffer. It

More information

Low-power dual 2-input NAND gate; open drain

Low-power dual 2-input NAND gate; open drain Rev. 8 11 February 2013 Product data sheet 1. General description The provides the dual 2-input NND gate with open-drain output. The output of the device is an open drain and can be connected to other

More information

Triple inverting Schmitt trigger with 5 V tolerant input

Triple inverting Schmitt trigger with 5 V tolerant input Rev. 14 15 December 2016 Product data sheet 1. General description The provides three inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply

More information

74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate

74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate Rev. 5 8 October 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual 2-input ND gate. Inputs include clamp diodes. This enables the use of current

More information

The 74LVC2G32 provides a 2-input OR gate function.

The 74LVC2G32 provides a 2-input OR gate function. Rev. 11 8 pril 2013 Product data sheet 1. General description The provides a 2-input OR gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices

More information

Dual inverting Schmitt trigger with 5 V tolerant input

Dual inverting Schmitt trigger with 5 V tolerant input Rev. 10 15 December 2016 Product data sheet 1. General description The provides two inverting buffers with Schmitt-trigger input. It is capable of transforming slowly changing input signals into sharply

More information

Temperature range Name Description Version 74LVC1G17GW -40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.

Temperature range Name Description Version 74LVC1G17GW -40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1. Rev. 12 8 June 2018 Product data sheet 1 General description 2 Features and benefits 3 Ordering information Table 1. Ordering information Type number The provides a buffer function with Schmitt trigger

More information

74HC2G08-Q100; 74HCT2G08-Q100

74HC2G08-Q100; 74HCT2G08-Q100 Rev. 1 11 November 2013 Product data sheet 1. General description The is a dual 2-input ND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to s in

More information

74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate

74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate Rev. 5 8 October 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual 2-input ND gate. Inputs include clamp diodes. This enables the use of current

More information

74LVC1G04. 1 General description. 2 Features and benefits. Single inverter

74LVC1G04. 1 General description. 2 Features and benefits. Single inverter Rev. 15 8 June 2018 Product data sheet 1 General description 2 Features and benefits The provides one inverting buffer. Input can be driven from either 3.3 V or 5 V devices. These features allow the use

More information

7-stage binary ripple counter

7-stage binary ripple counter Rev. 9 28 April 2016 Product data sheet 1. General description The is a with a clock input (CP), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6).

More information

Dual buffer/line driver; 3-state

Dual buffer/line driver; 3-state Rev. 14 15 December 2016 Product data sheet 1. General description The is a dual non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE

More information

74HC1G32-Q100; 74HCT1G32-Q100

74HC1G32-Q100; 74HCT1G32-Q100 Rev. 1 8 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information 74HC1G32-Q100 and 74HCT1G32-Q100 are high-speed Si-gate CMOS devices. They provide a 2-input

More information

74HC1G86; 74HCT1G86. 2-input EXCLUSIVE-OR gate. The standard output currents are half those of the 74HC/HCT86.

74HC1G86; 74HCT1G86. 2-input EXCLUSIVE-OR gate. The standard output currents are half those of the 74HC/HCT86. Rev. 04 20 July 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G86 and 74HCT1G86 are high-speed Si-gate CMOS devices. They provide a 2-input EXCLUSIVE-OR function.

More information

Octal bus transceiver; 3-state

Octal bus transceiver; 3-state Rev. 2 3 November 2016 Product data sheet 1. General description The is an 8-bit transceiver with 3-state outputs. The device features an output enable (OE) and send/receive (DIR) for direction control.

More information

74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02.

74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02. Rev. 04 11 July 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G02 and 74HCT1G02 are high speed Si-gate CMOS devices. They provide a 2-input NOR function. The HC

More information

Low-power buffer/line driver; 3-state

Low-power buffer/line driver; 3-state Rev. 7 16 May 2018 Product data sheet 1 General description 2 Features and benefits The provides a single non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output

More information

74HC30-Q100; 74HCT30-Q100

74HC30-Q100; 74HCT30-Q100 Rev. 1 30 January 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. Inputs include clamp diodes. This enables the use of current limiting resistors

More information

74LVC1G General description. 2. Features and benefits. Single D-type flip-flop with set and reset; positive edge trigger

74LVC1G General description. 2. Features and benefits. Single D-type flip-flop with set and reset; positive edge trigger Rev. 13 5 December 2016 Product data sheet 1. General description The is a single positive edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs,

More information

Dual bus buffer/line driver; 3-state

Dual bus buffer/line driver; 3-state Rev. 12 8 pril 2013 Product data sheet 1. General description The is a dual non-inverting buffer/line driver with 3-state outputs. Each 3-state output is controlled by an output enable input (pin noe).

More information

74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function.

74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function. Rev. 0 30 June 2009 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They

More information

74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter

74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter Rev. 5 1 July 27 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. It provides an inverting single stage function. The standard output

More information

74LVC General description. 2. Features and benefits. Ordering information. Octal D-type flip-flop with data enable; positive-edge trigger

74LVC General description. 2. Features and benefits. Ordering information. Octal D-type flip-flop with data enable; positive-edge trigger Rev. 6 20 November 2012 Product data sheet 1. General description The has eight edge-triggered D-type flip-flops with individual inputs (D) and outputs (Q). common clock input (CP) loads all flip-flops

More information

74HC1G02-Q100; 74HCT1G02-Q100

74HC1G02-Q100; 74HCT1G02-Q100 Rev. 1 7 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information 74HC1G02-Q100 and 74HCT1G02-Q100 are high speed Si-gate CMOS devices. They provide a 2-input

More information

74AHC2G241; 74AHCT2G241

74AHC2G241; 74AHCT2G241 Rev. 3 13 May 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a high-speed Si-gate CMOS device. The is a dual non-inverting buffer/line driver with

More information

74HC153-Q100; 74HCT153-Q100

74HC153-Q100; 74HCT153-Q100 Rev. 3 23 January 2014 Product data sheet 1. General description The is a dual 4-input multiplexer. The device features independent enable inputs (ne) and common data select inputs (S0 and S1). For each

More information

Buffer with open-drain output

Buffer with open-drain output Rev. 14 8 June 2018 Product data sheet 1 General description 2 Features and benefits The provides the non-inverting buffer. The output of this device is an open drain and can be connected to other open-drain

More information

74HC1G08; 74HCT1G08. 1 General description. 2 Features. 3 Ordering information. 2-input AND gate

74HC1G08; 74HCT1G08. 1 General description. 2 Features. 3 Ordering information. 2-input AND gate Rev. 5 14 March 2018 Product data sheet 1 General description 2 Features 3 Ordering information Table 1. Ordering information Type number 74HC1G08GW 74HCT1G08GW 74HC1G08GV 74HCT1G08GV The is a single.

More information

74AHC1G125; 74AHCT1G125

74AHC1G125; 74AHCT1G125 Rev. 10 23 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information 74HC1G125 and 74HCT1G125 are high-speed Si-gate CMOS devices. They provide one non-inverting

More information

74AHC1G00; 74AHCT1G00

74AHC1G00; 74AHCT1G00 74HC1G00; 74HCT1G00 Rev. 06 30 May 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G00 and 74HCT1G00 are high-speed Si-gate CMOS devices. They provide a 2-input

More information

Octal buffer/line driver; 3-state

Octal buffer/line driver; 3-state Rev. 4 1 March 2016 Product data sheet 1. General description The is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC244 and 74HCT244. The is an octal non-inverting buffer/line

More information

Inverter with open-drain output

Inverter with open-drain output Rev. 12 22 May 2018 Product data sheet 1 General description 2 Features and benefits The provides the inverting buffer. Input can be driven from either 3.3 V or 5 V devices. These features allow the use

More information

74LVC1G17-Q100. Single Schmitt trigger buffer

74LVC1G17-Q100. Single Schmitt trigger buffer Rev. 3 28 January 2019 Product data sheet 1. General description 2. Features and benefits 3. Ordering information Table 1. Ordering information Type number Package The provides a buffer function with Schmitt

More information

Dual inverting Schmitt trigger with 5 V tolerant input

Dual inverting Schmitt trigger with 5 V tolerant input Rev. 11 10 ugust 2018 Product data sheet 1. General description 2. Features and benefits 3. pplications The provides two inverting buffers with Schmitt-trigger input. It is capable of transforming slowly

More information

74AVC General description. 2 Features and benefits. 1-to-4 fan-out buffer

74AVC General description. 2 Features and benefits. 1-to-4 fan-out buffer Rev. 1 23 April 2018 Product data sheet 1 General description 2 Features and benefits The is a suitable for use in clock distribution. It has a data input (A), four data outputs (Yn) and an output enable

More information

74AHC1G126; 74AHCT1G126

74AHC1G126; 74AHCT1G126 Rev. 8 23 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information 74HC1G126 and 74HCT1G126 are high-speed Si-gate CMOS devices. They provide one non-inverting

More information

74AUP1G34. 1 General description. 2 Features and benefits. Low-power buffer

74AUP1G34. 1 General description. 2 Features and benefits. Low-power buffer 74UP1G34 Rev. 8 8 June 2018 Product data sheet 1 General description 2 Features and benefits The 74UP1G34 provides a low-power, low-voltage single buffer. Schmitt trigger action at all inputs makes the

More information

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic

More information

74HC1G14; 74HCT1G14. The standard output currents are half of those of the 74HC14 and 74HCT14.

74HC1G14; 74HCT1G14. The standard output currents are half of those of the 74HC14 and 74HCT14. Rev. 6 27 December 212 Product data sheet 1. General description 2. Features and benefits 3. pplications 74HC1G14 and 74HCT1G14 are high-speed Si-gate CMOS devices. They provide an inverting buffer function

More information

74HC132-Q100; 74HCT132-Q100

74HC132-Q100; 74HCT132-Q100 Rev. 3 1 December 2015 Product data sheet 1. General description The is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors

More information

74HC366; 74HCT366. Hex buffer/line driver; 3-state; inverting

74HC366; 74HCT366. Hex buffer/line driver; 3-state; inverting Rev. 5 2 February 2016 Product data sheet 1. General description The is a hex inverting buffer/line driver with 3-state outputs controlled by the output enable inputs (OEn). A HIGH on OEn causes the outputs

More information

74HC10; 74HCT General description. 2. Features and benefits. 3. Ordering information. Triple 3-input NAND gate

74HC10; 74HCT General description. 2. Features and benefits. 3. Ordering information. Triple 3-input NAND gate Rev. 3 5 August 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a triple 3-input NAND gate. Inputs include clamp diodes that enable the use of current

More information

The 74LV08 provides a quad 2-input AND function.

The 74LV08 provides a quad 2-input AND function. Quad 2-input ND gate Rev. 03 6 pril 2009 Product data sheet. General description 2. Features 3. Ordering information The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC0

More information

74HC280; 74HCT bit odd/even parity generator/checker

74HC280; 74HCT bit odd/even parity generator/checker Rev. 3 15 September 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a 9-bit parity generator or checker. Both even and odd parity outputs are available.

More information

74AHC1G14; 74AHCT1G14

74AHC1G14; 74AHCT1G14 Rev. 6 18 May 29 Product data sheet 1. General description 2. Features 3. pplications 74HC1G14 and 74HCT1G14 are high-speed Si-gate CMOS devices. They provide an inverting buffer function with Schmitt

More information

74HC368; 74HCT368. Hex buffer/line driver; 3-state; inverting

74HC368; 74HCT368. Hex buffer/line driver; 3-state; inverting Rev. 3 9 August 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a hex inverting buffer/line driver with 3-state outputs controlled by the output enable

More information

74LV General description. 2. Features and benefits. 3. Ordering information. Dual D-type flip-flop with set and reset; positive-edge trigger

74LV General description. 2. Features and benefits. 3. Ordering information. Dual D-type flip-flop with set and reset; positive-edge trigger Rev. 3 9 September 2013 Product data sheet 1. General description The is a dual positive edge triggered, D-type flip-flop. It has individual data (nd) inputs, clock (np) inputs, set (nsd) and (nrd) inputs,

More information