JFET CAPACITANCE CALCULATIONS
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1 JFET CAPACITANCE CALCULATIONS JFET CAPACITANCE CALCULATIONS In order to simplify the design procedure for the frequency response of the JFET amplifier we will consider effect of each capacitance separately. In other words, treat all others as if they are very large in size while concentrating on the one being taken into consideration at the time. Figure below is depicting the case in which C G is being considered as the only capacitance affecting the frequency response. Figure. SSAC of Common Source Stage with all Capacitors except C G are assumed to be too large to affect the frequency response. Note that C G creates a "High-Pass" single pole simple RC filter effect as Vsignal passes to the gate. The equivalent resistance it sees for the cut-off frequency is, HR eq L CG = R G + R signal w -3 db = i y j ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ z k R eq.c G { C G can be calculated from above for a given cut-off frequency. Equivalent Resistance for C D : Univ. of Southern Maine ELE342/343 Electronics 999/20
2 Prof. M. G. Guven Figure 2. SSAC of Common Source Stage with all Capacitors except C D are assumed to be too large to affect the frequency response HR eq L CD = R L + Hr ds R D L R out = Hr ds R D L Equivalent Resistance for C S : Figure 3. SSAC of Common Source Stage with all Capacitors except C S are assumed to be too large to affect the frequency response HR eq L CS = R ' L eq D C S Univ. of Southern Maine 2 ELE342/343 Electronics 999/20
3 Prof.M.G.Guven Figure 4. V Test - I Test Method Applied to Determine HR'L eq seen by C S at the source of the JFET Dv GS = V g - V s, V g = 0, V s = V test Make a Norton-Thevenin conversion: Figure 5. Univ. of Southern Maine 3 ELE342/343 Electronics 999/20
4 Prof. M. G. Guven V test = I test Hr ds + R D R L L + g m H-V s L.r ds V s = V test V test H + g m r ds L = I test Hr ds + R D R L L HR ' eql CS = V test ÄÄÄÄÄÄÄÄÄÄÄÄÄ I test = Hr ds + R D R L L ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ H + g m r ds L One can take into account multiple effects of all three capacitances by using a correction factor, k to calculate the capacitor values in the case when all of the capacitors are taken to create the same cut-off frequency. Obviously, if all except one are taken to be much larger than the values calculated above no such correction is needed. Then,. w -3 db = i y j ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ z.k k is correction for multiple capacitances. k R eq.c { w -3 db amplifier' s specified 3 db cut - off frequency k =.96 for 3 capacitances all chosen to create the same cut off point as the others If no 3-dB cut-off point is specified but a working frequency is given, in order to avoid the filtering effect of the capacitances their values should be chosen to create cut-off points well below the lowest operating frequency. A safe rule is to leave a factor of 0 as given below. 2. i y j ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ z k R eq.c { w lowest ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ 0 If there is no 3 db point specified. Univ. of Southern Maine 4 ELE342/343 Electronics 999/20
5 Prof.M.G.Guven ü Capacitor Calculations For The Example Circuit above: f -3 db 50 hz i y j ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ z k R eq.c.h.96l = 2 pf H.96L -3 db î C ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ = ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ { 2 pf -3 db R eq 57 R eq C G ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ = 3.5 nfarad Ceramic or paper will do. 57 * 470 KW C D ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ 57 * HR out + R L L = ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ 57 * H20 KW +smalll = 320 nfarad HR L = small is the worstl C S : HR ' eql CS = Hr ds + R D R L L ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ = 34 KW +H23.5 KW R LL ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ ÄÄÄÄÄÄÄÄÄÄÄÄÄÄ > ÄÄÄÄÄÄÄÄ = KW H + g m r ds L * 34 KW g m C S ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ = 7.6 mfarad Electrolytic or Tantalum 57 * H KW 5.3 KWL Homework: Use Microsim Suite to draw the circuit diagram of this design and verify its bias as well as the small signal gain and frequency response with J2N389. Make sure you run the simulation with the SPICE parameters of the JFET modified to the numbers used in the example above. Univ. of Southern Maine 5 ELE342/343 Electronics 999/20
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