NCP ma, Wide Input Range, Voltage Regulator

Transcription

1 NCP6 5 ma, Wide Input Range, Voltage Regulator The NCP6 is a CMOS 5 ma linear voltage regulator with high input voltage and ultra low supply current. It incorporates multiple protection features such as peak current limit, short circuit current limit and thermal shutdown to ensure a very robust device. A high maximum input voltage tolerance of 5 V and a wide temperature range make the NCP6 suitable for a variety of demanding applications. MARKING DIAGRAMS Features Operating Input Voltage Range: V to 36 V Output Voltage Range:. to 1. V (.1 steps) ±% Output Voltage Accuracy Output Current: min 5 ma (V IN = V, V OUT = 5 V) Line Regulation:.5%/V Peak Current Limit Circuit Short Current Limit Circuit Thermal Shutdown Circuit Available in SOT 9 5 and SOIC6 TL Package These are Pb Free Devices SOIC6 TL CASE 751BR SOT 9 5 CASE 5AB 1 1 XXX XMM XXX XMM Typical Applications Power source for home appliances Power source for car audio equipment, navigation system Power source for notebooks, digital TVs, cordless phones and private LAN systems Power source for office equipment machines such as copiers, printers, facsimiles, scanners, projectors, etc. XXXX MM = Specific Device Code = Date Code (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet. VIN C1 1n NCP6x VIN VOUT CE GND C 1n VOUT Figure 1. Typical Application Schematic Semiconductor Components Industries, LLC, 11 February, 11 Rev. 1 1 Publication Order Number: NCP6/D

2 NCP6 VIN VOUT Internal VR Vref CE Current Limit Short Protection Thermal Shutdown GND Figure. Simplified Schematic Block Diagram PIN FUNCTION DESCRIPTION Pin No. SOT9 Pin No. SOIC6 TL Pin Name Description 5 6 VIN Input pin GND Ground pin, all ground pins must be connected together when it is mounted on board GND Ground pin, all ground pins must be connected together when it is mounted on board 5 GND Ground pin, all ground pins must be connected together when it is mounted on board 3 3 CE Chip enable pin ( H active) 1 1 VOUT Output pin

3 NCP6 ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit Input Voltage V IN.3 to 5 V Peak Input Voltage (Note 1) V IN 6 V Output Voltage VOUT.3 to VIN V Chip Enable Input VCE.3 to VIN V Output Current I OUT 15 ma Power Dissipation SOT 9 P D 9 mw Power Dissipation SOIC6 TL 17 Junction Temperature T J to 15 C Storage Temperature T STG 55 to 15 C ESD Capability, Human Body Model (Note ) ESD HBM V ESD Capability, Machine Model (Note ) ESD MM V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Duration time = ms. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC Q1 (EIA/JESD A11) ESD Machine Model tested per AEC Q1 3 (EIA/JESD A115) Latchup Current Maximum Rating tested per JEDEC standard: JESD7. THERMAL CHARACTERISTICS Rating Symbol Value Unit Thermal Characteristics, SOT 9 Thermal Resistance, Junction to Air Thermal Characteristics, SOIC6 TL Thermal Resistance, Junction to Air R JA 111 C/W R JA 59 C/W 3

4 NCP6 ELECTRICAL CHARACTERISTICS T A = 5 C Parameter Test Conditions Symbol Min Typ Max Unit Operating Input Voltage VIN 36 V Output Voltage V IN = VOUT + 3 V, I OUT = 1 ma VOUT x.9 x1. V Output Voltage Temp. Coefficient V IN = VOUT + 3 V, I OUT = 1 ma, T A = to 15 C ±1 ppm/ C Line Regulation V IN = VOUT V to 36 V, I OUT = 1 ma Line Reg.5. %/V Load Regulation V IN = VOUT + 3 V, IOUT = 1 ma to ma. V V OUT < 5. V Load Reg 1 5 mv 5. V V OUT < 1. V 35 Dropout Voltage I OUT = ma. V V OUT < 3.7 V VDO (Note 3) V 3.7 V V OUT <. V V V OUT < 5. V V V OUT < 1. V..35 Output Current V IN = VOUT + 3 V IOUT 5 ma Short Current Limit V OUT = V I SC 5 ma Quiescent Current V IN = VOUT + 3 V, IOUT = ma IQ 9 A Standby Current V IN = 36 V, V CE = V ISTB.1 1 A CE Pin Threshold Voltage CE Input Voltage H VCEH 1.5 V IN V CE Input Voltage L VCEL.3 Thermal Shutdown Temperature T SD 15 C Thermal Shutdown Release Temperature T SR 15 C Power Supply Rejection Ratio VIN = 5. V, V OUT =. V, ΔV IN PK PK =. V, I OUT = 3 ma, f = 1 khz PSRR 3 db Output Noise Voltage V OUT =. V, I OUT = 3 ma, f = 1 Hz to 1 khz VN V rms 3. Dropout voltage for. V V OUT < 3.7 V can be computed by this formula: V DO = V V OUTSET

5 NCP V IN =. V.5 V 5. V 5.5 V V IN = 6.5 V 6. V 5. V 5.5 V Figure 3. Output Voltage vs. Output Current. V Version (T J = 5 C) Figure. Output Voltage vs. Output Current 3.3 V Version (T J = 5 C) V 1.5 V 11 V 11.5 V V 1.5 V 15 V 15.5 V Figure 5. Output Voltage vs. Output Current. V Version (T J = 5 C) Figure 6. Output Voltage vs. Output Current 1 V Version (T J = 5 C) V DO (V) T J = 5 C 15 C C Figure 7. Dropout Voltage vs. Output Current. V Version V DO (V) T J = 5 C 15 C C Figure. Dropout Voltage vs. Output Current 1 V Version 5

6 NCP V IN = 5. V T J, JUNCTION TEMPERATURE ( C) Figure 9. Output Voltage vs. Temperature,. V Version V IN = 6.3 V T J, JUNCTION TEMPERATURE ( C) Figure 1. Output Voltage vs. Temperature, 3.3 V Version..15 V IN = 11 V V IN = 15 V T J, JUNCTION TEMPERATURE ( C) Figure 11. Output Voltage vs. Temperature,. V Version T J, JUNCTION TEMPERATURE ( C) Figure 1. Output Voltage vs. Temperature, 1 V Version 1 1. V 1 V V V I GND ( A) V V OUT =. V I GND ( A) V V OUT =. V 6 1 T J, JUNCTION TEMPERATURE ( C) Figure 13. Supply Current vs. Temperature T J, JUNCTION TEMPERATURE ( C) Figure 1. Supply Current vs. Input Voltage 6

7 NCP ma ma ma ma.5 I OUT = ma 1..5 I OUT = ma V IN, INPUT VOLTAGE (V) Figure 15. Output Voltage vs. Input Voltage,. V Version V IN, INPUT VOLTAGE (V) Figure 16. Output Voltage vs. Input Voltage, 3.3 V Version ma ma I OUT = ma V IN, INPUT VOLTAGE (V) Figure 17. Output Voltage vs. Input Voltage,. V Version ma ma. I OUT = ma V IN, INPUT VOLTAGE (V) Figure 1. Output Voltage vs. Input Voltage, 1 V Version PSRR (db) I OUT = 1 ma 1 ma 3 ma FREQUENCY (khz) Figure 19. PSRR,. V Version, V IN = 5. V PSRR (db) I OUT = 1 ma 1 ma 1 3 ma FREQUENCY (khz) Figure. PSRR, 3.3 V Version, V IN = 6.3 V 7

8 NCP6 PSRR (db) I OUT = 1 ma 3 1 ma 1 3 ma FREQUENCY (khz) Figure 1. PSRR, 3.3 V Version, V IN = 6.3 V V N ( V rms / Hz) FREQUENCY (khz) Figure. Output Voltage Noise,. V Version, V IN = 5. V, I OUT = 3 ma V N ( V rms / Hz) FREQUENCY (khz) Figure 3. Output Voltage Noise, 3.3 V Version, V IN = 6.3 V, I OUT = 3 ma V N ( V rms / Hz) FREQUENCY (khz) Figure. Output Voltage Noise,. V Version, V IN = 11. V, I OUT = 3 ma 7 6 V N ( V rms / Hz) FREQUENCY (khz) Figure 5. Output Voltage Noise, 1. V Version, V IN = 15. V, I OUT = 3 ma

9 NCP t ( s) Figure 6. Line Transients,. V Version, t R = t F = 5 s, I OUT = 1 ma V IN (V) V IN (V) t ( s) Figure 7. Line Transients, 3.3 V Version, t R = t F = 5 s, I OUT = 1 ma V IN (V) t ( s) Figure. Line Transients,. V Version, t R = t F = 5 s, I OUT = 1 ma 9

10 NCP V IN (V) t ( s) Figure 9. Line Transients, 1. V Version, t R = t F = 5 s, I OUT = 1 ma t (ms) Figure 3. Load Transients,. V Version, I OUT = 1 ma, t R = t F = 5 s, V IN = 5. V t (ms) Figure 31. Load Transients, 3.3 V Version, I OUT = 1 ma, t R = t F = 5 s, V IN = 6.3 V 3 1 1

11 NCP t (ms) Figure 3. Load Transients,. V Version, I OUT = 1 ma, t R = t F = 5 s, V IN = 11. V t (ms) Figure 33. Load Transients, 1. V Version, I OUT = 1 ma, t R = t F = 5 s, V IN = 15. V t (ms) Figure 3. Load Transients,. V Version, I OUT = 5 ma, t R = t F = 5 s, V IN = 5. V

12 NCP t (ms) Figure 35. Load Transients, 3.3 V Version, I OUT = 5 ma, t R = t F = 5 s, V IN = 6.3 V t (ms) Figure 36. Load Transients,. V Version, I OUT = 5 ma, t R = t F = 5 s, V IN = 11. V t (ms) Figure 37. Load Transients, 1. V Version, I OUT = 5 ma, t R = t F = 5 s, V IN = 15. V

13 NCP I OUT = 1 ma I OUT = ma 1. I OUT = 5 ma.5 Chip Enable t ( s) Figure 3. Start up,. V Version, V IN = 5. V V CE (V) 3 I OUT = 1 ma I OUT = ma 1 I OUT = 5 ma Chip Enable t ( s) Figure 39. Start up, 3.3 V Version, V IN = 6.3 V V CE (V) 6 I OUT = 1 ma I OUT = ma I OUT = 5 ma 16 Chip Enable t ( s) Figure. Start up,. V Version, V IN = 11. V V CE (V) 13

14 NCP6 Chip Enable I OUT = ma V CE (V) I OUT = 1 ma I OUT = 5 ma t ( s) Figure 1. Start up, 1. V Version, V IN = 15. V 1

15 NCP6 APPLICATION INFORMATION A typical application circuit for NCP6 series is shown in Figure. VIN VIN NCP6x VOUT C1 C CE 1 n 1n GND Figure. Typical Application Schematic VOUT Input Decoupling Capacitor (C1) The device is stable without any input capacitance, but if input line is long and has high impedance or if more stable operation is needed, input capacitor C1 should be connected as close as possible to the IC. Recommended range of input capacitor value is 1 nf to 1 F. Output Decoupling Capacitor (C) The NCP61 can work stable without output capacitor, but if faster response and higher stability reserve is needed, output capacitor should be connected as close as possible to the device. Recommended range of output capacitance is 1 nf to 1 F. Larger values of output capacitance and lower ESR improves dynamic parameters. Enable Operation The enable pin CE may be used for turning the regulator on and off. The device is activated when high level is connected to CE pin. Do not keep CE pin not connected or between VCEH and VCEL voltage levels. Otherwise output voltage would be unstable or indefinite and unexpected would flow internally. Thermal As a power across the IC increase, it might become necessary to provide some thermal relief. The maximum power dissipation supported by the device is dependent upon board design and layout. Mounting pad configuration on the PCB, the board material, and also the ambient temperature affect the rate of temperature increase for the part. When the device has good thermal conductivity through the PCB the junction temperature will be relatively low in high power dissipation applications. The IC includes internal thermal shutdown circuit that stops operation of regulator, if junction temperature is higher than 15 C. After that, when junction temperature decreases below 15 C, the operation of voltage regulator would restart. While high power dissipation condition is, the regulator starts and stops repeatedly and protects itself against overheating. PCB layout Pins number and of SOT9 5 package and pins number, and 5 of SOIC6 TL must be wired to the GND plane while it is mounted on board. Make VIN and GND lines sufficient. If their impedance is high, noise pickup or unstable operation may result. Connect capacitors C1 and C as close as possible to the IC, and make wiring as short as possible. ORDERING INFORMATION Device Nominal Output Voltage Description Marking Package Shipping NCP6HT1G. V Enable High N SOT9 5 (Pb Free) NCP6H3T1G 3. V Enable High N3 SOT9 5 (Pb Free) NCP6H33T1G 3.3 V Enable High N33 SOT9 5 (Pb Free) NCP6HT1G. V Enable High N SOT9 5 (Pb Free) 1 / Tape & Reel 1 / Tape & Reel 1 / Tape & Reel 1 / Tape & Reel NCP6H1T1G 1. V Enable High N1 SOT9 5 (Pb Free) 1 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD11/D. *To order other package and voltage variants, please contact your ON Semiconductor sales representative. 15

16 NCP6 PACKAGE DIMENSIONS SOIC6 (HSOP6) CASE 751BR 1 ISSUE O D b1 6 H 1 3 B D A1 A e A E X b 6X.1 C SEATING PLANE L.1 M C A-B D C A3 F L DETAIL A DETAIL A C SEATING PLANE RECOMMENDED SOLDERING FOOTPRINT* 3.1 PITCH NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y1.5M, CONTROLLING DIMENSION: MILLIMETERS 3. DIMENSION b AND b1 DO NOT INCLUDE DAMBAR PROTRUSION. ALLOWAQBLE PROTRUSION SHALL BE.1 mm IN EXCESS OF MAXIMUM MATERIAL CONDITION.. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED.15 mm PER SIDE. DIMENSIONS D AND E ARE DETERMINED AT DATUM F. 5. DATUMS A AND B ARE DETERMINED AT DATUM F. 6. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. MILLIMETERS DIM MIN MAX A A1.5.5 A b.3.5 b D E e 3.1 BSC H L..6 L.5 BSC 6X X 1.7 X.6 DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 16

17 NCP6 PACKAGE DIMENSIONS SOT 9, 5 LEAD CASE 5AB 1 ISSUE O E D H NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y1.5M, CONTROLLING DIMENSION: MILLIMETERS. 3. LEAD THICKNESS INCLUDES LEAD FINISH.. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. 5. DIMENSIONS L, L, L3, L, L5, AND H ARE MEAS- URED AT DATUM PLANE C. C A 1 TOP VIEW SIDE VIEW c.1 C MILLIMETERS DIM MIN MAX A b.3.5 b c.3.5 D..6 D E..6 e H.5.5 L L. 1. L L L5..6 e b1 e b L RECOMMENDED MOUNTING FOOTPRINT* L 1 3 X L3 L 5 D BOTTOM VIEW L X 1.5 X.6 DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 17 USA Phone: or 3 36 Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: 955 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NCP6/D