Timed Automata as Task Models for Event-Driven Systems

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1 Timed Automt s Tsk Models for Event-Driven Systems Christer Norström 1 nd Anders Wll 1 1 Mälrdlen University Deprtment of Computer Engineering P.O. Box 883, S Västerås, Sweden Wng Yi 1;2 2 Uppsl University Deprtment of Computer Systems P.O. Box 325, S Uppsl, Sweden yi@docs.uu.se Abstrct In this pper, we extend the clssic model of timed utomt with notion of rel time tsks. The min ide is to ssocite ech discrete trnsition in timed utomton with tsk (n executble progrm). Intuitively, discrete trnsition in n extended timed utomton denotes n event relesing tsk nd the gurd on the trnsition specifies ll the possible rriving times of the event (insted of the so clled miniml inter-rrivl time). This yields generl model for hrd rel-time systems in which tsks my be periodic nd non-periodic. We show tht the schedulbility problem for the extended model cn be trnsformed to rechbility problem for stndrd timed utomt nd thus it is decidble. This llows us to pply model-checking tools for timed utomt to schedulbility nlysis for event-driven systems. In ddition, bsed on the sme model of system, we my use the tools to verify other properties (e.g. sfety nd functionlity) of the system. This unifies schedulbility nlysis nd forml verifiction in one frmework. We present n exmple where the model checker UPPAAL is pplied to check the schedulbility nd sfety properties of control progrm for turning lthe. 1. Introduction The trditionl pproch to the development of hrd reltime system is often bsed on scheduling theory. There re vrious methods [5, 12, 7] e.g. rte monotonic scheduling, which hve been very successful for the nlysis of timedriven systems s tsks re periodic. To del with nonperiodic tsks in event driven systems, the stndrd method is to consider non-periodic tsks s periodic using the miniml inter-rrivl times s tsk periods. Clerly, the nlysis result bsed on such tsk model would be pessimistic in mny cses, e.g. tsk set which is schedulble my be considered s non-schedulble s the inter-rrivl times of the tsks my vry over time, tht re not necessry miniml. In recent yers, in the re of forml methods, there hve been severl dvnces in forml modeling nd nlysis of rel time systems bsed the theory of timed utomt due to the pioneering work of Alur nd Dill [2]. Notbly, number of verifiction tools hve been developed (e.g. KRONOS nd UPPAAL [6, 4]) in the frmework of timed utomt, tht hve been successfully pplied in industril cse studies (e.g. [3, 13, 11]). Timed utomt hve proved expressive enough for mny rel-life exmples, in prticulr, for eventdriven systems. The dvntge with timed utomt is tht one my specify very relxed timing constrints on events (i.e. discrete trnsitions) thn the trditionl pproch in which events re often considered to be periodic. However, it is not cler how the model of timed utomt cn be used for schedulbility nlysis. In this pper, we present n extended version of timed utomt with rel-time tsks to provide model for event-driven systems. We show tht the extended model cn be used for both schedulbility nlysis nd verifiction of other properties, e.g. sfety nd liveness properties of timed systems. This unifies schedulbility nlysis nd forml verifiction in one frmework. The min ide is to ssocite ech discrete trnsition in timed utomton with tsk (or severl tsks in the generl cse). A tsk is ssumed to be n executble progrm with two given prmeters: its worst execution time nd dedline. Intuitively, discrete trnsition in n extended timed utomton denotes n event relesing tsk nd the gurd (clock constrints) on the trnsition specifies ll the possible rrivl times of the ssocited tsk. Whenever tsk is relesed, it will be put in the scheduling queue for execution. We ssume tht the tsks will be executed ccording to given scheduling strtegy e.g. erliest dedline first. Then dely trnsition of the timed utomton corresponds to the execution of the tsk with erliest dedline nd idling for the other witing tsks.

2 Thus, the sequences of discrete trnsitions of n extended timed utomton will correspond to the sequences of rrivls of non-periodic tsks. We sy tht such sequence of tsks is schedulble if ll the tsks cn be executed within their dedlines. Nturlly n utomton is schedulble if ll the tsk sequences re schedulble. We shll show tht under the ssumption tht the tsks re non-preemptive, the schedulbility problem cn be trnsformed to rechbility problem for ordinry timed utomt nd thus it is decidble. This llows us to pply model-checking tools for timed utomt to schedulbility nlysis for event-driven systems. We present n exmple where the model checker UPPAAL is pplied to check the schedulbility nd sfety properties of control progrm in control pplictions. The rest of this pper is orgnized s follows: Section 2 presents the syntx nd semntics of the extended timed utomt with tsks. Section 3 shows how to trnsform the scedulbility nlysis problem for extended model to rechbility problem for ordinry timed utomt, nd thus schedulbility nlysis my be performed by the existing verifiction tools for timed utomt. Section 4 provides n exmple to illustrte our pproch. Section 5 concludes the pper with summrized results nd future work. 2. Timed Automt with Rel-Time Tsks The theory of timed utomt ws first introduced in [2] nd hs since then estblished s stndrd model for rel time systems. We first give n brief review to fix the terminology nd nottion nd then present n extended version of the model with tsks Timed Automt A timed utomton is stndrd finite-stte utomton extended with finite collection of rel-vlued clocks. The trnsitions of timed utomton re lbelled with gurd ( condition on clocks), n ction, nd clock reset ( subset of clocks to be reset). Intuitively, timed utomton strts execution with ll clocks set to zero. Clocks increse uniformly with time while the utomton is within node. A trnsition cn be tken if the clocks fulfill the gurd. By tking the trnsition, ll clocks in the clock reset will be set to zero, while the remining keep their vlues. Thus trnsitions occur instntneously. Semnticlly, stte of n utomton is pir of control node nd clock ssignment, i.e. the current setting of the clocks. Trnsitions in the semntic interprettion re either lbelled with n ction (if it is n instntneous switch from the current node to nother) or positive rel number i.e. time dely (if the utomton stys within node letting time pss). For the forml definition, we ssume finite set of lphbets Act for ctions nd finite set of rel-vlued vribles C for clocks. We use ; b etc to rnge over Act nd X 1 ;X 2 etc. to rnge over C. We use B(C) rnged over by g nd lter by ffi etc, denote the set of conjunctive formuls of tomic constrints in the form: X i οm or X i X j οn where X i ;X j 2 C re clocks, ο 2 f»;<; ;>g, nd m; n re nturl numbers. The elements of B(C) re clled clock constrints. Definition 1. A timed utomton over ctions Act nd clocks C is tuple hn; l 0 ;Ei where ffl N is finite set of nodes, ffl l 0 2 N is the initil node, nd ffl E N B(C) Act 2 C N is the set of edges. When hl; g; ; r;l 0 i2e, we write l g;;r! l 0. Formlly, we represent the vlues of clocks s functions (clled clock ssignments) from C to the non negtive rels R 0. We denote by V the set of clock ssignments for C. A semnticl stte of n utomton is now pir (l; u), where l is node of the utomton nd u is clock ssignment nd the semntics of the utomton is given by trnsition system with the following two types of trnsitions (corresponding to dely trnsitions nd ction trnsitions): ffl (l; u)!(l; d u + d) ffl (l; u)!(l 0 ;u 0 ) if l g;;r! l 0, u 2 g nd u 0 =[r 7! 0]u where for d 2 R 0, u + d denotes the clock ssignment which mps ech clock X in C to the vlue u(x) +d, nd for r C, [r 7! 0]u denotes the ssignment for C which mps ech clock in r to the vlue 0 nd grees with u over Cnr. By u 2 g we denote tht the clock ssignment u stisfies the constrint g Extended Timed Automt with Tsks We shll view timed utomton s n bstrct model of running process. The model describes the possible events (lphbets ccepted by the utomton) tht my occur during the execution of the process nd the occurrence of the events must follow the timing constrints (given by the clock constrints). But the model gives no informtion on how these events should be hndled. In mny cses, for exmple in control system, when n externl event occurs, some computtion must be performed to hndle the event. A more concrete exmple is n interrupt hndling system.

3 m x>2 b n y:=0 x<4 y>2 Figure 1. An Exmple Timed Automton with Tsks. Whenever n interrupt signl occurs, the ssocited interrupt hndling progrm will be executed. Now, ssume tht ech ction symbol in timed utomton is ssocited with progrm clled tsk. Let P rnged over by p etc, denote the set of tsks. We further ssume tht the worst cse execution time nd hrd dedline of the tsks in P re known. We shll use clock constrints to specify the rrivl times of the tsks. Thus, ech tsk p in P is chrcterized s pir (c; d) of nturl numbers with c» d where c is the execution time of p nd d is the reltive dedline for p. The dedline d is reltive dedline mening tht when tsk p is relesed, it should finish within d time units. Definition 2. An extended timed utomton with tsks (TAT), over ctions Act, clocks C nd tsks P is tuple hn; l 0 ;E;Ti where ffl hn; l 0 ;E;Ti is stndrd timed utomton, ffl T : Act,! P is prtil function ssigning tsks to ctions. Semnticlly, n extended utomton my perform two types of trnsitions just s n ordinry timed utomton. In ddition, n ction trnsition will relese new instnce of the tsk ssocited with the ction. Assume tht there is queue holding ll the tsk instnces generted by ction trnsitions nd redy to run. The queue corresponds to the redy queue in n operting systems. A semntic stte of n extended utomton is triple consisting of node (the current control node), clock ssignment (the current setting of the clocks) nd tsk queue (the current sttus of the redy queue). Consider the utomton of Figure 1. Let p1 nd p2 be tsks hndling the interrupt signls nd b respectively. Assume tht the initil stte is (m; [x = 0;y = 0]; []) where the clocks re 0 nd the tsk queue is empty. Then the utomton my demonstrte the following sequence of trnsitions: (m; [x =0;x =0]; [])! 3 (m; [x =3;y =3]; [])! (n; [x =0;y =3]; [p1])! (n; [x =0;y =0]; [p1;p1]) 3! (n; [x =3;y =3]; [p1;p1])! (n; [x =3;y =0]; [p1;p1;p1]) 1! (n; [x =4;y =1]; [p1;p1;p1]) b! (m; [x =4;y =1]; [p1;p1;p1;p2]) ::: Note tht severl instnces of the sme tsk my be relesed. However, the number of copies my be bounded by the clock constrints. For exmple, in stte (n; [x =4;y = 1]; [p1; p1; p1]), no more instnce of p1 will be relesed becuse the clock vlues will not stisfy the constrint x<4 nd y > 2, but n instnce of p2 my be relesed by the b-trnsition (which hs no timing constrint). In the bove exmple, we hve only shown tht the tsk queue is growing due to ction trnsitions. Now we discuss the effect of dely trnsitions on tsk queue. We shll see tht the queue will be shrinking due to dely trnsitions. Let p1 =p2 =(2; 8) i.e. the computtion time of both p1 nd p2 is 2 nd the dedline is 8. We ssume tht there is processor running the tsk instnces ccording to certin scheduling strtegy. A dely trnsition with t time units is to execute the tsks in the queue with t time units. After the trnsition, tsk will be removed from the queue (shrinking) if its computtion time becomes 0 nd the dedlines of ll tsks in the queue will be decresed by t (since time hs progressed by t). Now we hve precise description on the stte chnges for the bove trnsition sequence: (m; [x =0;x =0]; [])! 3 (m; [x =3;y =3]; [])! (n; [x =0;y =3]; [(2; 8)])! (n; [x =0;y =0]; [(2; 8); (2; 8)]) 3! (n; [x =3;y =3]; [(1; 5)])! (n; [x =3;y =0]; [(1; 5); (2; 8)]) 1! (n; [x =4;y =1]; [(2; 7)]) b! (n; [x =4;y =1]; [(2; 7); (2; 8)]) ::: More precisely we hve the following ssumptions on the underlining execution model: 1. A redy queue holding the tsk instnces relesed nd witing for execution. A tsk instnce will be removed from the queue when its computtion time becomes An on-line scheduler Sch sorting the queue ccording to given scheduling strtegy. It will report? if the queue becomes non-schedulble when new tsk instnce is dded.

4 3. A single processor executing the tsks ccording to the ordering of the queue. It will lwys execute the tsk in the first position. The tsks re executed nonpreemtive. Further we use Run(q; t) to denote the resulted tsk queue fter t time units of execution. The mening of Run(q; t) should be obvious. For exmple, let q =[(2; 7); (2; 8)] nd t = 3 then Run(q; t) = [(1; 5)] in which the first tsk is finished nd the second hs been executed for 1 time unit. Now we re redy to present the trnsitionl rules for extended timed utomt. Definition 3. The semntics of n extended utomton is trnsition system defined by the following trnsition rules (corresponding to relese of new tsk nd execution of existing tsks): ffl (l; u; q)! (l 0 ;u 0 ; Sch(q 0 )) if l g;;r! l 0, u 2 g, u 0 = u[r 7! 0], nd q 0 = q :: T () ffl (l; u; q) t! (l; u + t; Run(q; t)) We shll write (l; u; q)! (l 0 ;u 0 ;q 0 ) if (l; u; q)! (l 0 ;u 0 ;q 0 d ) for n ction or (l; u; q)! (l 0 ;u 0 ;q 0 ) for dely d. Finlly, to hndle concurrency nd synchroniztion, prllel composition of extended timed utomt my be introduced in the sme wy s for ordinry timed utomt (e.g. see [10]) using the notion of synchroniztion function [8]. For exmple, consider the prllel composition AjjB of A nd B over the sme set of ctions Act. The set of nodes of AjjB is simply the product of A s nd B s nodes, the set of clocks is the (disjoint) union of A s nd B s clocks, the edges re bsed on synchronizble A s nd B s edges with enbling conditions conjuncted nd reset-sets unioned. Note tht due to the notion of synchroniztion function [8], the ction set of the prllel composition will be Act nd thus the tsk ssignment function for AjjB is the sme s for A nd B. 3. Schedulbility Anlysis s Rechbility Anlysis Trditionlly, the temporl ttributes for rel-time computer systems re derived from their environment, e.g. period times, etc. These ttributes re used for constructing model of the system in terms of its temporl behvior. Such temporl model is often clled tsk model, which is used to verify whether the system is schedulble or not, but other properties such s functionl nd sfety properties cn not be verified bsed on such model. In our pproch, we my construct model for the whole system including the environment nd tsks in the control system. The prllel composition of these models give us the possibility of not only verifying temporl constrints, but lso its other spects such s synchroniztion between tsks nd simple computtions within tsks etc. Normlly, system is sid to be schedulble if ll tsks cn lwys be executed within their dedlines, i.e. no dedlines re violted. The objective of the schedulbility nlysis is to verify tht there re no violtion of dedlines in ll situtions where the system my evolve to. Now we formlize the notion of schedulbility for extended timed utomt. Definition 4. An extended timed utomton A is nonschedulble if it my rech non-schedulble stte, tht is: (l 0 ;u 0 ;q 0 )! Λ (l; u;?) where (l 0 ;u 0 ;q 0 ) is the initil stte of A, nd! Λ is the trnsitive closure of!. We sy tht A is schedulble if nd only if ll its rechble sttes re schedulble. Thus, the schedulbility of extended utomt cn be checked by rechbility nlysis, to prove tht (l; u;?) is not rechble in the utomton. However, it is not obvious tht the rechbility problem for extended utomt is decidble. In fct, the decidbility of this problem is closely relted to the preemptiveness of the tsks P. The following is one of our min results in this pper. Theorem 1. The problem of checking schedulbility for extended timed utomt over non-preemptive tsks P is decidble. Proof ide: It is bsed on the fct tht the problem of schedulbility checking for extended timed utomt cn be trnsformed to the rechbility problem for stndrd timed utomt, which is known to be decidble [1]. See the following subsection for detils on the trnsformtion Trnsformtion from TAT to ordinry timed utomt The ide is to construct timed utomton simulting redy queue nd scheduler tht code ll possible scenrios of the system described by TAT, including the tsks in the queue nd schedules. For exmple, consider the temporl ttributes of the two tsks p nd tsk p b, where p hd worst-cse-execution time (wcet), of 4 time units (tu), nd dedline (d), of 7 tu. The second tsk p b hs wcet of 3 tu nd dedline of 5 tu. Intuitively for system to be schedulble, the redy queue cn contin only finite number of tsk instnces. More

5 precisely, there cn only be MNT i instnces of tsk i, where MNT i is given by: MNT i = μ di c i ν where d i denotes the dedline for tsk i nd c i denotes the computtion time. By clculting the mximum length of the redy queue, we know tht to be schedulble, the queue in our exmple cn only contin one instnce of p nd one instnce of p b.if t ny time point, there re more thn one instnces of prticulr tsk in the redy queue witing for execution, we know for sure tht the system is non-schedulble nd the error stte should be reched. This ensures finite number of sttes in our model of the scheduler nd the redy queue. Now, we use the bove exmple to present the lgorithm for constructing the scheduler nd queue utomton, which cn be generlized esily to the generl cse. 1. Crete three different nodes, one node in which the redy queue is empty, one for which there exists tsk instnces in the redy queue nd, finlly n error node. 2. Crete trnsitions from the empty node to the running node, one for every ction ssocited with tsk. Furthermore, tsks cn rrive while in the run node, consequently we need one trnsition from run bck to run for every possible tsk instnce s well. In order to keep trck of every new tsk instnce, unique semphore for every instnce is introduced (denoted s tsk nd tskb in Figure 2). We lso need unique dedline clock for every instnce in order to know which tsk to execute nd to detect dedline violtions. 3. According to EDF, the tsk hving lest time left until its dedline should be executed. For ll possible tsk instnces, crete trnsition from run to run which compres its reltive dedline to ll the other redy tsks. In our exmple p should be executing if 7 d < 5 d b, nd p b if 5 d b < 7 d where d nd d b re the dedline clocks. In order to keep trck of execution time of the running tsk, clock is reseted on every relese of tsk. In our exmple, this clock is denoted s c. Furthermore, s we consider the non-preemptive cse, no tsk cn strt to execute while nother tsk lredy is executing. Thus we need semphore to know whether the processor is idle or not (denoted r in Figure 2). 4. Introduce one trnsition from run to run for every possible instnce which termintes the tsk whenever c becomes equl to its specified execution time nd its dedline clock is less or equl to its specified dedline. Termintion is modeled by resetting the instnce semphore. 5. If redy queue gets empty, i.e. no tsks instnces re present in the queue trnsition to the empty node should be tken. 6. For ech possible tsk instnce we introduce trnsition from run to error if: ffl An ction A occurs, mking the number of instnces of A exceeding MNT ffl The executing tsk hs overrun its dedline ffl A tsk pending for execution in the redy queue hs exceeded its dedline Figure 2 shows the result from trnsforming our exmple system shown. This is n ordinry timed utomt for which decidbility hs been proven in [1]. tsk==0 tsk==1 tskb==1 tskb==1 tsk==1 7-d<5-db tskb==0 r:=2 tsk==1 r:=1 tskb==1 5-db<7-d r:=1 tsk==0 r:=2 tskb==0 r==1? c==4 tsk:=1 d<=7 d:=0 r:=0 tsk:=0 empty b? tskb:=1 db:=0 tsk==0? d:=0 tskb==0 tsk:=1 b? db:=0 tskb:=1 r==2 run c==3 d<=5 r:=0 tskb:=0 tsk==1 d>7 tskb==1 db>5 tskb==1 b? tsk==1 error? Figure 2. A model of the redy queue nd the scheduler using ordinry timed utomt For the generl cse, the scheduler nd queue utomt is illustrted in Figure 3 where q denotes queue, r is the executing tsk, c mesures how long time the executing tsk hs been running nd d(i) is vector keeping trck of the time elpsed since the tsks entered the redy queue. C(i) is vector holding the worst cse execution time of ll tsks. Both re vectors re finite s been discussed bove. Moreover, the function sch() returns the instnce mong ll tsks residing in the queue hving lest time left until its dedline. Tsk i is returned by sch() if the predicte V 8m2q:m6=i d(i) d(m)» D i D m is true, where D i denotes the reltive dedline specified for tsk i.

6 t i? d(i):=0 r:=i d(r) >D r c<c(r) t i? i := insert(t i;q) d(i):=0 c=c(r) delete(t r;q) r = sch(q) 9t i 2 q : d(i) >D i ^ r 6= i being either on or off. Consequently, we hve to model ll these prts s network of TATs. Moreover, we hve two softwre tsks, the control tsk nd the emergency stop hndler. These prts lso hve to be modeled in TATs belonging to the network constituting the complete system Modeling the system error Figure 3. A generl model of the scheduler using ordinry timed utomt 4. A Cse Study with UPPAAL UPPAAL is model-checker for timed utomt [9]. As shown in the previous section, the scheduler nd redy queue cn be modeled s n ordinry timed utomton. In this section, we present n exmple showing how to use UP- PAAL for schedulbility checking. Our exmple system is event-driven ppliction controlling the speed of the shft in turning lthe. The objectives of the forml verifiction is to verify tht the system is schedulble nd the sfety requirement tht the engine is not turned on by the control tsk while the emergency stop is ctive. An event reports the current speed of the shft nd control tsk is checking tht the speed is within the speed limits (in our exmple speed=3). If the speed is to high (over 3), the engine is turned off nd if the speed is to low (below 3), the engine is turned on. There is lso n emergency stop function which is implemented in softwre. The setup is shown in Figure 4. Emergncy stop Stop/ctivte On/Off Emergency Tsk We strt by modeling the environment, i.e. the shft, the emergency stop button nd the engine. This cn for instnce be done s shown in Figure 5, 6. off? offs off? sttus:=0 ons on? sttus:=1 c:es sttus:=1 on? ups em_t>=5 empos:=0 em_t:=0 emb! empos:=1 downs em_t:=0 emb! Figure 6. A model of the engine nd the emergency stop button If the engine is on, the shft mkes complete revolution in between 4-8 time units, nd n event is generted every time the opticl sensor detects complete revolution. Next to model is the emergency stop hndler nd the control tsk. The control tsk hs clculted wcet of 2 tu nd hrd dedline of 3 tu (Figure 8). As for the control tsk, dedline nd wcet must be specified for the emergency stop hndler. According to our imgined requirement specifiction, it must respond within 2 tu, i.e. it hs dedline t 2 tu. The wcet estimtion result in wcet of 1 tu (see Figure 7). Furthermore, two subsequent ctivtions/dectivtion of the emergency stop cn not be less thn 5 tu in between. This gives us minimum interrrivl time for the emergency stop hndler of 5 tu. Shft Engine On/Off Velocity Control Tsk Figure 4. The setup for our exmple system on! ex>=1 em:=0 emh off! ex>=1 em:=1 strt (ex<=1) embr? empos==0 e embr? empos==1 e stop (ex<=1) As shown in Figure 4, the prts belonging to the systems environment re the shft hving n opticl sensor generting n event on every complete revolution, the emergency stop button hving two sttes: up or down nd the engine, Figure 7. A model of the emergency hndler in timed utomt

7 sttus==0 x>7 s (x<=8) sttus==1 x>7 speed:=1 sttus==0 x>=7 speed:=0 sttus==1 x>6 speed:=2 sb (x<=7) sttus==0 x>=6 speed:=1 sttus==1 x>5 speed:=3 sc (x<=6) sttus==0 x>=5 speed:=2 sttus==1 x>4 speed:=4 sd (x<=5) sttus==0 x>=4 speed:=3 se (x<=4) sttus==1 x>=4 speed:=4 Figure 5. A model of the shft in timed utomt cs velr? cx>=2 cx>=2 c off! lspeed:=speed c:clc em==0 lspeed>3 em==0 lspeed<=2 cx>=2 on! em==0 lspeed==3 toff ton (cx<=2) em==1 (cx<=2) noct (cx<=2) Figure 8. A model of the control tsk in timed utomt The model of the scheduler is omitted in the pper. However, this process will be generted utomticlly by UP- PAAL ccording to the lgorithm given in Section 3.1 nd will be invisible for the designer Verifying schedulbility nd sfety We use model checking nd rechbility nlysis on our network of TAT for this purpose. UPPAAL uses timed CTL lnguge for specifying properties to verify. To verify tht the system is schedulble, we must show tht the error stte is never rechble. We will use the lwys predicte in our exmple s lwys not ff is equivlent to never. This property is specified s shown in the formul below, scheduler.error mens the stte error in the process nmed scheduler: 82not scheduler:error For the sfety property we need to verify tht the system never rech stte where the control tsk is in position to turn the engine on while the emergency stop hs been ctivted. For our model, such n expression looks like the formul given below: 82not(control tsk:ton nd em =1) First we will verify the schedulbility property. As result UPPAAL tells us tht the property is not stisfied by giving counter exmple. Consequently, the system is not schedulble. In order to obtin schedulble system, the temporl constrints on the tsks hve to be modified. The counter exmple given by UPPAAL, shows tht the emergency hndler tsk misses its dedline if this event hppens just fter the control tsk hs been invoked. By chnging the dedlines for the control tsk nd the emergency stop hndler to 4 tu, the system becomes schedulble. This is verified by the sme property, but with n updted scheduler model. The model of the scheduler must be updted since now there cn exist two instnces of the control tsk nd four instnces of the emergency hndler simultneously in the redy queue. Next to verify is our sfety property, i.e. the control tsk should not be ble to turn the engine on s long s the emergency stop is ctivted. In this cse UPPAAL reports tht the property is stisfied nd consequently, the sfety requirement is fulfilled. It is of course possible to verify other functionl properties. For instnce, we cn verify tht the shft eventully will rotte with the set vlue. In our model, the set vlue is the speed of 3, i.e. the speed is eventully equl to 3. The corresponding formul given in UPPAAL logic is: 5. Conclusions 93speed =3 An importnt step in the development of embedded reltime systems is schedulbility nlysis tht is to check whether ll tsks in system cn be executed within the given dedlines in ll possible scenrios. The trditionl pproch to schedulbility nlysis is often bsed on scheduling theory nd tsk model, which hs been very successful for periodic tsks, but less successful for event-driven tsks. In this pper, we hve developed n extended version of timed utomt with rel-time tsks to provide model

8 for event-driven systems, which cn be used for modeling, schedulbility nlysis, forml verifiction, nd code genertion. The min ide is to ssocite ech discrete trnsition in timed utomton with tsk (n executble progrm e.g. written in C) with its worst cse execution time. Intuitively, discrete trnsition in n extended timed utomton denotes n event relesing tsk nd the gurd on the trnsition specifies ll the possible rriving times of the event (insted of the so clled miniml inter-rrivl time). This yields generl model for hrd rel-time systems in which tsks re non-periodic. In this model, n utomton is used to model control structure of systems nd ssocited tsks re used to perform computtion. Thus, code genertion for such model is reduced to trnsform the utomton into runnble progrm with procedure-cll. However, criticl problem is to gurntee tht ll the tsks ssocited with the utomton cn be executed within their dedlines. This is the so-clled schedulbility checking problem. As the min result of this pper, we hve shown tht the schedulbility checking problem for the extended timed utomt with rel time tsks cn be trnsformed to rechbility problem for stndrd timed utomt nd thus it is decidble. This result llows us to pply model-checking tools for timed utomt to schedulbility nlysis for event-driven systems. In ddition, bsed on the sme model of system, we my use the tools to verify other properties (e.g. sfety nd functionlity) of the system. This unifies schedulbility nlysis nd forml verifiction in one frmework. IEEE Rel-Time Systems Symposium, pges 66 75, Dec [7] M. L. Dertouzos. Control robotics: The procedurl control of physicl processes. Informtion Processing, [8] H. Hüttel nd K. G. Lrsen. The use of sttic constructs in modl process logic. In Logic t Botik 89, number 363, pges Springer Verlg, [9] K. G. Lrsen, P. Pttersson, nd Y. Wng. UPPAAL in nutshell. Springer Interntionl Journl of Softwre Tools for Technology Trnsfer, 1, [10] K. G. Lrsen, P. Petterson, nd Y. Wng. Compositionl nd symbolic model-checking of rel-time systems. In Proceedings of the 16th Rel-Time Systems Symposium, pges IEEE Computer Society Press, [11] M. Lindhl, P. Pettersson, nd W. Yi. Forml design nd nlysis of ger controller. Lecture Notes in Computer Science, 1384: , [12] C. Liu nd J. Lylnd. Scheduling Algorithms for Multiprogrmming in Hrd-Rel-Time Environment. Journl of the Assocition for Computing Mchinery, 2, [13] H. Lönn, P. Pettersson, nd W. Yi. Forml Verifiction of TDMA Protocol Strt-Up Mechnism. In Proceedings of 1997 IEEE Pcific Rim Interntionl Symposium on Fult- Tolernt Systems, pges , As future work, we pln to extend the UPPAAL model checker for schedulbility nlysis. Future work lso include code genertion which is to trnslte extended timed utomt with tsks into executble progrms. References [1] R. Alur. Model-checking in dense rel-time. Informtion nd computing, [2] R. Alur nd D. Dill. Automt for modelling rel-time systems. In Proceedings of ICALP 90, volume 443 of Lecture Notes in Computer Science. Springer, [3] Bengtsson, Griffioen, Kristoffersen, Lrsen, L. n d Pettersson, nd Yi. Verifiction of n udio protocol with bus collision using uppl. In Proceedings of CAV 96, volume 1102, [4] J. Bengtsson, K. G. Lrsen, F. Lrsson, P. Pettersson, nd W. Yi. UPPAAL in In Proc. of the 2nd Workshop on Tools nd Algorithms for the Construction nd Anlysis of Systems, number 1055 in Lecture Notes in Computer Science, pges Springer Verlg, Mr [5] G. C. Buttzzo. Hrd Rel-Time Computing Systems. Kluwer Acdemic Publishers, [6] C. Dws nd S. Yovine. Two exmples of verifiction of multirte timed utomt with KRONOS.In Proc. of the 16th

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