Appendix D: Basics of convolutional codes

Transcription

1 Appendix D: Basics of convolutional codes Convolutional encoder: In convolutional code (B. P. Lathi, 2009; S. G. Wilson, 1996; E. Biglieri, 2005; T. Oberg, 2001), the block of n code bits generated by the encoder in a particular time instant depends not only on the block of k message bits within that time instant but also on the block of data bits within a previous span of N-1 time instants (N>1). A convolutional code with constraint length N consists of an N-stage shift register (SR) and ν modulo-2 adders. ν1 ν 2 ν = s s s ; ν = s s Fig. D.1 Convolutional coder Fig. D.1 shows such a coder for the case N=3 and ν=2. The message bits are applied at the input of the SR. The coded digit stream is obtained at the commutator output. The commutator samples the ν modulo-2 adders in a sequence, once during each input-bit interval. Example: Assume that the input digits are Find the coded sequence output. Solution: Initially, the SRs s1=s2=s3=0. Note that SR just shifts the input data to the next SR in the next time instant. 1

2 When the first message bit 1 enters the SR, s1= 1, s2 = s3=0. Then ν1=1, ν2=1. The coder output is 11. When the second message bit 0 enters the SR, s1=0, s2=1, s3=0. Then ν1=1 and ν2=0. The coder output is 10. When the third message bit 1 enters the SR, s1=1, s2=0 and s3=1 Then ν1=0 and ν2=0. The coder output is 00. When the fourth message bit 0 enters the SR, s1=0, s2=1 and s3=0 Then ν1=1 and ν2=0. The coder output is 10. In order to stop, we add N-1 number of 0 s to the input stream and make sure that the last data digit (0 in this case) proceeds all the way through the SR in order to influence the N groups of ν digits. Hence when the input digits are 0101, we actually apply (L R) to the SR. The coder output is (L R) There are in all n=(n+k-1) ν digits in the coded output for every k input bits. 2

3 output = ν ν 1 2 ν = s s s ν = s s Fig. D.2 (a) 3-shift registers showing states a, b, c and d (b) State diagram for the coder State diagram: When a message bit enters the SR (s1) the coder outputs are determined not only by the message bit in s1 but also by the two previous bits already in s3 and s2. There are four possible combinations of the two previous bits in s3 and s2: 00, 01,10,11. We will name these four states as a, b, c, d respectively as shown in Fig. D.2 (a). The number of states is equal to 2 (N-1). A message bit 0 or 1 generates four different outputs depending on the encoder state. This entire behavior can be concisely expressed by the state diagram of Fig. D.2 (b). This is a four-state directed graph 3

4 used to represent the input-output relation of encoder. Convention: we will use solid lines when the input bit is 0, and dashed lines when the input bit is 1. Interpretations from State diagram D.2 (b): (1) State a goes to State a when the input is 0 and the output is 00 (2) State a goes to State b when the input is 1 and the output is 11 (3) State b goes to State c when the input is 0 and the output is 10 (4) State b goes to State d when the input is 1 and the output is 01 (5) State c goes to State a when the input is 0 and the output is 11 (6) State c goes to State b when the input is 1 and the output is 00 (7) State d goes to State c when the input is 0 and the output is 01 (8) State d goes to State d when the input is 1 and the output is 10 Note that the encoder cannot go directly from state a to states c or d. From any given state, the encoder can go to only two states directly by inputting a single message bit. Trellis diagram: Trellis diagram can be readily drawn using the above state diagram. It starts from scratch (all 0 s in the SR, i.e., state a) and makes transitions corresponding to each input data digit. These transitions are denoted by a solid line for the next data digit 0 and by a dashed line for the next data digit 1. Thus when the first input digit is 0, the encoder output is 00 (solid line) and when the input digit is 1, the encoder output is 11 (dashed line). We continue this way for the second input digit and so on as depicted in Fig. D.3. 4

5 Fig. D.3 Trellis diagram for the convolution coder Fig. D.4 Survivor paths after the 3 rd branch of the Trellis diagram for received sequence Decoding: We shall consider maximum-likelihood (ML) decoding (Viterbi s algorithm). Among various decoding methods for convolutional codes, Viterbi s ML algorithm is one of the best techniques in digital communications. As usual, ML receiver implies selecting a code word closest to the received code word. Because there are 2 k code words (k input data digits), the ML decision involves storage of 2 k code words and their comparison with the received word. The calculation 5

6 is extremely difficult for large k and result in exponential increase in complexity of the decoder. A major simplification was made by Viterbi in the ML calculation by noting that each of the four nodes (a, b, c and d) has only two predecessors. Each node can be reached through two nodes only and only the path agrees most with the received sequence (the minimum distance path) need to be retained for each node. Given a received sequence of bits, we need to find a path in the trellis diagram with the output digit sequence agrees most with the received sequence. Example: Suppose that the first six received digits are Find the survivor paths (minimum-distance path with the received sequence). Solution: Table D.1 Survivor paths after the 3 rd branch of the Trellis diagram for received sequence After 3 rd branches Paths Distance with received sequence Survivor? Node a Yes Node b Yes Node c Yes Node d Yes With four paths eliminated as illustrated in Table D.1, the four survivor paths are the only contenders. What we need to remember is the four survivor paths and their distances from the 6

7 received sequences. In general, the number of survivor paths is equal to the number of states, that is, 2 N-1. Once we have survivors at all the third-level nodes, we look at the next two received digits. To truncate the Viterbi algorithm and ultimately we need to decide on one path rather than four. This is done by forcing the last two data digits to be 00. Hence the received sequence is (L R) When the first dummy 0 enters the register, we consider the survivors only at nodes a and c. The survivors at nodes b and d are discarded because these nodes can be reached only when input bit is 1, as seen from the trellis diagram. When the second dummy 0 enters the register, we consider survivor at node a. We discard the survivor at node c because the last two dummy data 00 leads to the encoder state a. In terms of trellis diagram, this means that the number of states is reduced from four to two (a and c) by insertion of the first zero and to a single state (a) by insertion of the second zero. With the Viterbi algorithm, storage and computational complexity reduces considerably (proportional to 2N) and are very attractive for constraint length N<10. References: 1) B. P. Lathi, Modern digital and analog communication systems, Oxford University Press, ) E. Biglieri, Coding for wireless channels, Springer, ) S. G. Wilson, Digital Modulation and Coding, Pearson, ) T. Oberg, Modulation, Detection and Coding, John Wiley and Sons,