MOS Capacitors Prof. Ali M. Niknejad Prof. Rikky Muller

Size: px
Start display at page:

Download "MOS Capacitors Prof. Ali M. Niknejad Prof. Rikky Muller"

Transcription

1 EECS 105 Spring 2017, Modue 3 MOS Capacitors Prof. Ai M. Niknejad Prof. Rikky Muer Department of EECS University of Caifornia, Berkeey

2 Announcements Prof. Rikky Muer Wecome to the second haf of EE105! Professor Muer wi be ecturing Midterm 1 handed back today Mean = Median = Standard Dev = Midterm 2 on Thursday, March 23 in ecture Attend discussion sessions! They are hepfu for homework, exam reviews and topics not covered in ecture. 2 University of Caifornia, Berkeey

3 MOS Capacitor Prof. Rikky Muer Gate (n + poy) Body (p-type substrate) εs = 11.7ε 0 0 x Oxide (SiO 2 ) ε = 3.9ε 0 ery Thin! t ~1nm 3 MOS = Meta Oxide Semiconductor Sandwich of conductors separated by an insuator Meta is more commony a heaviy doped poysiicon (poy-si) ayer n + or p + ayer Was meta (e.g. A) unti ~1970 but changed to poy-si due to high temperature processing. After 2008, meta gates have been reintroduced! Learn more about MOS process technoogy in EE130 & EE143 NMOS à p-type substrate, PMOS à n-type substrate University of Caifornia, Berkeey

4 Meta-Oxide-Semi Junction Prof. Rikky Muer Gate (n + poy) Body (p-type substrate) 4 Under therma equiibrium, the n-type poy gate is at a higher potentia than the p-type substrate φ p = kt q n N a φ n poy,n + = kt i q n N d,poy n 550m i No current can fow because of the insuator but this potentia difference is accompanied with an eectric fied Fieds terminate on charge! University of Caifornia, Berkeey

5 Fieds and Charge at Equiibrium Prof. Rikky Muer + + B X d 0 Body (p-type substrate) E 5 At equiibrium there is an eectric fied from the gate to the body Need a positive charge on the gate, negative charge in substrate Since body is p-type, negative charges in the body come from a depetion region University of Caifornia, Berkeey

6 Prof. Rikky Muer Fat Band otage, GB = FB FB < 0 + Q ( = ) = 0 G GB FB Body (p-type substrate) 6 If we appy a bias, we can compensate for this buit-in potentia = ( φ φ ) FB In this case the charge on the gate goes to zero and the depetion region disappears In soid-state physics ingo, the energy bands are fat under this condition n + p University of Caifornia, Berkeey

7 Prof. Rikky Muer Fat Band otage, GB = FB 7 University of Caifornia, Berkeey

8 Prof. Rikky Muer Accumuation, GB < FB Q = C ( ) G GB FB GB < FB Q B = Q G Body (p-type substrate) If we further decrease the potentia beyond the fat-band condition, we essentiay have a parae pate capacitor Penty of hoes and eectrons are avaiabe to charge up the pates Negative bias attracts hoes under gate 8 University of Caifornia, Berkeey

9 Prof. Rikky Muer Accumuation, GB < FB 9 University of Caifornia, Berkeey

10 Prof. Rikky Muer Depetion, GB > FB GB > FB Body (p-type substrate) Q ( ) = Q G GB B Q = qn X ( ) B a d GB Simiar to equiibrium, the potentia in the gate is higher than the body Body charge is made up of the depetion region ions Potentia drop across the body and depetion region 10 University of Caifornia, Berkeey

11 Prof. Rikky Muer Depetion, GB > FB 11 University of Caifornia, Berkeey

12 Prof. Rikky Muer Inversion, GB > T GB = T φ s Body (p-type substrate) 12 As we further increase the gate votage, eventuay the surface potentia increases to a point where the eectron density at the surface equas the background ion density qφs kt s i a n = ne = N φs = φp At this point, the depetion region stops growing and the extra charge is provided by the inversion charge at surface Inversion meaning that the surface is effectivey n-type University of Caifornia, Berkeey

13 Prof. Rikky Muer Inversion, GB > T 13 University of Caifornia, Berkeey

14 Threshod otage Prof. Rikky Muer The threshod votage is defined as the gate-body votage that causes the surface to change from p- type to n-type For this condition, the surface potentia has to equa the negative of the p-type potentia We can derive that this votage is equa to: 1 Tn = FB 2φp + 2 qεs Na( 2 φp) C 14 University of Caifornia, Berkeey

15 Prof. Rikky Muer Recap Accumuation: GB < FB Q = C ( ) G GB FB GB < FB + Q B = Q G Body (p-type substrate) Essentiay a parae pate capacitor Capacitance is determined by ide thickness 15 University of Caifornia, Berkeey

16 Prof. Rikky Muer Recap Depetion: FB < GB < T GB > + FB Q ( ) = Q G GB B Body (p-type substrate) Q = qn X ( ) B a d GB Positive charge on gate terminates on negative charges in depetion region Potentia drop across the ide and depetion region Charge has a square-root dependence on appied bias 16 University of Caifornia, Berkeey

17 Prof. Rikky Muer Recap Inversion: GB > T φ s GB = T Body (p-type substrate) qφs kt s = i = a n ne N 17 The surface potentia increases to a point where the eectron density at the surface equas the background ion density At this point, the depetion region stops growing and the extra charge is provided by the inversion charge (eectrons) at the surface University of Caifornia, Berkeey

18 Q- Curve for MOS Capacitor Prof. Rikky Muer Q G depetion Q B,max Q ( ) N GB FB Tn ( ) GB In accumuation, the charge is simpy proportiona to the appies gate-body bias In inversion, the same is true In depetion, the charge grows sower since the votage is appied over a depetion region 18 University of Caifornia, Berkeey

19 MOS C Curve Prof. Rikky Muer Q G C C C Q ( ) N GB Q B,max ( ) GB GB FB Tn FB Tn Sma-signa capacitance is sope of Q- curve Capacitance is constant in accumuation and inversion Capacitance in the depetion region is smaest Capacitance is non-inear in depetion 19 University of Caifornia, Berkeey

20 C- Curve Equivaent Circuits Prof. Rikky Muer Accumuation Depetion Inversion C C C dep C 20 ε s CdepC C Cdep = C Ctot = = = xdep Cdep + C Cdep ε s t C ε x dep In accumuation mode the capacitance is just due to the votage drop across t In depetion region, the votage drop is across the ide and the depetion region In inversion the incrementa charge comes from the inversion ayer (depetion region stops growing). University of Caifornia, Berkeey

21 Numerica Exampe Prof. Rikky Muer MOS Capacitor with p-type substrate: 16 3 t = 20nm = 5 10 cm Cacuate fat-band: N a = ( φ φ ) = (550 ( 402)) = 0.95 FB n + Cacuate threshod votage: p 13 ε F/cm C = = -6 t 2 10 cm 1 Tn = FB 2φp + 2 qεs Na( 2 φp) C Tn =.95 2( 0.4) + = 0.52 C 21 University of Caifornia, Berkeey

22 Num Exampe: Eectric Fied in Oxide Prof. Rikky Muer Appy a gate-to-body votage: GB = 2.5 < FB Device is in accumuation The entire votage drop is across the ide: E GB + φ + φ n p ( 0.4) = = = = 8 10 t t cm The charge in the substrate (body) consist of hoes: 22 Q = C ( ) = C/cm B GB FB 7 2 University of Caifornia, Berkeey

Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) Prof. Ali M. Niknejad Prof. Rikky Muller

Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) Prof. Ali M. Niknejad Prof. Rikky Muller EECS 105 Spring 2017, Modue 3 Meta Oxide Semiconductor Fied Effect Transistors (MOSFETs) Prof. Ai M. Niknejad Prof. Rikky Muer Department of EECS University of Caifornia, Berkeey Announcements Prof. Rikky

More information

Lecture 11: MOS Transistor

Lecture 11: MOS Transistor Lecture 11: MOS Transistor Prof. Niknejad Lecture Outline Review: MOS Capacitors Regions MOS Capacitors (3.8 3.9) CV Curve Threshold Voltage MOS Transistors (4.1 4.3): Overview Cross-section and layout

More information

Lecture 12: MOS Capacitors, transistors. Context

Lecture 12: MOS Capacitors, transistors. Context Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those

More information

EE105 - Fall 2006 Microelectronic Devices and Circuits

EE105 - Fall 2006 Microelectronic Devices and Circuits EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM

More information

EE105 - Fall 2005 Microelectronic Devices and Circuits

EE105 - Fall 2005 Microelectronic Devices and Circuits EE105 - Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture

More information

EE 560 MOS TRANSISTOR THEORY

EE 560 MOS TRANSISTOR THEORY 1 EE 560 MOS TRANSISTOR THEORY PART 1 TWO TERMINAL MOS STRUCTURE V G (GATE VOLTAGE) 2 GATE OXIDE SiO 2 SUBSTRATE p-type doped Si (N A = 10 15 to 10 16 cm -3 ) t ox V B (SUBSTRATE VOLTAGE) EQUILIBRIUM:

More information

Department of Electrical and Computer Engineering, Cornell University. ECE 3150: Microelectronics. Spring Due on March 01, 2018 at 7:00 PM

Department of Electrical and Computer Engineering, Cornell University. ECE 3150: Microelectronics. Spring Due on March 01, 2018 at 7:00 PM Department of Electrical and Computer Engineering, Cornell University ECE 3150: Microelectronics Spring 2018 Homework 4 Due on March 01, 2018 at 7:00 PM Suggested Readings: a) Lecture notes Important Note:

More information

FIELD-EFFECT TRANSISTORS

FIELD-EFFECT TRANSISTORS FIEL-EFFECT TRANSISTORS 1 Semiconductor review 2 The MOS capacitor 2 The enhancement-type N-MOS transistor 3 I-V characteristics of enhancement MOSFETS 4 The output characteristic of the MOSFET in saturation

More information

EE105 - Spring 2007 Microelectronic Devices and Circuits. Structure and Symbol of MOSFET. MOS Capacitor. Metal-Oxide-Semiconductor (MOS) Capacitor

EE105 - Spring 2007 Microelectronic Devices and Circuits. Structure and Symbol of MOSFET. MOS Capacitor. Metal-Oxide-Semiconductor (MOS) Capacitor EE105 - Spring 007 Microelectronic Device and ircuit Metal-Oide-Semiconductor (MOS) apacitor Lecture 4 MOS apacitor The MOS tructure can be thought of a a parallel-plate capacitor, with the top plate being

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor

More information

Lecture 7 PN Junction and MOS Electrostatics(IV) Metal Oxide Semiconductor Structure (contd.)

Lecture 7 PN Junction and MOS Electrostatics(IV) Metal Oxide Semiconductor Structure (contd.) Lecture 7 PN Junction and MOS Electrostatics(IV) Metal Oxide Semiconductor Structure (contd.) Outline 1. Overview of MOS electrostatics under bias 2. Depletion regime 3. Flatband 4. Accumulation regime

More information

Announcements. EE105 - Fall 2005 Microelectronic Devices and Circuits. Lecture Material. MOS CV Curve. MOSFET Cross Section

Announcements. EE105 - Fall 2005 Microelectronic Devices and Circuits. Lecture Material. MOS CV Curve. MOSFET Cross Section Announcements EE0 - Fall 00 Microelectronic evices and Circuits ecture 7 Homework, due today Homework due net week ab this week Reading: Chapter MO Transistor ecture Material ast lecture iode currents

More information

Lecture 6 PN Junction and MOS Electrostatics(III) Metal-Oxide-Semiconductor Structure

Lecture 6 PN Junction and MOS Electrostatics(III) Metal-Oxide-Semiconductor Structure Lecture 6 PN Junction and MOS Electrostatics(III) Metal-Oxide-Semiconductor Structure Outline 1. Introduction to MOS structure 2. Electrostatics of MOS in thermal equilibrium 3. Electrostatics of MOS with

More information

Interim Exam 1 5AIB0 Sensing, Computing, Actuating , Location AUD 11

Interim Exam 1 5AIB0 Sensing, Computing, Actuating , Location AUD 11 Interim Exam 1 5AIB0 Sensing, Computing, Actuating 3-5-2015, 14.00-15.00 Location AUD 11 Name: ID: This interim exam consists of 1 question for which you can score at most 30 points. The fina grade for

More information

Gauss Law. 2. Gauss s Law: connects charge and field 3. Applications of Gauss s Law

Gauss Law. 2. Gauss s Law: connects charge and field 3. Applications of Gauss s Law Gauss Law 1. Review on 1) Couomb s Law (charge and force) 2) Eectric Fied (fied and force) 2. Gauss s Law: connects charge and fied 3. Appications of Gauss s Law Couomb s Law and Eectric Fied Couomb s

More information

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE15 Spring 28 Lecture

More information

Parallel plate capacitor. Last time. Parallel plate capacitor. What is the potential difference? What is the capacitance? Quick Quiz "V = 1 C Q

Parallel plate capacitor. Last time. Parallel plate capacitor. What is the potential difference? What is the capacitance? Quick Quiz V = 1 C Q Last time r r r V=V o Potentia an eectric fie Capacitors "V = 1 C Q Parae pate capacitor Charge Q move from right conuctor to eft conuctor Each pate has size Length With = Area = A outer Pate surfaces

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 29, 2019 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2019 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 24, 2017 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2017 Khanna Lecture Outline! Semiconductor Physics " Band gaps "

More information

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET: Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)

More information

University of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA

University of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA University of Pennsylvania Department of Electrical Engineering ESE 570 Midterm Exam March 4, 03 FORMULAS AND DATA. PHYSICAL CONSTANTS: n i = intrinsic concentration undoped) silicon =.45 x 0 0 cm -3 @

More information

ECE321 Electronics I

ECE321 Electronics I EE31 Electronics I Lecture 8: MOSET Threshold Voltage and Parasitic apacitances Payman Zarkesh-Ha Office: EE Bldg. 3B Office hours: Tuesday :-3:PM or by appointment E-mail: payman@ece.unm.edu Slide: 1

More information

Demonstration of Ohm s Law Electromotive force (EMF), internal resistance and potential difference Power and Energy Applications of Ohm s Law

Demonstration of Ohm s Law Electromotive force (EMF), internal resistance and potential difference Power and Energy Applications of Ohm s Law Lesson 4 Demonstration of Ohm s Law Eectromotive force (EMF), interna resistance and potentia difference Power and Energy Appications of Ohm s Law esistors in Series and Parae Ces in series and Parae Kirchhoff

More information

Induction and Inductance

Induction and Inductance Induction and Inductance How we generate E by B, and the passive component inductor in a circuit. 1. A review of emf and the magnetic fux. 2. Faraday s Law of Induction 3. Lentz Law 4. Inductance and inductor

More information

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics t ti Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE105 Fall 2007

More information

EECS130 Integrated Circuit Devices

EECS130 Integrated Circuit Devices EECS130 Integrated Circuit Devices Professor Ali Javey 10/02/2007 MS Junctions, Lecture 2 MOS Cap, Lecture 1 Reading: finish chapter14, start chapter16 Announcements Professor Javey will hold his OH at

More information

Electrical Characteristics of MOS Devices

Electrical Characteristics of MOS Devices Electrical Characteristics of MOS Devices The MOS Capacitor Voltage components Accumulation, Depletion, Inversion Modes Effect of channel bias and substrate bias Effect of gate oide charges Threshold-voltage

More information

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring

More information

Chapter 26 - Capacitance

Chapter 26 - Capacitance Chapter 26 Capacitance Probem Set #5 ue: Ch 26 2, 3, 5, 7, 9, 5, 22, 26, 29, 6, 63, 64 The ieas of energy storage in fies can be carrie a step further by unerstaning the concept of "Capacitance." Lecture

More information

EECS130 Integrated Circuit Devices

EECS130 Integrated Circuit Devices EECS130 Integrated Circuit Devices Professor Ali Javey 9/18/2007 P Junctions Lecture 1 Reading: Chapter 5 Announcements For THIS WEEK OLY, Prof. Javey's office hours will be held on Tuesday, Sept 18 3:30-4:30

More information

Preamble. Flow and Fluid Velocity. In this section of my lectures we will be. To do this we will use as an analogy

Preamble. Flow and Fluid Velocity. In this section of my lectures we will be. To do this we will use as an analogy Preambe Resistance Physics, 8 th Edition Custom Edition Cutne & Johnson Chapter 20.3 Pages 602-605 In this section of my ectures we wi be deveoping the concept of resistance. To do this we wi use as an

More information

! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.

! CMOS Process Enhancements. ! Semiconductor Physics.  Band gaps.  Field Effects. ! MOS Physics.  Cut-off.  Depletion. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 3, 018 MOS Transistor Theory, MOS Model Lecture Outline! CMOS Process Enhancements! Semiconductor Physics " Band gaps " Field Effects!

More information

MOSFET: Introduction

MOSFET: Introduction E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major

More information

! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.

! CMOS Process Enhancements. ! Semiconductor Physics.  Band gaps.  Field Effects. ! MOS Physics.  Cut-off.  Depletion. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 9, 019 MOS Transistor Theory, MOS Model Lecture Outline CMOS Process Enhancements Semiconductor Physics Band gaps Field Effects

More information

(Refer Slide Time: 2:34) L C V

(Refer Slide Time: 2:34) L C V Microwave Integrated Circuits Professor Jayanta Mukherjee Department of Eectrica Engineering Indian Intitute of Technoogy Bombay Modue 1 Lecture No 2 Refection Coefficient, SWR, Smith Chart. Heo wecome

More information

Section 12: Intro to Devices

Section 12: Intro to Devices Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si

More information

RELUCTANCE The resistance of a material to the flow of charge (current) is determined for electric circuits by the equation

RELUCTANCE The resistance of a material to the flow of charge (current) is determined for electric circuits by the equation INTRODUCTION Magnetism pays an integra part in amost every eectrica device used today in industry, research, or the home. Generators, motors, transformers, circuit breakers, teevisions, computers, tape

More information

! MOS Capacitances. " Extrinsic. " Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications

! MOS Capacitances.  Extrinsic.  Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 7: February, 07 MOS SPICE Models, MOS Parasitic Details Lecture Outline! MOS Capacitances " Extrinsic " Intrinsic! Lumped Capacitance Model!

More information

EECS130 Integrated Circuit Devices

EECS130 Integrated Circuit Devices EECS130 Integrated Circuit Devices Professor Ali Javey 10/30/2007 MOSFETs Lecture 4 Reading: Chapter 17, 19 Announcements The next HW set is due on Thursday. Midterm 2 is next week!!!! Threshold and Subthreshold

More information

Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs

Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs EECS 142 Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs Prof. Ali M. Niknejad University of California, Berkeley Copyright c 2005 by Ali M. Niknejad A. M. Niknejad University of California,

More information

CHAPTER 5 MOS FIELD-EFFECT TRANSISTORS

CHAPTER 5 MOS FIELD-EFFECT TRANSISTORS CHAPTER 5 MOS FIELD-EFFECT TRANSISTORS 5.1 The MOS capacitor 5.2 The enhancement-type N-MOS transistor 5.3 I-V characteristics of enhancement mode MOSFETS 5.4 The PMOS transistor and CMOS technology 5.5

More information

ECE 305 Exam 5 SOLUTIONS: Spring 2015 April 17, 2015 Mark Lundstrom Purdue University

ECE 305 Exam 5 SOLUTIONS: Spring 2015 April 17, 2015 Mark Lundstrom Purdue University NAME: PUID: : ECE 305 Exam 5 SOLUTIONS: April 17, 2015 Mark Lundstrom Purdue University This is a closed book exam. You may use a calculator and the formula sheet at the end of this exam. Following the

More information

Lecture 7 - PN Junction and MOS Electrostatics (IV) Electrostatics of Metal-Oxide-Semiconductor Structure. September 29, 2005

Lecture 7 - PN Junction and MOS Electrostatics (IV) Electrostatics of Metal-Oxide-Semiconductor Structure. September 29, 2005 6.12 - Microelectronic Devices and Circuits - Fall 25 Lecture 7-1 Lecture 7 - PN Junction and MOS Electrostatics (IV) Electrostatics of Metal-Oide-Semiconductor Structure September 29, 25 Contents: 1.

More information

Chapter 2 MOS Transistor theory

Chapter 2 MOS Transistor theory Chapter MOS Transistor theory.1 Introduction An MOS transistor is a majority-carrier device, which the current a conductg channel between the source and the dra is modulated by a voltage applied to the

More information

MOS Transistor Theory

MOS Transistor Theory MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

More information

Semiconductor Integrated Process Design (MS 635)

Semiconductor Integrated Process Design (MS 635) Semiconductor Integrated Process Design (MS 635) Instructor: Prof. Keon Jae Lee - Office: 응용공학동 #4306, Tel: #3343 - Email: keonlee@kaist.ac.kr Lecture: (Tu, Th), 1:00-2:15 #2425 Office hour: Tues & Thur

More information

ESE 570 MOS TRANSISTOR THEORY Part 1. Kenneth R. Laker, University of Pennsylvania, updated 5Feb15

ESE 570 MOS TRANSISTOR THEORY Part 1. Kenneth R. Laker, University of Pennsylvania, updated 5Feb15 ESE 570 MOS TRANSISTOR THEORY Part 1 TwoTerminal MOS Structure 2 GATE Si Oxide interface n n Mass Action Law VB 2 Chemical Periodic Table Donors American Chemical Society (ACS) Acceptors Metalloids 3 Ideal

More information

ECEN474/704: (Analog) VLSI Circuit Design Spring 2018

ECEN474/704: (Analog) VLSI Circuit Design Spring 2018 ECEN474/704: (Analog) SI Circuit Design Spring 2018 ecture 2: MOS ransistor Modeling Sam Palermo Analog & Mixed-Signal Center exas A&M University Announcements If you haven t already, turn in your 0.18um

More information

ECE 340 Lecture 39 : MOS Capacitor II

ECE 340 Lecture 39 : MOS Capacitor II ECE 340 Lecture 39 : MOS Capacitor II Class Outline: Effects of Real Surfaces Threshold Voltage MOS Capacitance-Voltage Analysis Things you should know when you leave Key Questions What are the effects

More information

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: MOSFET N-Type, P-Type. Semiconductor Physics.

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: MOSFET N-Type, P-Type. Semiconductor Physics. ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 24, 217 MOS Transistor Theory, MOS Model Lecture Outline! Semiconductor Physics " Band gaps " Field Effects! MOS Physics " Cutoff

More information

MOS Transistor Properties Review

MOS Transistor Properties Review MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO

More information

ELEC 3908, Physical Electronics, Lecture 23. The MOSFET Square Law Model

ELEC 3908, Physical Electronics, Lecture 23. The MOSFET Square Law Model ELEC 3908, Physical Electronics, Lecture 23 The MOSFET Square Law Model Lecture Outline As with the diode and bipolar, have looked at basic structure of the MOSFET and now turn to derivation of a current

More information

Chapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

Chapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Chapter 2 CMOS Transistor Theory Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction MOS Device Design Equation Pass Transistor Jin-Fu Li, EE,

More information

Lecture 04 Review of MOSFET

Lecture 04 Review of MOSFET ECE 541/ME 541 Microelectronic Fabrication Techniques Lecture 04 Review of MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu) What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D

More information

Sure Shot 2016 Electric Current By M K Ezaz

Sure Shot 2016 Electric Current By M K Ezaz Sure Shot 06 Eectric Current B M K Ezaz. A 0 V batter of negigibe interna resistance is connected across a 00 V batter and a resistance of 38 Ω. Find the vaue of the current in circuit. () E 00 0 A: I

More information

P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions

P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions P. R. Nelson 1 ECE418 - VLSI Midterm Exam Solutions 1. (8 points) Draw the cross-section view for A-A. The cross-section view is as shown below.. ( points) Can you tell which of the metal1 regions is the

More information

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. EECS 130 Professor Ali Javey Fall 2006

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. EECS 130 Professor Ali Javey Fall 2006 UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EECS 130 Professor Ali Javey Fall 2006 Midterm 2 Name: SID: Closed book. Two sheets of notes are

More information

The Three terminal MOS structure. Semiconductor Devices: Operation and Modeling 115

The Three terminal MOS structure. Semiconductor Devices: Operation and Modeling 115 The Three terminal MOS structure 115 Introduction MOS transistor two terminal MOS with another two opposite terminal (back to back of inversion layer). Theses two new terminal make the current flow if

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 5: January 25, 2018 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation!

More information

Section 12: Intro to Devices

Section 12: Intro to Devices Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals Bond Model of Electrons and Holes Si Si Si Si Si Si Si Si Si Silicon

More information

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing

More information

Dept. of Materials Science and Engineering. Electrical Properties Of Materials

Dept. of Materials Science and Engineering. Electrical Properties Of Materials Problem Set 12 Solutions See handout "Part 4: Heterojunctions MOS Devices" (slides 9-18) Using the Boise State Energy Band Diagram program, build the following structure: Gate material: 5nm p + -Poly Si

More information

Related Topics Maxwell s equations, electrical eddy field, magnetic field of coils, coil, magnetic flux, induced voltage

Related Topics Maxwell s equations, electrical eddy field, magnetic field of coils, coil, magnetic flux, induced voltage Magnetic induction TEP Reated Topics Maxwe s equations, eectrica eddy fied, magnetic fied of cois, coi, magnetic fux, induced votage Principe A magnetic fied of variabe frequency and varying strength is

More information

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EE 105: Microelectronic Devices and Circuits Spring 2008 MIDTERM EXAMINATION #1 Time

More information

MOS Transistor I-V Characteristics and Parasitics

MOS Transistor I-V Characteristics and Parasitics ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes

More information

SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University

SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University NAME: PUID: SECTION: Circle one: Alam Lundstrom ECE 305 Exam 5 SOLUTIONS: April 18, 2016 M A Alam and MS Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula

More information

EE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing

EE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing EE115C Winter 2017 Digital Electronic Circuits Lecture 3: MOS RC Model, CMOS Manufacturing Agenda MOS Transistor: RC Model (pp. 104-113) S R on D CMOS Manufacturing Process (pp. 36-46) S S C GS G G C GD

More information

Homework Assignment No. 1 - Solutions

Homework Assignment No. 1 - Solutions Homework Assignment o. 1 - Solutions Problem P1.7 This question is as easy as it looks, no tricks here. a. The delay from a to b is simply the delay of an inverter times the number of inverters which would

More information

MOS Capacitor MOSFET Devices. MOSFET s. INEL Solid State Electronics. Manuel Toledo Quiñones. ECE Dept. UPRM.

MOS Capacitor MOSFET Devices. MOSFET s. INEL Solid State Electronics. Manuel Toledo Quiñones. ECE Dept. UPRM. INEL 6055 - Solid State Electronics ECE Dept. UPRM 20th March 2006 Definitions MOS Capacitor Isolated Metal, SiO 2, Si Threshold Voltage qφ m metal d vacuum level SiO qχ 2 E g /2 qφ F E C E i E F E v qφ

More information

Classification of Solids

Classification of Solids Classification of Solids Classification by conductivity, which is related to the band structure: (Filled bands are shown dark; D(E) = Density of states) Class Electron Density Density of States D(E) Examples

More information

Check course home page periodically for announcements. Homework 2 is due TODAY by 5pm In 240 Cory

Check course home page periodically for announcements. Homework 2 is due TODAY by 5pm In 240 Cory EE141 Fall 005 Lecture 6 MOS Capacitances, Propagation elay Important! Check course home page periodically for announcements Homework is due TOAY by 5pm In 40 Cory Homework 3 will be posted TOAY ue Thursday

More information

ECE-305: Fall 2017 Metal Oxide Semiconductor Devices

ECE-305: Fall 2017 Metal Oxide Semiconductor Devices C-305: Fall 2017 Metal Oxide Semiconductor Devices Pierret, Semiconductor Device Fundamentals (SDF) Chapters 15+16 (pp. 525-530, 563-599) Professor Peter Bermel lectrical and Computer ngineering Purdue

More information

Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor

Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor Triode Working FET Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor The characteristics of energy bands as a function of applied voltage. Surface inversion. The expression for the

More information

Lecture 3: CMOS Transistor Theory

Lecture 3: CMOS Transistor Theory Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors

More information

Introduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline

Introduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline Introduction to MOS VLSI Design hapter : MOS Transistor Theory copyright@david Harris, 004 Updated by Li hen, 010 Outline Introduction MOS apacitor nmos IV haracteristics pmos IV haracteristics Gate and

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 7: February 4, 2016 MOS SPICE Models, MOS Parasitic Details Lecture Outline! MOS Capacitances " Extrinsic " Intrinsic! Lumped Capacitance

More information

The Devices: MOS Transistors

The Devices: MOS Transistors The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor

More information

Extensive reading materials on reserve, including

Extensive reading materials on reserve, including Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si

More information

6.012 Electronic Devices and Circuits Spring 2005

6.012 Electronic Devices and Circuits Spring 2005 6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):

More information

Midterm I - Solutions

Midterm I - Solutions UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EECS 130 Spring 2008 Professor Chenming Hu Midterm I - Solutions Name: SID: Grad/Undergrad: Closed

More information

VLSI Design The MOS Transistor

VLSI Design The MOS Transistor VLSI Design The MOS Transistor Frank Sill Torres Universidade Federal de Minas Gerais (UFMG), Brazil VLSI Design: CMOS Technology 1 Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V

More information

ECS 40, Fall 2008 Prof. Chang-Hasnain Test #3 Version A

ECS 40, Fall 2008 Prof. Chang-Hasnain Test #3 Version A ECS 40, Fall 2008 Prof. ChangHasnain Test #3 Version A 10:10 am 11:00 am, Wednesday December 3, 2008 Total Time Allotted: 50 minutes Total Points: 100 1. This is a closed book exam. However, you are allowed

More information

an introduction to Semiconductor Devices

an introduction to Semiconductor Devices an introduction to Semiconductor Devices Donald A. Neamen Chapter 6 Fundamentals of the Metal-Oxide-Semiconductor Field-Effect Transistor Introduction: Chapter 6 1. MOSFET Structure 2. MOS Capacitor -

More information

Microelectronics Part 1: Main CMOS circuits design rules

Microelectronics Part 1: Main CMOS circuits design rules GBM8320 Dispositifs Médicaux telligents Microelectronics Part 1: Main CMOS circuits design rules Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim! http://www.cours.polymtl.ca/gbm8320/! med-amine.miled@polymtl.ca!

More information

Lecture 4: CMOS Transistor Theory

Lecture 4: CMOS Transistor Theory Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q

More information

6.012 Electronic Devices and Circuits

6.012 Electronic Devices and Circuits Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to

More information

Lecture 22 - The Si surface and the Metal-Oxide-Semiconductor Structure (cont.) April 2, 2007

Lecture 22 - The Si surface and the Metal-Oxide-Semiconductor Structure (cont.) April 2, 2007 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 22-1 Lecture 22 - The Si surface and the Metal-Oxide-Semiconductor Structure (cont.) April 2, 2007 Contents: 1. Ideal MOS structure

More information

Lecture 7 MOS Capacitor

Lecture 7 MOS Capacitor EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 7 MOS Capacitor Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ 07030

More information

PN Junction and MOS structure

PN Junction and MOS structure PN Junction and MOS structure Basic electrostatic equations We will use simple one-dimensional electrostatic equations to develop insight and basic understanding of how semiconductor devices operate Gauss's

More information

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EECS 40 Spring 2000 Introduction to Microelectronic Devices Prof. King MIDTERM EXAMINATION

More information

1 Name: Student number: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND. Fall :00-11:00

1 Name: Student number: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND. Fall :00-11:00 1 Name: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND Final Exam Physics 3000 December 11, 2012 Fall 2012 9:00-11:00 INSTRUCTIONS: 1. Answer all seven (7) questions.

More information

MOS CAPACITOR AND MOSFET

MOS CAPACITOR AND MOSFET EE336 Semiconductor Devices 1 MOS CAPACITOR AND MOSFET Dr. Mohammed M. Farag Ideal MOS Capacitor Semiconductor Devices Physics and Technology Chapter 5 EE336 Semiconductor Devices 2 MOS Capacitor Structure

More information

Lecture 6 - PN Junction and MOS Electrostatics (III) Electrostatics of pn Junction under Bias February 27, 2001

Lecture 6 - PN Junction and MOS Electrostatics (III) Electrostatics of pn Junction under Bias February 27, 2001 6.012 Microelectronic Devices and Circuits Spring 2001 Lecture 61 Lecture 6 PN Junction and MOS Electrostatics (III) Electrostatics of pn Junction under Bias February 27, 2001 Contents: 1. electrostatics

More information

ECE-305: Fall 2017 MOS Capacitors and Transistors

ECE-305: Fall 2017 MOS Capacitors and Transistors ECE-305: Fall 2017 MOS Capacitors and Transistors Pierret, Semiconductor Device Fundamentals (SDF) Chapters 15+16 (pp. 525-530, 563-599) Professor Peter Bermel Electrical and Computer Engineering Purdue

More information

CMOS Devices. PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors

CMOS Devices. PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors CMOS Devices PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors PN Junctions Diffusion causes depletion region D.R. is insulator and establishes barrier

More information

Week 3, Lectures 6-8, Jan 29 Feb 2, 2001

Week 3, Lectures 6-8, Jan 29 Feb 2, 2001 Week 3, Lectures 6-8, Jan 29 Feb 2, 2001 EECS 105 Microelectronics Devices and Circuits, Spring 2001 Andrew R. Neureuther Topics: M: Charge density, electric field, and potential; W: Capacitance of pn

More information

EEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 116 Lecture #3: CMOS Inverters MOS Scaling Rajeevan Amirtharajah University of California, Davis Jeff Parhurst Intel Corporation Outline Review: Inverter Transfer Characteristics Lecture 3: Noise Margins,

More information

The Gradual Channel Approximation for the MOSFET:

The Gradual Channel Approximation for the MOSFET: 6.01 - Electronic Devices and Circuits Fall 003 The Gradual Channel Approximation for the MOSFET: We are modeling the terminal characteristics of a MOSFET and thus want i D (v DS, v GS, v BS ), i B (v

More information

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS ) ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets

More information

Microelectronic Devices and Circuits Lecture 9 - MOS Capacitors I - Outline Announcements Problem set 5 -

Microelectronic Devices and Circuits Lecture 9 - MOS Capacitors I - Outline Announcements Problem set 5 - 6.012 - Microelectronic Devices and Circuits Lecture 9 - MOS Capacitors I - Outline Announcements Problem set 5 - Posted on Stellar. Due net Wednesday. Qualitative description - MOS in thermal equilibrium

More information