Digital Circuit Design

Size: px
Start display at page:

Download "Digital Circuit Design"

Transcription

1 Introdution Digitl Ciruit Design Eri Hehner University of Toronto The word iruit is relted to the word irle. It ws used to desrie losed eletril pth tht goes from one end of n eletril ttery, through wires nd mhines, doing work on the wy, nd returning to the other end of the ttery. Tht's why there re two wires in the ord of n eletril devie (suh s lmp or omputer): eletriity goes from its soure to the devie in one wire, nd returns from the devie k to the soure in the other wire, ompleting the irle or iruit. These dys, we use the word iruit for ny sort of eletril or eletroni devie. The word digitl is relted to the word digit, whih mens finger. Sine fingers re used for ounting, digit lso mens symol used in the representtion of numer. A digitl iruit is n eletroni devie tht hs disrete sttes, like the disply of digitl lok. You n ount the numer of different possile sttes of the devie. This is in ontrst to the old, round loks tht hd hnds tht move; they hve ontinuous sttes. This short ourse is out the design of digitl iruits, inluding ut not limited to omputers. In the 1940s when omputers were new, they were progrmmed in mhine lnguge, whih is seuene of 0s nd 1s, using physil swithes tht were off or on. In the 1950s, progrmmers relized tht there is etter wy. They invented wht they lled high-level progrmming. They used three-letter mnemonis for the mhine instrutions, nd identifiers (nmes) for the ddresses. Tody, we ll tht ssemly lnguge. At the end of the 1950s, progrmmers invented wht we tody ll high-level lnguges. Progrms now re not just mnemoni versions of mhine instrutions. They desrie the dt strutures nd lgorithms of the omputtion, rther thn the mhine instrutions tht perform the omputtion. Digitl iruit design is going through the sme evolution, ut muh more slowly. For mny yers, iruits hve een designed y hoosing the iruit elements (gtes, swithes, flipflops), onneting them with wires to hieve the right funtionlity, nd rrnging the iruit elements nd wires in the est sptil lyout. In the 1980s nd 1990s, iruit designers invented wht they lled high-level pproh to iruit design. They used mnemonis for the iruit elements, nd identifiers (nmes) for the wires, in iruit-design lnguge. The two most populr iruit-design lnguges re VHDL nd Verilog. These lnguges re like ssemly lnguges in the sense tht progrm diretly desries iruit, just like n ssemly-lnguge progrm diretly desries mhine-lnguge progrm. In this short ourse, we tke the next step. We use modern high-level progrmming lnguge (C++ or Jv or Python or...) to write progrms for the lgorithms we wnt to ompute, not to desrie the iruits to ompute the lgorithms. Then we ompile the progrms to produe iruits to ompute the lgorithms. For exmple, you write progrm to ompute the numer of times given word ours in given text, nd ompile the progrm to produe iruit tht omputes the numer of times given word ours in given text. You n write rowser progrm, nd ompile it to produe rowser iruit. You n write progrm to interpret mhine lnguge, nd ompile it to produe omputer with tht mhine lnguge. But efore we get to the progrms, we strt t the very eginning of iruit design: we strt with how iruit elements re uilt from elementry prtiles. When we re done, you will know how iruits re designed nd how they work, from the elementry prtiles right up to the most omplex iruits in existene. Free online letures for this short ourse n e found t

2 1 Digitl Ciruit Design Physil Bse Mtter is mde of moleules; moleules re mde of toms; toms re mde of protons, neutrons, nd eletrons. Protons re positively hrged, nd eletrons re eully negtively hrged. A neutron, whih onsists of proton nd n eletron, is neutrl, or unhrged. The protons nd neutrons re the nuleus, t the enter, of n tom. Eletrons surround the nuleus in shells, or lyers. The outermost shell of eletrons determines the eletril hrteristis of the mteril. If the eletrons in the outer shell re strongly ound to the tom, the mteril is lled resistor. Silion, whih is wht glss nd ermis re mde of, is resistor. If the eletrons in the outer shell re wekly ound to the tom, the mteril is lled ondutor. Copper is ondutor. Different mterils oupy different ples long the spetrum etween very onduting nd very resisting. Towrd the onduting end of the spetrum, eletrons n move esily from tom to tom. Towrd the resisting end, eletrons n still move from tom to tom, ut it tkes more energy. Here re the eletril symols for ondutor (the line on the left) nd resistor (the zig-zg on the right; it's just symol, not the shpe of the resistor). A flow of eletrons through the mteril in one diretion is lled eletriity, or eletri urrent. In solid, the nuleus nd eletrons in the inner shells sty still, nd do not flow. In liuid or gs, toms n flow, so eletriity is omintion of free eletrons flowing one wy nd toms with more protons thn eletrons flowing the other wy. But our iruits re mde of solid mteril, so eletriity is just eletron flow. VLSI (Very Lrge Sle Integrtion) is the wy digitl iruits re urrently uilt. First, silion is heted so hot tht it melts nd eomes liuid. Then it is poured onto len flt surfe in thin pnke-size irles, lled wfers. The silion wfers ool nd solidify into rystl struture. The room where this tkes ple must e dust-free (it is lled lenroom ), nd insulted from ll noise nd virtions, in order to get good rystl struture. Here is piture of silion rystl struture Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si The letters Si stnd for the nuleus of the silion toms. The dots re the eletrons in the outer shell of these toms. There re 4 eletrons in the outer shell of eh silion tom, ut s you n see, these eletrons re shred etween pirs of toms. You n't sy whih tom n eletron elongs to; you n sy only tht it elongs to pir of neighoring toms. The piture is indeute in two wys. First, rystl wfer is 3-dimensionl, not 2-dimensionl s shown; the toms re rrnged in regulr tetrhedron pttern. Seond, n eletron is not dot sitting in speifi ple. Wht the piture is intended to onvey is tht the silion rystl is regulr

3 Digitl Ciruit Design 2 struture of toms, eh tom hs 4 nerest neighors, nd eh eletron in n outer shell is strongly ound to pir of toms. A silion rystl struture is resistor. The next phse in VLSI frition is lled doping. Some speilly seleted silion toms re hemilly repled y phosphorus toms, whih hve 5 eletrons in the outer shell. Other speilly seleted silion toms re repled y oron toms, whih hve 3 eletrons in the outer shell. Here is piture (with the sme indeuies s efore): Si Si Si Si Si Si Si P. P B B Si Si P. P B B Si Si Si Si Si Si Si The letter P stnds for phosphorus nuleus, nd B stnds for oron nuleus. The extr eletron of phosphorus tom is ttrted to the nuleus of the tom, ut it hs no ple in the rystl struture; so it is wekly ound to its tom, nd esily dislodged. A region tht is doped with phosphorus is sid to e negtively doped. Eh oron tom mkes ple in the rystl struture for n eletron tht isn't there; tht ple is lled hole. A region doped with oron is sid to e positively doped. Along the oundry etween the negtive nd positive doping, some of the extr, wekly ound eletrons on the negtive side drift wy from their toms, nd some of them drift over to the positive side, where there re ples for them in the rystl struture. But they re still wekly ound there euse there is no orresponding proton in the oron nuleus. Eletrons ontinue to drift round on oth sides of the oundry, ut they soon reh n euilirium of density on the two sides. Silion with positively nd negtively doped regions is lled semiondutor (it ould just s well hve een lled semiresistor ). The next phse in VLSI frition ots the semiondutor surfe with n oxide resistor, nd then metl wire ondutors re pinted on the oxide surfe, poking through the oxide into the semiondutor t just the right ples. A diode is pir of negtively nd positively doped regions eside eh other, with wire poking into eh region. If the wire in the negtively doped region is soure of eletrons, nd the wire in the positively doped region is destintion for eletrons (or we ould sy soure of holes, or ples for eletrons to go), here's wht hppens. Eletrons tht drift ross from the negtively doped region to the positively doped region ontinue into the wire tht is n eletron destintion, nd they get repled from the wire tht is n eletron soure into the negtive region. The replement eletrons ross the oundry, nd then go to the destintion, nd so on. A urrent flows through the diode until either the soure of eletrons is depleted, or the soure of holes is depleted (the holes re filled up). Now, suppose the wire in the negtively doped region is destintion for eletrons. As efore, some eletrons from the negtively doped region ross the oundry into the positively doped region, ut they do not get repled in the negtively doped region, so nothing more hppens; there is no urrent. Similrly if the wire in the positively doped region is soure for

4 3 Digitl Ciruit Design eletrons, the eletrons tht ross the oundry from the negtively doped region into the positively doped region hve no further ple to go, so there is no urrent. A diode is one-wy gte for urrent. A destintion for eletrons is lled positive voltge or high voltge or power, nd denoted. A soure of eletrons is lled negtive voltge or low voltge or ground, nd denoted. In typil digitl iruit tody, the differene is out 5 volts. Voltge is reltive term; we ould ll the nd voltges 5 volts nd 0 volts, or we ould ll them 3 volts nd 2 volts, or ny other two voltges tht differ y 5. Eletrons flow from to. Here is series of pitures of eletrons flowing from left to right. First, suppose we hve where eh is n eletron, nd is hole. Then suppose the eletron to the left of the hole moves into the hole. Then gin the eletron to the left of the hole moves into the hole. As eletrons flow from left to right, the hole flows from right to left. Now suppose there re lots of eletrons nd holes, rndomly pled. When there's n eletron to the left of hole, the eletron moves into the hole. Also, the t the left end fills the hole t the left end, nd the eletron t the right end moves into the t the right end. Eletrons flow from to, nd holes flow from to. Some people sy tht eletriity flows from to ; they re tlking out the flow of holes. A diode llows eletriity to flow in one diretion only. Another wy to sy the sme thing is tht diode supports voltge differene in one diretion only. It supports the voltge differene when it does not llow the urrent to flow. When it does llow the urrent to flow, either the eletron soure gets depleted or the holes fill up, nd the voltges eome the sme. The eletril symol for diode is The horizontl lines t the left nd right ends re the wires into the positively (on the left) nd negtively (on the right) doped regions. The tringle nd vertil line re not shped like the doped regions; they re just symol. Eletrons n flow from right to left, or to sy the sme thing differently, holes n flow from left to right. The left end n e nd the right end n e (no urrent), or oth ends n e the sme (no urrent). If the left end is nd the right end is, urrent flows until oth ends re the sme; tht diretion of voltge differene doesn't lst long. A trnsistor is three doped regions in row, either positive-negtive-positive, or negtivepositive-negtive, with wire in eh region. The middle wire, lled the se, n e or, nd tht determines whether the pth etween the end wires, lled the olletor nd the emitter, is onduting or nononduting. Its eletril symol is There re mny vritions in the wy VLSI is produed nd in the wy it works, nd mny detils tht re not presented here. This short ourse is not intended to e out VLSI frition; we hve presented just enough so tht you n see how iruits, inluding omputers, re uilt nd how they work.

5 Digitl Ciruit Design 4 Wter Ciruits There is lose nlogy etween wter nd eletriity. The flow of eletriity is like the flow of wter. A power soure or ttery is like pump tht pumps wter uphill. Voltge is like height differene of wter flowing downhill. A ondutor is like river ed or wide pipe. A resistor is like nrrow pipe or pipe with kink in it. A diode is like one-wy vlve. And trnsistor is like siphon or swith. Atully, it's more thn n nlogy: flling wter n e used to generte eletriity, nd eletriity n e used to pump wter uphill. Eletriity nd wter flow re interonvertile. Binry Astrtion Digitl iruit designers use only two voltge levels, whih we ll nd, typilly 5 volts prt. They pretend tht the voltge level t ny point in digitl iruit is one of those two levels. Over time, the voltge level t tht point my hnge, ut, ording to digitl iruit designers, it is lwys one of those two levels. Tht is the inry strtion. Here is piture of the voltge level t point in digitl iruit, hnging over time, ording to digitl iruit designers. Time inreses from left to right in the piture, nd the voltge goes up nd down. A seuene of hnges from to to is lled pulse. This piture shows two pulses. Wht relly hppens is more like this. Eletril engineers do their est, nd they do mzingly well, to mke the voltge levels e the wy digitl iruit designers wnt them to e: nie nd sure. Tht's so iruit designers n use simple inry lger in their designs, rther thn hving to del with omplited ontinuous voltge hnges. Gtes A simple iruit using the inry strtion is lled gte. The first gte we present is the or gte. It hs two inputs nd, nd one output. If either input or input or oth re, output is. If oth inputs re, the output is. We n uild n or gte from two diodes nd resistor. = ( or )

6 5 Digitl Ciruit Design A voltge is the sme ll long wire, so the voltge t input is the voltge t the left side of the top diode. Similrly the voltge t input is the voltge t the left side of the ottom diode. The wire to the right of the top diode is onneted to the wire to the right of the ottom diode, nd to the output ; tht's ll one wire, so the voltge to the right of the two diodes nd t the output must e the sme. Suppose the inputs nd re oth. Then the output hs to e euse the diodes nnot mintin the voltge differene with on the left nd on the right. If is nd is, hs to e euse we n't hve ross the diode, ut we n hve ross the diode. Similrly if is nd is, hs to e. Now suppose oth nd re. The diodes llow the output to e either or. If is, there is voltge differene ross the resistor, so there will e n eletron flow from the eletron soure mrked through the resistor to until is. (Tht tkes out seonds, whih is slower thn through ondutor, ut still superfst for humns.) If is, there is no voltge differene ross the resistor, nd so no eletron flow through the resistor. The wter nlogy my e helpful for understnding the opertion of n or gte. Sine eletril engineers like to put t the top nd t the ottom of piture, s in the or gte ove, nd sine wter flows downhill, we'll mke the flow of wter nlogous to the flow of holes. Imgine tht wter is pumped into the pipes t the nd inputs. The diodes re onewy gtes tht llow the wter to pss through to pipe. The resistor is pipe with kink in it, so wter goes through the resistor pipe slowly, dripping out the ottom. Wter tht drips out the resistor is replenished from the soures t nd, so pipe stys full of wter. If we remove the soure of wter t, nd let pipe drin empty, pipe will remin full; ny wter dripping out the resistor pipe is replenished from. It is possile for to e full nd to e empty euse the diode does not llow wter to flow from to. Now suppose we lso remove the soure of wter t, nd let pipe drin empty too. Pipe loses wter though the resistor until it is empty; it is not replenished from or. The previous piture is n eletril piture, showing wht relly hppens to the voltge levels. After we mke the inry strtion, the iruit design symol of n or gte is: = ( or ) An or gte n hve more thn two inputs. The output is if one or more inputs re, nd if ll inputs re. The implementtion uses one diode per input. The next gte we present is the nd gte. It hs two inputs nd, nd one output. If oth input nd input re, output is. If either or or oth re, the output is. We n uild n nd gte from two diodes nd resistor. = ( nd ) Suppose the inputs nd re oth. The diodes llow the output to e either or. If is, there is voltge differene ross the resistor, so there will e n eletron flow from through the resistor to the eletron sink mrked until is. If is, there is no voltge differene ross the resistor, nd so no eletron flow through the resistor. If either or oth of the inputs eomes, then eletrons flow from those input(s) to until is.

7 Digitl Ciruit Design 6 Eletrons will then flow from (slowly) through the resistor to, ut they re immeditely replenished from the input(s) tht re. In the wter nlogy, if wter is pumped into the nd pipes, it fills those pipes, ut hs nowhere to go sine it is stopped y the diodes, whih re one-wy gtes the wrong wy. So wter drips through the resistor until is full. If either or oth of nd is emptied, the wter in drins out through nd/or (whihever is empty). Wter ontinues to drip into from the resistor, ut it is immeditely drined out through nd/or, nd so remins empty. The inry strtion piture of n nd gte is: = ( nd ) An nd gte n hve more thn two inputs. The output is if ll inputs re, nd if one or more inputs re. The implementtion uses one diode per input. The simplest gte is the not gte, with one input nd one output. If the input is, the output is ; if the input is, the output is. The output is not wht the input is. It n e uilt from resistor nd trnsistor: = not When input is, the pth etween nd is onduting. Sine the voltge is the sme ll long onduting pth, the output is. Some of the eletrons t will move through the resistor to, ut they re immeditely repled from, nd the voltge t stys. When input is, the pth etween nd is not onduting. If is, there is voltge differene ross the resistor, so there will e (slow seonds) eletron flow from through the resistor to the eletron destintion until is. After we mke the inry strtion, the iruit design symol of not gte is irle: = not The lst gte we present is the dely. Its iruit design symol looks like this: = dely If the input to dely is represented y voltge versus time digrm, then the output dely is the sme digrm ut shifted to the right y the mount of the dely. dely

8 7 Digitl Ciruit Design A dely n e uilt y putting n even numer of not gtes in seuene. For more dely use more not gtes; for less dely use fewer not gtes. Gtes n e omined. For exmple, dely followed y not looks like this: = not dely Even if the input to digitl iruit strts off right on the nd voltge levels, hnging levels with eutifully sure hnges, fter going through few nd nd or gtes, the signl eomes degrded; the hnges re less sure nd the levels my not e extly nd. Fortuntely, not gte improves the signl in ddition to negting it. The output of not gte is right on or even if the input ws little off. A dely gte, whih is mde from not gtes, lso improves the signl. There re 4 different gtes with one inry input nd one inry output. Two of them do not py ttention to their input, giving onstnt output. They re represented y nd. One of them is the identity funtion, whose output is lwys the sme s the input. If the output is essentilly instnt, the identity funtion is represented y wire. If the output is delyed from the input, the identity funtion is represented y the dely gte. And finlly there is the not gte, whose output is lwys the opposite of the input. There re 16 different gtes with 2 inry inputs nd 1 inry output. Six of them do not py ttention to oth inputs, so they re of no interest. Two of them re the nd nd or gtes, whih we hve presented. The other 8 re useful, nd thorough presenttion of inry lger should present them. But we stop here. Binry lger is very useful for iruit design, nd if you wnt to red out it, you might try from Boolen Alger to Unified Alger nd lso Unified Alger. Informtion Flow We hve tlked out eletron flow, nd we hve tlked out hole flow, whih is the opposite diretion to eletron flow. We hve tlked out wter flow, whih we used s n nlogy to hole flow. We ould just s well use wter flow s n nlogy to eletron flow if we drw the pitures the other wy up, with t the top nd t the ottom. Informtion flow is the diretion from inputs to outputs. It is not relted in ny wy to the diretion of eletrons, holes, or wter; it my hppen to e the sme diretion, or it my hppen to e the opposite diretion. A wire is n input if we hoose its voltge, hoosing either or s we wish. A wire is n output if we mesure its voltge. We tend to drw inputs on the left side nd outputs on the right side, ut tht is not wht mkes them inputs nd outputs, nd sometimes tht's not the onvenient wy to drw them. At the eletril level, wires n e joined together, mking single wire oming nd going in vrious diretions, ll with the sme voltge. We hve seen this in the eletril pitures of the or gte nd the nd gte. It is possile for n informtion pth to split into two or more pths, s in this piture, showing the diretion of informtion flow y rrows. We n hoose or for input, nd then outputs nd will oth hve the sme vlue s. But it is not possile for two informtion pths to join into one. We nnot hve

9 Digitl Ciruit Design 8 If we hoose different vlues for inputs nd, then output is in the impossile position of hving to e oth nd. The only wy to join two informtion pths is to use gte. When we use n nd gte or n or gte, the gte sys how the output is determined y the inputs. We sometimes need to show wires rossing eh other, s in this piture: Wherever wires ross, it mens tht they re not onneted to eh other. We now leve the eletril level ehind; we mke the inry strtion. We stop tlking out voltges, nd we tlk only out inry vlues nd. We stop tlking out eletrons nd holes, nd tlk only out informtion flow. We stop tlking out wires, nd tlk insted out informtion pths, or just pths. The si unit of informtion is inry vlue, whih is lso lled it. Multiplexer nd Demultiplexer Eh iruit hs two pitures. One piture is ox, with inputs pointing to it, nd outputs pointing wy from it, nd in the ox there re words or symols to identify the funtion of the iruit. The other piture shows wht's in the ox, so we n see how the iruit is uilt. The first iruit we present is the multiplexer. x x y z if then else It hs inputs x, y, nd z, nd output. If x= then =y. If x= then =z. To see tht the nd, or, nd not gtes on the right re orret implementtion, it is neessry to look t 8 ses. The inputs x y z n e,,,,,,, nd. You should hek eh of these ses to see tht the output is orret. The next iruit is the demultiplexer. x x y z y if then else r y r It hs inputs x nd y, nd outputs nd r. If x= then =y nd r=. If x= then r=y nd =. To see tht the nd nd not gtes on the right re orret implementtion, it is neessry to look t 4 ses. You should hek eh of them.

10 9 Digitl Ciruit Design Flip-flop The next iruit is the flip-flop (sometimes lled lth ). d d if then else The inputs re d (for dt) nd (for ontrol. Textooks often sy tht is for lok euse sometimes this input omes from the output of lok iruit. But we should not nme n input y where it my or my not ome from). The output is (for output, ut o looks too muh like zero, so is used). A flip-flop ehves s follows. If =, then =d. If =, remins s it ws. The iruit on the right hs n interesting feture lled feedk. The output goes through dely nd then is fed k into n input of the multiplexer. When =, the multiplexer's else input is wht ws moment erlier; tht's how remins wht it ws. Without the dely, there would e no onstrint on when = ; the multiplexer would sy =, whih is lwys true no mtter wht is. So dely is neessry: when =, = dely. However, multiplexer is not instnt, nd its dely is suffiient. A dely is implemented s n even numer of not gtes, nd 0 is n even numer. The dely in the flip-flop iruit represents the dely lredy present in the multiplexer, without dding more. Here is inry versus time digrm of flip-flop. d Both nd d re inputs, so we n hoose to mke them whtever we wnt. They re hosen here to illustrte tht while is, is identil to d, nd while is, remins s it ws when hnged from to. Feedk is hrteristi of memory. A flip-flop is one it of memory; it rememers wht d ws the lst time ws. Edge-trigger The flip-flop we hve just seen is lled sensitive euse the output euls the d input ll the time tht is. Next we look t mehnism lled edge-triggering tht keeps the output onstnt exept when hnges. A rising edge-trigger keeps the output onstnt exept when hnges from to. It looks like this. d d The ox piture on the left hs little tringle t the ontrol input to sy it is rising edge-

11 Digitl Ciruit Design 10 triggered. We uild it from sensitive flip-flop (with little sure t the ontrol input) nd some edge-triggering iruitry. The only time the ontrol of the sensitive flip-flop is is when is nd it ws just previously ( nd not dely ). We need the dely to e long enough to detet rising edge, ut no longer. A flling edge-trigger keeps the output onstnt exept when hnges from to. It looks like this. d d The ox piture hs little irle nd tringle t the ontrol input to sy it is flling edgetriggered. In the right digrm we see tht the only time the ontrol of the flip-flop is is when is nd it ws just previously ( not nd dely ). The dely from d into the flipflop's dt input is so tht the output will e the vlue of d just efore hnged from to. Merge The 1-2-merge hs inputs nd nd output. When pulses rrive on nd in tht order ( first, seond), or simultneously, it outputs pulse, nd then resets itself redy to go gin. The output is t ll other times. Here re the pitures. 1 2 For the purpose of explntion, two internl pths hve een leled. Pth r is when is or ws just previously, nd r is when is nd ws just previously. In other words, r is t the flling edge of, when n output pulse hs just ourred (the r iruitry is n edge-trigger). The dely etween nd r must e just enough to detet the edge. Suppose n output pulse hs not just ourred, nd hs not just hnged from to. Then r is. So A is if input is or ws previously. As long s is, will e ; when eomes, will eome ; when eomes, will eome. If there hs lredy een pulse on, or t lest pulse on hs strted, then pulse on eomes pulse on. At the end of the pulse on, r momentrily eomes, so A eomes until the next pulse on. The dely fter A represents the dely lredy present in the nd nd or gtes, without dding more. Next we look t symmetri merge. It lso hs inputs nd nd output. When pulses rrive on nd in either order or simultneously, it outputs pulse, nd then resets itself redy to go gin. r r A A B

12 11 Digitl Ciruit Design As efore, r is t the flling edge of, when n output pulse hs just ourred. As efore, A is if input is or ws sine the end of the lst pulse on. Symmetrilly, B is if input is or ws sine the end of the lst pulse on. Output oinides with whihever pulse on or ours seond. At the end of the pulse on, r momentrily eomes, so A eomes until the next pulse on, nd B eomes until the next pulse on. The wy the merges funtion hs een explined y nming internl pths r, A, nd B. But the merges re designed the other wy round. First, we deide tht it would e helpful to know whether there hs een pulse on input sine the lst pulse on output, nd similrly whether there hs een pulse on input sine the lst pulse on output. Tht is, we deide tht there will e internl pths A nd B efore we know wht gtes there will e. To implement A nd B, we deide tht it will e helpful to know when is the flling edge of ; tht is, we deide to hve internl pth r. And finlly, we deide wht gtes re needed. Binry Numer Representtion We re fmilir with the nturl numers expressed in deiml: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, nd so on. In inry, it's muh the sme, exept tht there re only two digits insted of ten. The nturl numers expressed in inry re: 0, 1, 10, 11, 100, 101, 110, 111, 1000, nd so on. The seuene of inry digits 1101 represents the numer expressed in deiml s = = 13 The exponents (powers of 2) re 0, 1, 2,... for the digits going from right to left. We therefore numer the digits tht sme wy: in 1101, digit numer 0 is the rightmost 1, digit numer 1 is 0, digit numer 2 is 1, nd digit numer 3 is the leftmost 1. If = 1101, then = = 1101 We use inry vlue to represent inry digit 0, nd inry vlue to represent inry digit 1. The word it hs lredy een introdued s the si unit of informtion, the si unit of memory, nd s synonym for inry vlue. It is lso ontrtion of inry digit. Fortuntely, these four menings re omptile, not onfliting. Multipth Nottion We use doule rrow to men severl pths, without eing speifi out how mny. In eh row elow, the piture on the left mens the piture in the middle (s 4-it exmple). Sometimes the piture in the middle n e deomposed into the piture on the right mens nd mye mens nd mye

13 Digitl Ciruit Design mens nd mye Bit Comprison We now ompre two inry inputs to see if they re uneul. If nd re uneul, then = ; if they re eul, then =. (This iruit is sometimes lled exlusive or, sometimes lled prity, nd sometimes lled ddition modulo 2.) We might wnt to ompre mny pirs of its to see whih pirs re uneul. The ox piture is: i = (i i), i = n 1, n 2,..., 0 The input is relly n inputs n 1, n 2,..., 2, 1, 0. Similrly for the input nd the output. This omprison is lled itwise ; it mens 0 = (0 0), 1 = (1 1), nd so on. It is implemented y putting n single-it iruits eside eh other. Numer Comprison More often, we wnt to ompre two n-it numers to see if they re uneul; we wnt single it of result, not n its. Here is the ox piture nd its implementtion. = ( ) If nd differ in one or more it positions, then nd re uneul. Numers n lso e ompred to see whih is smller nd whih lrger. Here is the ox piture. < = (<) It n e implemented y seuene of oxes, lled LT oxes (for Less Thn). Eh ox gets one it of input nd one it of input, nd they re onneted s in the following 6-it exmple = ( ) = 6 LT 5 LT 4 LT 3 LT 2 LT 1 LT 0 Bit i hs the mening i 1..0 < i In other words, i = if nd only if the prt of to the right of i is less thn the prt of to the right of i. And therefore the output is 6. Eh

14 13 Digitl Ciruit Design LT ox gives its output i+1 the vlue in the following three ses: i=0 nd i=1, euse then the prt of to the right of i+1 is less thn the prt of to the right of i+1, regrdless of the inputs further to the right; i=0 nd i=, euse then, either i=1 s efore, or i=0 nd the reltion is determined y i= ; i=1 nd i=, euse then, either i=0 s efore, or i=1 nd the reltion is determined y i=. Here is n LT ox nd its implementtion. i i i i i+1 LT i i+1 Arithmeti i We now present iruit tht dds two inry numers. Its ox piture is + s overflow Inputs nd nd output s ould e 32 pths eh, for n dder tht dds two 32-it numers produing 32-it sum. When you dd two 32-it numers, the sum my not e representle in 32 its; the overflow result is if the sum is representle, nd if it is not. To implement n dder, we need to know how to dd. Here is 6-it exmple, in whih we dd nd it position = = s = Strting from the right end, we dd 0+0 = 1+0 = 1 = s0. Next we dd 1+1 = 1+1 = 10 so s1=0 nd 1 is rried to it position 2. Next 2+2+(the rry) = = 1 = s2. Next 3+3 = 1+1 = 10 so s3=0 nd 1 is rried to it position 4. Next 4+4+(the rry) = = 11 so s2=1 nd 1 is rried to it position 5. Finlly 5+5+(the rry) = = 1 = s5. The sum is representle in 6 its, so overflow=. Here is the sme exmple gin, ut this time when there is no rry, we sy the rry is 0. To mke ll it positions the sme, the rry in position 0 is 0. Clling the rry, we hve it position = = = s = The rry into it position 6 is the overflow it (no overflow in this exmple). In eh it position i, there is sum of 3 its: i+i+i, produing 2 its of result: i+1 si. So 6-it dder iruit looks like this: overflow = ADD ADD ADD ADD 3 2 ADD 1 ADD 0 s5 s4 s3 s2 s1 s0 Eh ADD ox represents one olumn of the ddition. The pttern is esily generlized to ny

15 Digitl Ciruit Design 14 numer of it positions. Now we hve to design n ADD ox; it hs to dd 3 its, with 2-it result. The right it of the result is 1 if there re n odd numer of 1's mong the inputs. In other words, si is 1 if i i i is 001, 010, 100, or 111. Let's mke iruit for the right it of the result. i i i i i i ODD si The left it of the result is 1 if there re two or more 1's mong the inputs. In other words, i+1 is 1 if i i i is 011, 101, 110, or 111. Let's mke iruit for the left it of the result, nd we'll ll it MAJ for mjority. i i i i i i si i+1 MAJ i+1 We put the left nd right its together to mke the ADD ox. i i i i i i+1 ADD i i+1 MAJ ODD si And tht ompletes the dder. Mny people were tught to sutrt in poor wy. For exmple, in deiml, to sutrt 3456 from 13002, you my hve een tught position = = d = In position 0, you n't tke 6 from 2, so you orrow from position 1, ut you n't orrow from 0, so you orrow from position 2, ut gin you n't orrow from 0, so you orrow from position 3. Tht redues the 3 in position 3 to 2, hnges the 0 in position 2 to 9, hnges the 0 in position 1 to 9, nd finlly hnges the 2 in position 0 to 12. All of tht just to get the rightmost digit of the nswer. We wnt to mke ox for eh position, nd onnet eh position to its immedite neighors, just s we did for ddition. We don't wnt to hve to onnet eh position to ll other positions. So here is etter wy to sutrt. si

16 15 Digitl Ciruit Design position = = = d = We re sutrting nd getting the differene d. We don't orrow, we rry, nd the rries re written in etween the two opernds. To mke ll positions the sme, we rry 0 into position 0. We dd the digit nd the rry digit, nd sutrt tht from the digit. In position 0, we n't sutrt 6+0 from 2, so we rry 1 to position 1. Now we sutrt 6+0 from 12 (you n see the 12 inside the ovl) nd get 6 s the rightmost nswer digit. We didn't hve to look further left thn the next position. In position 1, we n't sutrt 5+1 from 0, so we rry 1 to position 2. Now we sutrt 5+1 from 10 (to see the 10, slide the ovl left one position) nd get 4 s the nswer digit in position 1. In position 2, we n't sutrt 4+1 from 0, so we rry 1 to position 3. Now we sutrt 4+1 from 10 nd get 5 s the nswer digit in position 2. In position 3, we n't sutrt 3+1 from 3, so we rry 1 to position 4. Now we sutrt 3+1 from 13 nd get 9 s the nswer digit in position 3. In position 4, we n sutrt 0+1 from 1 nd get 0 s the nswer digit in position 4. The rry to position 6, whih is 0, sys tht is less thn or eul to, nd the nswer is orret. Now in 6-it inry, we sutrt from position = = = d = The rry into position 0 is 0. In position 0, we sutrt 0+0 from 1 nd get 1 s the nswer it. In position 1, we n't sutrt 1+0 from 0, so we rry 1 to position 2. Now we sutrt 1+0 from 10 (you n see the 10 inside the ovl) nd get 1. In position 2, we sutrt 0+1 from 1 nd get 0. In position 3, we n't sutrt 1+0 from 0, so we rry 1 to position 4. Now we sutrt 1+0 from 10 (to see the 10, slide the ovl left one position) nd get 1. In position 4, we n't sutrt 1+1 from 0, so we rry 1 to position 5. Now we sutrt 1+1 from 10 nd get 0. In position 5, we sutrt 0+1 from 1 nd get 0. The rry to position 6, whih is 0, sys tht is less thn or eul to, nd the nswer is orret. Here is the ox piture of sutrtor. d overflow The word overflow is not the right nme for this output, ut it is the nme tht is lwys used. This output is 0 when nd d is the desired differene. This output is 1 when < nd d is not the desired differene. Here is the implementtion of 6-it sutrtor overflow 5 4 SUB SUB SUB SUB 3 2 SUB 1 SUB 0 d5 d4 d3 d2 d1 d0 Eh SUB ox represents one olumn of the sutrtion. The pttern is esily generlized to ny numer of it positions. Now we hve to design SUB ox. The right it of the result is 1 if there re n odd

17 Digitl Ciruit Design 16 numer of 1's mong the inputs, extly the sme s for ddition. The left it of the result is given y the LT ox tht we designed erlier. i i i i i+1 SUB i i+1 LT i ODD di You should hek ll 8 omintions of inputs for the SUB ox to mke sure they hve the right outputs. And tht ompletes the sutrtor. We hve looked t ddition nd sutrtion of nturl numers. We n esily dpt these iruits to dd nd sutrt integers: positive, zero, nd negtive. The stndrd representtion of integers is lled two's omplement. The esiest definition of two's omplement is the representtion tht uses the sme ddition nd sutrtion lgorithms s nturl numers. The only ltertion is overflow. Here is 6-it ddition. di ADD 5 ADD 4 ADD 3 ADD 2 ADD 1 ADD 0 s5 s4 s3 s2 s1 s0 overflow For two's omplement sutrtion, mke extly the sme hnge to the overflow output. We hve looked t ddition nd sutrtion of integers. We will look t multiplition of integers lter. We will not look t division, whih is hrder. And we will not look t flotingpoint rithmeti. In this short ourse, we show how si rithmeti n e done in order to remove the mgi. Fst rithmeti is so importnt tht n immense mount of work hs gone into finding etter, fster wys of doing rithmeti thn re presented here. If you re interested, onsult textook devoted to rithmeti. And you might like to look t New Representtion of the Rtionl Numers for Fst Esy Arithmeti. Generl Multiplexer nd Demultiplexer We hve lredy seen the iruit for multiplexer. We now generlize it: insted of 1-it input x tht hooses etween 2 other inputs y nd z, this generliztion hs n its of input x tht hoose mong 2 n other inputs y, where n is ny nturl numer. Here is the n=2 version. x x1x0 y se z y0 y1 z y2 y3

18 17 Digitl Ciruit Design In the implementtion on the right, x is 2 pths, nd the x inputs re inry representtion of one of the numers 0, 1, 2, nd 3. If x represents 0, then z=y0. If x represents 1, then z=y1. And so on. In generl, z=yx. We mke the sme generliztion of demultiplexer. x x1x0 z0 y se z y z1 z2 z3 If x represents 0, then z0=y ; if x doesn't represent 0, then z0=. If x represents 1, then z1=y ; if x doesn't represent 1, then z1=. And so on. In generl, for ny numer of inputs, zx=y, nd zi= for i x. Register A register is group of flip-flops onneted y ommon ontrol. Its ox piture is on the left, nd its implementtion is on the right. d3 d2 d1 d0 d This implementtion uses 4 flip-flops to mke 4-it register, ut it should e ler how to mke register with ny other numer of its. An n-it register holds n its of informtion. Tht just mens tht there re n its of output from the n flip-flops. This informtion ould e n n-it numer, or the odes for some hrters, or omputer instrution, or just n its. To hnge the informtion in register, put the new informtion on the dt input pths d, nd then send pulse on the ontrol pth. In the sensitive register pitured ove (sure t the ontrol input), the informtion in the register (the outputs from the register) my hnge t the rising edge of the ontrol pulse, nd ontinue hnging ording to ny hnges in the dt inputs for s long s the ontrol pulse is up, nd then eome unhnging t the flling edge of the ontrol pulse. To rete n edgetriggered register, we do not need to use edge-triggered flip-flops. The edge-triggering n e done one for ll flip-flops. Here is flling edge-triggered register. d 0 d3 d2 d1 d

19 Digitl Ciruit Design 18 In the flling edge-triggered register (irle nd tringle t the ontrol input ), the informtion in the register doesn't hnge until the flling edge of the ontrol pulse. At the flling edge, the its of dt input eome the its in the register. After tht, the ontent of the register is gin unhnging. In rising edge-triggered register (just tringle t the ontrol input ), the its of dt input eome the its in the register t the rising edge of the ontrol pulse. After tht, the ontent of the register is unhnging. Memory A memory (or rndom ess memory, or RAM) is olletion of registers onneted y ommon dt pths. Its ox piture is on the left, nd its implementtion is on the right. w d r w d r se se!? For the memory of omputer, eh register is typilly 8 its, whih is lled yte. A 4 gigyte memory hs 2 32 registers, rther thn the 4 shown here. The registers re numered 0, 1, 2, 3,..., nd register's numer is lled its ddress. A 4 gigyte memory hs 32 writing ddress inputs ( w ), 32 reding ddress inputs ( r ), 8 dt inputs ( d ), 8 outputs ( ), nd 1 ontrol input ( ). To write something into register, put the ddress of the register you wnt to write in input w, nd t the sme time, put the dt you wnt to write in input d ; then put pulse in input. The dt goes to ll registers, ut the demultiplexer on the left side of the implementtion piture routes the pulse to the orret register, so only tht register hnges its ontents. To red the ontents of register from the memory, put the ddress of the register you wnt to red in input r ; the ontents of tht register is output. On the right side of the implementtion piture, the multiplexer is relly severl multiplexers: one for eh it in register. The ddress r goes to eh multiplexer. Multiplexer 0 tkes ll the it 0s from ll the registers, nd produes it 0 of the result. And so on for the other its. The memory pitured is sensitive (sure t the ontrol input). To mke n edgetriggered memory, we do not need to mke eh register edge-triggered; we just need to dd the edge-triggering one t the input. (Aside: The previous digrm shows how memory works. But for omputer, 8 its wide nd 2 32 its long is not prtil lyout for VLSI iruit. To e prtil, the 32-it ddress is divided into hlves. The first 16 its re used to ddress n x-oordinte, nd the lst 16 its re used to ddress y-oordinte, in sure rry. Eh yte of memory sits t the intersetion of n x-oordinte nd y-oordinte. This gives memory sure shpe. End of Aside) Memory tht you uy differs from the memory presented here in one respet: it hs only one ddress input, not two s shown here. Its one ddress goes to oth the demultiplexer for writing nd to the multiplexer(s) for reding. The wy omputers hve een uilt up to now, n

20 19 Digitl Ciruit Design instrution eing exeuted might red from memory, or it might write to memory, ut not oth t the sme time. The memory shown here, with two ddresses, llows writing t one ddress to hppen t the sme time s reding t nother ddress. In ft, it llows writing nd reding to hppen t the sme ddress t the sme time, ut the result is unpreditle, so tht's not good ide. Progrms We now hve ll we need to show how progrms eome iruits. The mteril presented here is one of the iruit design methods in the pper High-Level Ciruit Design. Write progrm in ny impertive progrmming lnguge, suh s C, Jv, Python, or ny other lnguge of your hoie. Eh vrile in the progrm eomes flling edgetriggered register with enough its to store the vlues tht n e ssigned to the vrile. For exmple, if we hve vrile x in the progrm tht n e ssigned 32-it integers, then in the iruit we hve dx x Just efore the ontrol input, there is n or gte; its inputs x ome from ll the ples where x is eing ssigned vlue. The or gte going into the register's dt input is relly severl or gtes: one for eh it in the register. So in this exmple, it is 32 or gtes. The inputs dx to these or gtes ome from ll the ples where x is eing ssigned vlue, just like the ontrol inputs x. If there re 4 suh ples, then eh of these 32 or gtes hs 4 inputs. The outputs x go to ll ples tht reuire the vlue of vrile x. If there re 5 suh ples, then eh of the 32 outputs splits into 5 diretions. For eh rry in the progrm, there is flling edge-triggered memory. If there re 3 rrys in the progrm, there will e three memories. A memory hs just enough registers for the numer of elements in its rry; if the rry size is dynmi, the memory must hve enough registers for the mximum size of its rry. Eh register in the memory hs the numer of its neessry to store the vlue of n rry element. For exmple, if the progrm hs n rry A, then the iruit hs: da x wa A!? ra A The inputs leled da (dt for A ), wa (writing ddress for A ), nd A (ontrol for A ) ome from ll ples where n element of rry A is eing ssigned vlue. The inputs leled ra (reding ddress for A ) ome from ll ples tht use the vlue of n element of rry A. The outputs leled A go to ll ples tht use the vlue of n element of rry A. The A inputs go into single or gte. The wa nd ra inputs go into s mny or gtes s there re ddress its. The da inputs go into s mny or gtes s there re dt its. For eh sttement in the progrm we hve iruit with ontrol input nd output ʹ.

21 Digitl Ciruit Design 20 A pulse on strts the iruit working, nd when it is finished, it sends out pulse on ʹ. In progrm, vrile or rry element gets vlue y mens of n ssignment. To ssign to vrile x the sum of the vlues of x nd y, the syntx my e x:=x+y or x=x+y; or something else, depending on the progrmming lnguge. This ssignment is ompiled to the following iruit. The inputs mrked x nd y ome from the registers for vriles x nd y. If x nd y re 32 it vriles, there re 32 pths for eh of them. They go through n dder tht hs 32 its of output (we re ignoring the overflow output). A pulse rriving on goes through dely tht is just long enough to llow the dder to dd the urrent vlues of vriles x nd y. The nd gte in the piture is relly 32 nd gtes, eh of whih hs one input from the sum nd the dely input. The 32 outputs from the nd gtes eome the dt input dx for vrile x. Menwhile, the pulse from dely goes to the ontrol input for vrile x, to give x its new vlue. Also, dely goes through nother dely to provide smll seprtion etween this ssignment nd the next opertion, eoming pulse on ʹ to sy ll done this ssignment. When this ssignment is not eing exeuted, dely =, so the outputs dx of the 32 nd gtes re ll, so they do not interfere with ny other ssignments to x tht my e tking ple. Our exmple ssignment sttement hs n ddition in it, nd the iruit hs n dder in it. So the iruit for the whole progrm will hve s mny dders s there re dditions ppering in the progrm. Similrly for sutrtors, multipliers, nd so on. Alterntively, n dder or other iruit n e shred mong severl expressions (y mens of the funtion ll iruitry whih we present lter), t the progrmmer's disretion. An expression my depend on n rry element; if so, the reding ddress for tht rry element must e output from the expression iruit, onjoined with, nd routed to the memory for tht rry. There my e referenes to elements of severl rrys, ut there n e t most one rry element referene per rry in the expression. If you wnt more thn one element of the sme rry, you must rek up the expression. For exmple, x:= A[i]+A[j] eomes x:= A[i]; x:= x+a[j] (or whtever syntx your lnguge uses). An rry element ssignment is little more omplited. For exmple, A[i]:= x produes the iruit ʹ A i wa When sttement P is followed seuentilly y sttement Q in progrm, the iruit for P is onneted to the iruit for Q y onneting the ʹ output of P to the input of Q. x y x P + The pulse tht P sends out to sy it is done is the pulse tht strts Q. Most ommonly used progrmming lnguges either do not hve prllel omposition, or hve prllel onstrut tht is restrited in how it n e used nd is not esy to use. If sttement P is to e exeuted in prllel with sttement Q, the iruits for P nd Q re Q da ʹ x dx ʹ

22 21 Digitl Ciruit Design onneted like this: P ʹ Q The ontrol signl strts oth P nd Q t the sme time. They my finish t different times. Eh sends pulse on its ʹ output when it finishes. These pulses go to merge ox, whih emits pulse only when it hs reeived input pulses on oth its inputs. Simultneous ess to different vriles or rrys poses no prolem. Even for the sme vrile, simultneous reds re no prolem. But simultneously reding nd writing the sme vrile, or two simultneous writes to the sme vrile, hve unpreditle results, nd is not reommended. Every progrmming lnguge hs onditionl sttement. It my look like if then P or it my look like if () P or it my look some other wy. The inry expression is evluted, nd if is true, sttement P is exeuted, nd if is flse, nothing more hppens. It produes the iruit: The ox leled evlutes expression, nd hs inputs tht ome from ny vriles nd rry elements used in expression. The dely is just long enough to evlute expression. The ontrol pulse goes either to P nd then out ʹ, or diretly out ʹ. The onditionl sttement my hve two-tiled version tht looks like if () P else Q, or like if then P else Q, or perhps some other syntx. The inry expression is evluted, nd if is true, sttement P is exeuted, nd if is flse, sttement Q is exeuted. It produes the iruit: if then else if then else P P Q ʹ ʹ A loop my hve syntx like while do P or like while () P or something else. Here is its iruit. if then else P ʹ We n similrly onstrut iruit for loop whose exit ondition omes t the end, nd even for loop tht hs severl exits in the middle. A proedure or void funtion or method is unit of progrm tht n e nmed, so tht it n e lled from severl ples, nd return k to the ple where it ws lled. Ignoring prmeters for moment, proedure P hs this iruit: P P Pʹ

23 Digitl Ciruit Design 22 The inputs leled P ome from ll the ples where P is lled (the piture shows 2 inputs, ut it ould e ny numer). The outputs leled Pʹ go k to ll the ples where P is lled (the piture shows 2 outputs, ut it ould e ny numer). The lling points eh eome P Pʹ 2 1 ʹ When ontrol pulse rrives t ll, it is sent to the lled proedure to strt the proedure. It lso goes into the 1-input of 1-2-merge ox. A 1-2-merge ox emits pulse only when it reeives input pulses in speifi order: first into the 1-input, then into the 2-input. When the proedure finishes, it sends pulse k to ll lling points. When the pulse rrives t this lling point, it goes into the 2-input, using the 1-2-merge ox to emit pulse. All those pulses tht rrive t lling points tht did not ll the proedure go into the 2-input of the 1-2-merge ox there, ut there ws no previous pulse in the 1-input there, so no pulse is emitted y those 1-2-merge oxes. This implementtion does not work for reursive lls in generl, ut it does work for til-reursive lls. An internl (non-til) reursive ll reuires n up-down-ounter, ut we don't pursue tht here. The present implementtion lso doesn't work if prllel lling points ll the proedure t the sme time or t overlpping times, so tht should e voided. A prmeter delrtion n e treted extly s though it were introduing lol vrile insted of prmeter, nd prmeter pssing n e treted the sme s ssignment, t lest for some kinds of prmeters. For funtion ll tht returns result, we n gin use the ssignment iruit. There re other wys to produe iruits from progrms, nd there re mny other lnguge fetures we ould over, ut perhps tht's enough to give you the min ide. Now let's put it ll together with n exmple. Gretest Common Divisor Here is progrm in C, exept tht is eing used for prllel omposition; it should lso e understndle to Jv progrmmers. int, ; void gd (void) { while (!=) if (<) = ; else = ; } min ( ) { { = 3; = 27;} gd ( ); { = 12; = 30;} gd ( ); } If nd hve positive integer vlues, then proedure gd omputes their gretest ommon divisor, nd presents the nswer s the vlue of oth nd. Here re the iruits of vriles nd. d d

1 PYTHAGORAS THEOREM 1. Given a right angled triangle, the square of the hypotenuse is equal to the sum of the squares of the other two sides.

1 PYTHAGORAS THEOREM 1. Given a right angled triangle, the square of the hypotenuse is equal to the sum of the squares of the other two sides. 1 PYTHAGORAS THEOREM 1 1 Pythgors Theorem In this setion we will present geometri proof of the fmous theorem of Pythgors. Given right ngled tringle, the squre of the hypotenuse is equl to the sum of the

More information

Project 6: Minigoals Towards Simplifying and Rewriting Expressions

Project 6: Minigoals Towards Simplifying and Rewriting Expressions MAT 51 Wldis Projet 6: Minigols Towrds Simplifying nd Rewriting Expressions The distriutive property nd like terms You hve proly lerned in previous lsses out dding like terms ut one prolem with the wy

More information

6.5 Improper integrals

6.5 Improper integrals Eerpt from "Clulus" 3 AoPS In. www.rtofprolemsolving.om 6.5. IMPROPER INTEGRALS 6.5 Improper integrls As we ve seen, we use the definite integrl R f to ompute the re of the region under the grph of y =

More information

CS 573 Automata Theory and Formal Languages

CS 573 Automata Theory and Formal Languages Non-determinism Automt Theory nd Forml Lnguges Professor Leslie Lnder Leture # 3 Septemer 6, 2 To hieve our gol, we need the onept of Non-deterministi Finite Automton with -moves (NFA) An NFA is tuple

More information

PYTHAGORAS THEOREM WHAT S IN CHAPTER 1? IN THIS CHAPTER YOU WILL:

PYTHAGORAS THEOREM WHAT S IN CHAPTER 1? IN THIS CHAPTER YOU WILL: PYTHAGORAS THEOREM 1 WHAT S IN CHAPTER 1? 1 01 Squres, squre roots nd surds 1 02 Pythgors theorem 1 03 Finding the hypotenuse 1 04 Finding shorter side 1 05 Mixed prolems 1 06 Testing for right-ngled tringles

More information

Intermediate Math Circles Wednesday, November 14, 2018 Finite Automata II. Nickolas Rollick a b b. a b 4

Intermediate Math Circles Wednesday, November 14, 2018 Finite Automata II. Nickolas Rollick a b b. a b 4 Intermedite Mth Circles Wednesdy, Novemer 14, 2018 Finite Automt II Nickols Rollick nrollick@uwterloo.c Regulr Lnguges Lst time, we were introduced to the ide of DFA (deterministic finite utomton), one

More information

5. Every rational number have either terminating or repeating (recurring) decimal representation.

5. Every rational number have either terminating or repeating (recurring) decimal representation. CHAPTER NUMBER SYSTEMS Points to Rememer :. Numer used for ounting,,,,... re known s Nturl numers.. All nturl numers together with zero i.e. 0,,,,,... re known s whole numers.. All nturl numers, zero nd

More information

The University of Nottingham SCHOOL OF COMPUTER SCIENCE A LEVEL 2 MODULE, SPRING SEMESTER MACHINES AND THEIR LANGUAGES ANSWERS

The University of Nottingham SCHOOL OF COMPUTER SCIENCE A LEVEL 2 MODULE, SPRING SEMESTER MACHINES AND THEIR LANGUAGES ANSWERS The University of ottinghm SCHOOL OF COMPUTR SCIC A LVL 2 MODUL, SPRIG SMSTR 2015 2016 MACHIS AD THIR LAGUAGS ASWRS Time llowed TWO hours Cndidtes my omplete the front over of their nswer ook nd sign their

More information

Spacetime and the Quantum World Questions Fall 2010

Spacetime and the Quantum World Questions Fall 2010 Spetime nd the Quntum World Questions Fll 2010 1. Cliker Questions from Clss: (1) In toss of two die, wht is the proility tht the sum of the outomes is 6? () P (x 1 + x 2 = 6) = 1 36 - out 3% () P (x 1

More information

CS 2204 DIGITAL LOGIC & STATE MACHINE DESIGN SPRING 2014

CS 2204 DIGITAL LOGIC & STATE MACHINE DESIGN SPRING 2014 S 224 DIGITAL LOGI & STATE MAHINE DESIGN SPRING 214 DUE : Mrh 27, 214 HOMEWORK III READ : Relte portions of hpters VII n VIII ASSIGNMENT : There re three questions. Solve ll homework n exm prolems s shown

More information

NON-DETERMINISTIC FSA

NON-DETERMINISTIC FSA Tw o types of non-determinism: NON-DETERMINISTIC FS () Multiple strt-sttes; strt-sttes S Q. The lnguge L(M) ={x:x tkes M from some strt-stte to some finl-stte nd ll of x is proessed}. The string x = is

More information

Introduction to Olympiad Inequalities

Introduction to Olympiad Inequalities Introdution to Olympid Inequlities Edutionl Studies Progrm HSSP Msshusetts Institute of Tehnology Snj Simonovikj Spring 207 Contents Wrm up nd Am-Gm inequlity 2. Elementry inequlities......................

More information

Exercise 3 Logic Control

Exercise 3 Logic Control Exerise 3 Logi Control OBJECTIVE The ojetive of this exerise is giving n introdution to pplition of Logi Control System (LCS). Tody, LCS is implemented through Progrmmle Logi Controller (PLC) whih is lled

More information

Algorithms & Data Structures Homework 8 HS 18 Exercise Class (Room & TA): Submitted by: Peer Feedback by: Points:

Algorithms & Data Structures Homework 8 HS 18 Exercise Class (Room & TA): Submitted by: Peer Feedback by: Points: Eidgenössishe Tehnishe Hohshule Zürih Eole polytehnique fédérle de Zurih Politenio federle di Zurigo Federl Institute of Tehnology t Zurih Deprtement of Computer Siene. Novemer 0 Mrkus Püshel, Dvid Steurer

More information

Arrow s Impossibility Theorem

Arrow s Impossibility Theorem Rep Voting Prdoxes Properties Arrow s Theorem Arrow s Impossiility Theorem Leture 12 Arrow s Impossiility Theorem Leture 12, Slide 1 Rep Voting Prdoxes Properties Arrow s Theorem Leture Overview 1 Rep

More information

Chapter 4 State-Space Planning

Chapter 4 State-Space Planning Leture slides for Automted Plnning: Theory nd Prtie Chpter 4 Stte-Spe Plnning Dn S. Nu CMSC 722, AI Plnning University of Mrylnd, Spring 2008 1 Motivtion Nerly ll plnning proedures re serh proedures Different

More information

Activities. 4.1 Pythagoras' Theorem 4.2 Spirals 4.3 Clinometers 4.4 Radar 4.5 Posting Parcels 4.6 Interlocking Pipes 4.7 Sine Rule Notes and Solutions

Activities. 4.1 Pythagoras' Theorem 4.2 Spirals 4.3 Clinometers 4.4 Radar 4.5 Posting Parcels 4.6 Interlocking Pipes 4.7 Sine Rule Notes and Solutions MEP: Demonstrtion Projet UNIT 4: Trigonometry UNIT 4 Trigonometry tivities tivities 4. Pythgors' Theorem 4.2 Spirls 4.3 linometers 4.4 Rdr 4.5 Posting Prels 4.6 Interloking Pipes 4.7 Sine Rule Notes nd

More information

CS311 Computational Structures Regular Languages and Regular Grammars. Lecture 6

CS311 Computational Structures Regular Languages and Regular Grammars. Lecture 6 CS311 Computtionl Strutures Regulr Lnguges nd Regulr Grmmrs Leture 6 1 Wht we know so fr: RLs re losed under produt, union nd * Every RL n e written s RE, nd every RE represents RL Every RL n e reognized

More information

For a, b, c, d positive if a b and. ac bd. Reciprocal relations for a and b positive. If a > b then a ab > b. then

For a, b, c, d positive if a b and. ac bd. Reciprocal relations for a and b positive. If a > b then a ab > b. then Slrs-7.2-ADV-.7 Improper Definite Integrls 27.. D.dox Pge of Improper Definite Integrls Before we strt the min topi we present relevnt lger nd it review. See Appendix J for more lger review. Inequlities:

More information

Propositional models. Historical models of computation. Application: binary addition. Boolean functions. Implementation using switches.

Propositional models. Historical models of computation. Application: binary addition. Boolean functions. Implementation using switches. Propositionl models Historil models of omputtion Steven Lindell Hverford College USA 1/22/2010 ISLA 2010 1 Strt with fixed numer of oolen vriles lled the voulry: e.g.,,. Eh oolen vrile represents proposition,

More information

GM1 Consolidation Worksheet

GM1 Consolidation Worksheet Cmridge Essentils Mthemtis Core 8 GM1 Consolidtion Worksheet GM1 Consolidtion Worksheet 1 Clulte the size of eh ngle mrked y letter. Give resons for your nswers. or exmple, ngles on stright line dd up

More information

A Study on the Properties of Rational Triangles

A Study on the Properties of Rational Triangles Interntionl Journl of Mthemtis Reserh. ISSN 0976-5840 Volume 6, Numer (04), pp. 8-9 Interntionl Reserh Pulition House http://www.irphouse.om Study on the Properties of Rtionl Tringles M. Q. lm, M.R. Hssn

More information

expression simply by forming an OR of the ANDs of all input variables for which the output is

expression simply by forming an OR of the ANDs of all input variables for which the output is 2.4 Logic Minimiztion nd Krnugh Mps As we found ove, given truth tle, it is lwys possile to write down correct logic expression simply y forming n OR of the ANDs of ll input vriles for which the output

More information

Finite State Automata and Determinisation

Finite State Automata and Determinisation Finite Stte Automt nd Deterministion Tim Dworn Jnury, 2016 Lnguges fs nf re df Deterministion 2 Outline 1 Lnguges 2 Finite Stte Automt (fs) 3 Non-deterministi Finite Stte Automt (nf) 4 Regulr Expressions

More information

Lecture 6. CMOS Static & Dynamic Logic Gates. Static CMOS Circuit. PMOS Transistors in Series/Parallel Connection

Lecture 6. CMOS Static & Dynamic Logic Gates. Static CMOS Circuit. PMOS Transistors in Series/Parallel Connection NMOS Trnsistors in Series/Prllel onnetion Leture 6 MOS Stti & ynmi Logi Gtes Trnsistors n e thought s swith ontrolled y its gte signl NMOS swith loses when swith ontrol input is high Peter heung eprtment

More information

Lecture 3: Equivalence Relations

Lecture 3: Equivalence Relations Mthcmp Crsh Course Instructor: Pdric Brtlett Lecture 3: Equivlence Reltions Week 1 Mthcmp 2014 In our lst three tlks of this clss, we shift the focus of our tlks from proof techniques to proof concepts

More information

where the box contains a finite number of gates from the given collection. Examples of gates that are commonly used are the following: a b

where the box contains a finite number of gates from the given collection. Examples of gates that are commonly used are the following: a b CS 294-2 9/11/04 Quntum Ciruit Model, Solovy-Kitev Theorem, BQP Fll 2004 Leture 4 1 Quntum Ciruit Model 1.1 Clssil Ciruits - Universl Gte Sets A lssil iruit implements multi-output oolen funtion f : {0,1}

More information

CARLETON UNIVERSITY. 1.0 Problems and Most Solutions, Sect B, 2005

CARLETON UNIVERSITY. 1.0 Problems and Most Solutions, Sect B, 2005 RLETON UNIVERSIT eprtment of Eletronis ELE 2607 Swithing iruits erury 28, 05; 0 pm.0 Prolems n Most Solutions, Set, 2005 Jn. 2, #8 n #0; Simplify, Prove Prolem. #8 Simplify + + + Reue to four letters (literls).

More information

(a) A partition P of [a, b] is a finite subset of [a, b] containing a and b. If Q is another partition and P Q, then Q is a refinement of P.

(a) A partition P of [a, b] is a finite subset of [a, b] containing a and b. If Q is another partition and P Q, then Q is a refinement of P. Chpter 7: The Riemnn Integrl When the derivtive is introdued, it is not hrd to see tht the it of the differene quotient should be equl to the slope of the tngent line, or when the horizontl xis is time

More information

Proving the Pythagorean Theorem

Proving the Pythagorean Theorem Proving the Pythgoren Theorem W. Bline Dowler June 30, 2010 Astrt Most people re fmilir with the formul 2 + 2 = 2. However, in most ses, this ws presented in lssroom s n solute with no ttempt t proof or

More information

THE PYTHAGOREAN THEOREM

THE PYTHAGOREAN THEOREM THE PYTHAGOREAN THEOREM The Pythgoren Theorem is one of the most well-known nd widely used theorems in mthemtis. We will first look t n informl investigtion of the Pythgoren Theorem, nd then pply this

More information

8 THREE PHASE A.C. CIRCUITS

8 THREE PHASE A.C. CIRCUITS 8 THREE PHSE.. IRUITS The signls in hpter 7 were sinusoidl lternting voltges nd urrents of the so-lled single se type. n emf of suh type n e esily generted y rotting single loop of ondutor (or single winding),

More information

Instructions. An 8.5 x 11 Cheat Sheet may also be used as an aid for this test. MUST be original handwriting.

Instructions. An 8.5 x 11 Cheat Sheet may also be used as an aid for this test. MUST be original handwriting. ID: B CSE 2021 Computer Orgniztion Midterm Test (Fll 2009) Instrutions This is losed ook, 80 minutes exm. The MIPS referene sheet my e used s n id for this test. An 8.5 x 11 Chet Sheet my lso e used s

More information

CS103B Handout 18 Winter 2007 February 28, 2007 Finite Automata

CS103B Handout 18 Winter 2007 February 28, 2007 Finite Automata CS103B ndout 18 Winter 2007 Ferury 28, 2007 Finite Automt Initil text y Mggie Johnson. Introduction Severl childrens gmes fit the following description: Pieces re set up on plying ord; dice re thrown or

More information

Homework 3 Solutions

Homework 3 Solutions CS 341: Foundtions of Computer Science II Prof. Mrvin Nkym Homework 3 Solutions 1. Give NFAs with the specified numer of sttes recognizing ech of the following lnguges. In ll cses, the lphet is Σ = {,1}.

More information

Arrow s Impossibility Theorem

Arrow s Impossibility Theorem Rep Fun Gme Properties Arrow s Theorem Arrow s Impossiility Theorem Leture 12 Arrow s Impossiility Theorem Leture 12, Slide 1 Rep Fun Gme Properties Arrow s Theorem Leture Overview 1 Rep 2 Fun Gme 3 Properties

More information

2.4 Theoretical Foundations

2.4 Theoretical Foundations 2 Progrmming Lnguge Syntx 2.4 Theoretil Fountions As note in the min text, snners n prsers re se on the finite utomt n pushown utomt tht form the ottom two levels of the Chomsky lnguge hierrhy. At eh level

More information

Linear Algebra Introduction

Linear Algebra Introduction Introdution Wht is Liner Alger out? Liner Alger is rnh of mthemtis whih emerged yers k nd ws one of the pioneer rnhes of mthemtis Though, initilly it strted with solving of the simple liner eqution x +

More information

CS12N: The Coming Revolution in Computer Architecture Laboratory 2 Preparation

CS12N: The Coming Revolution in Computer Architecture Laboratory 2 Preparation CS2N: The Coming Revolution in Computer Architecture Lortory 2 Preprtion Ojectives:. Understnd the principle of sttic CMOS gte circuits 2. Build simple logic gtes from MOS trnsistors 3. Evlute these gtes

More information

Improper Integrals. The First Fundamental Theorem of Calculus, as we ve discussed in class, goes as follows:

Improper Integrals. The First Fundamental Theorem of Calculus, as we ve discussed in class, goes as follows: Improper Integrls The First Fundmentl Theorem of Clculus, s we ve discussed in clss, goes s follows: If f is continuous on the intervl [, ] nd F is function for which F t = ft, then ftdt = F F. An integrl

More information

1.3 SCALARS AND VECTORS

1.3 SCALARS AND VECTORS Bridge Course Phy I PUC 24 1.3 SCLRS ND VECTORS Introdution: Physis is the study of nturl phenomen. The study of ny nturl phenomenon involves mesurements. For exmple, the distne etween the plnet erth nd

More information

Part 4. Integration (with Proofs)

Part 4. Integration (with Proofs) Prt 4. Integrtion (with Proofs) 4.1 Definition Definition A prtition P of [, b] is finite set of points {x 0, x 1,..., x n } with = x 0 < x 1

More information

Algebra Basics. Algebra Basics. Curriculum Ready ACMNA: 133, 175, 176, 177, 179.

Algebra Basics. Algebra Basics. Curriculum Ready ACMNA: 133, 175, 176, 177, 179. Curriulum Redy ACMNA: 33 75 76 77 79 www.mthletis.om Fill in the spes with nything you lredy know out Alger Creer Opportunities: Arhitets eletriins plumers et. use it to do importnt lultions. Give this

More information

Probability. b a b. a b 32.

Probability. b a b. a b 32. Proility If n event n hppen in '' wys nd fil in '' wys, nd eh of these wys is eqully likely, then proility or the hne, or its hppening is, nd tht of its filing is eg, If in lottery there re prizes nd lnks,

More information

Vectors. a Write down the vector AB as a column vector ( x y ). A (3, 2) x point C such that BC = 3. . Go to a OA = a

Vectors. a Write down the vector AB as a column vector ( x y ). A (3, 2) x point C such that BC = 3. . Go to a OA = a Streth lesson: Vetors Streth ojetives efore you strt this hpter, mrk how onfident you feel out eh of the sttements elow: I n lulte using olumn vetors nd represent the sum nd differene of two vetors grphilly.

More information

Part I: Study the theorem statement.

Part I: Study the theorem statement. Nme 1 Nme 2 Nme 3 A STUDY OF PYTHAGORAS THEOREM Instrutions: Together in groups of 2 or 3, fill out the following worksheet. You my lift nswers from the reding, or nswer on your own. Turn in one pket for

More information

Discrete Structures Lecture 11

Discrete Structures Lecture 11 Introdution Good morning. In this setion we study funtions. A funtion is mpping from one set to nother set or, perhps, from one set to itself. We study the properties of funtions. A mpping my not e funtion.

More information

Symmetrical Components 1

Symmetrical Components 1 Symmetril Components. Introdution These notes should e red together with Setion. of your text. When performing stedy-stte nlysis of high voltge trnsmission systems, we mke use of the per-phse equivlent

More information

Intermediate Math Circles Wednesday 17 October 2012 Geometry II: Side Lengths

Intermediate Math Circles Wednesday 17 October 2012 Geometry II: Side Lengths Intermedite Mth Cirles Wednesdy 17 Otoer 01 Geometry II: Side Lengths Lst week we disussed vrious ngle properties. As we progressed through the evening, we proved mny results. This week, we will look t

More information

Numbers and indices. 1.1 Fractions. GCSE C Example 1. Handy hint. Key point

Numbers and indices. 1.1 Fractions. GCSE C Example 1. Handy hint. Key point GCSE C Emple 7 Work out 9 Give your nswer in its simplest form Numers n inies Reiprote mens invert or turn upsie own The reiprol of is 9 9 Mke sure you only invert the frtion you re iviing y 7 You multiply

More information

Chapter 8 Roots and Radicals

Chapter 8 Roots and Radicals Chpter 8 Roots nd Rdils 7 ROOTS AND RADICALS 8 Figure 8. Grphene is n inredily strong nd flexile mteril mde from ron. It n lso ondut eletriity. Notie the hexgonl grid pttern. (redit: AlexnderAIUS / Wikimedi

More information

Chapter 3. Vector Spaces. 3.1 Images and Image Arithmetic

Chapter 3. Vector Spaces. 3.1 Images and Image Arithmetic Chpter 3 Vetor Spes In Chpter 2, we sw tht the set of imges possessed numer of onvenient properties. It turns out tht ny set tht possesses similr onvenient properties n e nlyzed in similr wy. In liner

More information

System Validation (IN4387) November 2, 2012, 14:00-17:00

System Validation (IN4387) November 2, 2012, 14:00-17:00 System Vlidtion (IN4387) Novemer 2, 2012, 14:00-17:00 Importnt Notes. The exmintion omprises 5 question in 4 pges. Give omplete explntion nd do not onfine yourself to giving the finl nswer. Good luk! Exerise

More information

How do we solve these things, especially when they get complicated? How do we know when a system has a solution, and when is it unique?

How do we solve these things, especially when they get complicated? How do we know when a system has a solution, and when is it unique? XII. LINEAR ALGEBRA: SOLVING SYSTEMS OF EQUATIONS Tody we re going to tlk out solving systems of liner equtions. These re prolems tht give couple of equtions with couple of unknowns, like: 6= x + x 7=

More information

Matrices SCHOOL OF ENGINEERING & BUILT ENVIRONMENT. Mathematics (c) 1. Definition of a Matrix

Matrices SCHOOL OF ENGINEERING & BUILT ENVIRONMENT. Mathematics (c) 1. Definition of a Matrix tries Definition of tri mtri is regulr rry of numers enlosed inside rkets SCHOOL OF ENGINEERING & UIL ENVIRONEN Emple he following re ll mtries: ), ) 9, themtis ), d) tries Definition of tri Size of tri

More information

I1 = I2 I1 = I2 + I3 I1 + I2 = I3 + I4 I 3

I1 = I2 I1 = I2 + I3 I1 + I2 = I3 + I4 I 3 2 The Prllel Circuit Electric Circuits: Figure 2- elow show ttery nd multiple resistors rrnged in prllel. Ech resistor receives portion of the current from the ttery sed on its resistnce. The split is

More information

Bases for Vector Spaces

Bases for Vector Spaces Bses for Vector Spces 2-26-25 A set is independent if, roughly speking, there is no redundncy in the set: You cn t uild ny vector in the set s liner comintion of the others A set spns if you cn uild everything

More information

Engr354: Digital Logic Circuits

Engr354: Digital Logic Circuits Engr354: Digitl Logi Ciruits Chpter 4: Logi Optimiztion Curtis Nelson Logi Optimiztion In hpter 4 you will lern out: Synthesis of logi funtions; Anlysis of logi iruits; Tehniques for deriving minimum-ost

More information

22: Union Find. CS 473u - Algorithms - Spring April 14, We want to maintain a collection of sets, under the operations of:

22: Union Find. CS 473u - Algorithms - Spring April 14, We want to maintain a collection of sets, under the operations of: 22: Union Fin CS 473u - Algorithms - Spring 2005 April 14, 2005 1 Union-Fin We wnt to mintin olletion of sets, uner the opertions of: 1. MkeSet(x) - rete set tht ontins the single element x. 2. Fin(x)

More information

2.4 Linear Inequalities and Interval Notation

2.4 Linear Inequalities and Interval Notation .4 Liner Inequlities nd Intervl Nottion We wnt to solve equtions tht hve n inequlity symol insted of n equl sign. There re four inequlity symols tht we will look t: Less thn , Less thn or

More information

Technische Universität München Winter term 2009/10 I7 Prof. J. Esparza / J. Křetínský / M. Luttenberger 11. Februar Solution

Technische Universität München Winter term 2009/10 I7 Prof. J. Esparza / J. Křetínský / M. Luttenberger 11. Februar Solution Tehnishe Universität Münhen Winter term 29/ I7 Prof. J. Esprz / J. Křetínský / M. Luttenerger. Ferur 2 Solution Automt nd Forml Lnguges Homework 2 Due 5..29. Exerise 2. Let A e the following finite utomton:

More information

AP CALCULUS Test #6: Unit #6 Basic Integration and Applications

AP CALCULUS Test #6: Unit #6 Basic Integration and Applications AP CALCULUS Test #6: Unit #6 Bsi Integrtion nd Applitions A GRAPHING CALCULATOR IS REQUIRED FOR SOME PROBLEMS OR PARTS OF PROBLEMS IN THIS PART OF THE EXAMINATION. () The ext numeril vlue of the orret

More information

April 8, 2017 Math 9. Geometry. Solving vector problems. Problem. Prove that if vectors and satisfy, then.

April 8, 2017 Math 9. Geometry. Solving vector problems. Problem. Prove that if vectors and satisfy, then. pril 8, 2017 Mth 9 Geometry Solving vetor prolems Prolem Prove tht if vetors nd stisfy, then Solution 1 onsider the vetor ddition prllelogrm shown in the Figure Sine its digonls hve equl length,, the prllelogrm

More information

Trigonometry Revision Sheet Q5 of Paper 2

Trigonometry Revision Sheet Q5 of Paper 2 Trigonometry Revision Sheet Q of Pper The Bsis - The Trigonometry setion is ll out tringles. We will normlly e given some of the sides or ngles of tringle nd we use formule nd rules to find the others.

More information

Unit 4. Combinational Circuits

Unit 4. Combinational Circuits Unit 4. Comintionl Ciruits Digitl Eletroni Ciruits (Ciruitos Eletrónios Digitles) E.T.S.I. Informáti Universidd de Sevill 5/10/2012 Jorge Jun 2010, 2011, 2012 You re free to opy, distriute

More information

INTEGRATION. 1 Integrals of Complex Valued functions of a REAL variable

INTEGRATION. 1 Integrals of Complex Valued functions of a REAL variable INTEGRATION NOTE: These notes re supposed to supplement Chpter 4 of the online textbook. 1 Integrls of Complex Vlued funtions of REAL vrible If I is n intervl in R (for exmple I = [, b] or I = (, b)) nd

More information

Nondeterministic Finite Automata

Nondeterministic Finite Automata Nondeterministi Finite utomt The Power of Guessing Tuesdy, Otoer 4, 2 Reding: Sipser.2 (first prt); Stoughton 3.3 3.5 S235 Lnguges nd utomt eprtment of omputer Siene Wellesley ollege Finite utomton (F)

More information

CSE 332. Sorting. Data Abstractions. CSE 332: Data Abstractions. QuickSort Cutoff 1. Where We Are 2. Bounding The MAXIMUM Problem 4

CSE 332. Sorting. Data Abstractions. CSE 332: Data Abstractions. QuickSort Cutoff 1. Where We Are 2. Bounding The MAXIMUM Problem 4 Am Blnk Leture 13 Winter 2016 CSE 332 CSE 332: Dt Astrtions Sorting Dt Astrtions QuikSort Cutoff 1 Where We Are 2 For smll n, the reursion is wste. The onstnts on quik/merge sort re higher thn the ones

More information

Parse trees, ambiguity, and Chomsky normal form

Parse trees, ambiguity, and Chomsky normal form Prse trees, miguity, nd Chomsky norml form In this lecture we will discuss few importnt notions connected with contextfree grmmrs, including prse trees, miguity, nd specil form for context-free grmmrs

More information

Green s Theorem. (2x e y ) da. (2x e y ) dx dy. x 2 xe y. (1 e y ) dy. y=1. = y e y. y=0. = 2 e

Green s Theorem. (2x e y ) da. (2x e y ) dx dy. x 2 xe y. (1 e y ) dy. y=1. = y e y. y=0. = 2 e Green s Theorem. Let be the boundry of the unit squre, y, oriented ounterlokwise, nd let F be the vetor field F, y e y +, 2 y. Find F d r. Solution. Let s write P, y e y + nd Q, y 2 y, so tht F P, Q. Let

More information

Polynomials. Polynomials. Curriculum Ready ACMNA:

Polynomials. Polynomials. Curriculum Ready ACMNA: Polynomils Polynomils Curriulum Redy ACMNA: 66 www.mthletis.om Polynomils POLYNOMIALS A polynomil is mthemtil expression with one vrile whose powers re neither negtive nor frtions. The power in eh expression

More information

Logarithms LOGARITHMS.

Logarithms LOGARITHMS. Logrithms LOGARITHMS www.mthletis.om.u Logrithms LOGARITHMS Logrithms re nother method to lulte nd work with eponents. Answer these questions, efore working through this unit. I used to think: In the

More information

Lesson 2: The Pythagorean Theorem and Similar Triangles. A Brief Review of the Pythagorean Theorem.

Lesson 2: The Pythagorean Theorem and Similar Triangles. A Brief Review of the Pythagorean Theorem. 27 Lesson 2: The Pythgoren Theorem nd Similr Tringles A Brief Review of the Pythgoren Theorem. Rell tht n ngle whih mesures 90º is lled right ngle. If one of the ngles of tringle is right ngle, then we

More information

= state, a = reading and q j

= state, a = reading and q j 4 Finite Automt CHAPTER 2 Finite Automt (FA) (i) Derterministi Finite Automt (DFA) A DFA, M Q, q,, F, Where, Q = set of sttes (finite) q Q = the strt/initil stte = input lphet (finite) (use only those

More information

Section 1.3 Triangles

Section 1.3 Triangles Se 1.3 Tringles 21 Setion 1.3 Tringles LELING TRINGLE The line segments tht form tringle re lled the sides of the tringle. Eh pir of sides forms n ngle, lled n interior ngle, nd eh tringle hs three interior

More information

Generalization of 2-Corner Frequency Source Models Used in SMSIM

Generalization of 2-Corner Frequency Source Models Used in SMSIM Generliztion o 2-Corner Frequeny Soure Models Used in SMSIM Dvid M. Boore 26 Mrh 213, orreted Figure 1 nd 2 legends on 5 April 213, dditionl smll orretions on 29 My 213 Mny o the soure spetr models ville

More information

Fast Boolean Algebra

Fast Boolean Algebra Fst Boolen Alger ELEC 267 notes with the overurden removed A fst wy to lern enough to get the prel done honorly Printed; 3//5 Slide Modified; Jnury 3, 25 John Knight Digitl Circuits p. Fst Boolen Alger

More information

Lecture 6: Coding theory

Lecture 6: Coding theory Leture 6: Coing theory Biology 429 Crl Bergstrom Ferury 4, 2008 Soures: This leture loosely follows Cover n Thoms Chpter 5 n Yeung Chpter 3. As usul, some of the text n equtions re tken iretly from those

More information

TIME AND STATE IN DISTRIBUTED SYSTEMS

TIME AND STATE IN DISTRIBUTED SYSTEMS Distriuted Systems Fö 5-1 Distriuted Systems Fö 5-2 TIME ND STTE IN DISTRIUTED SYSTEMS 1. Time in Distriuted Systems Time in Distriuted Systems euse eh mhine in distriuted system hs its own lok there is

More information

Lecture Notes No. 10

Lecture Notes No. 10 2.6 System Identifition, Estimtion, nd Lerning Leture otes o. Mrh 3, 26 6 Model Struture of Liner ime Invrint Systems 6. Model Struture In representing dynmil system, the first step is to find n pproprite

More information

Electromagnetism Notes, NYU Spring 2018

Electromagnetism Notes, NYU Spring 2018 Eletromgnetism Notes, NYU Spring 208 April 2, 208 Ation formultion of EM. Free field desription Let us first onsider the free EM field, i.e. in the bsene of ny hrges or urrents. To tret this s mehnil system

More information

Math 32B Discussion Session Week 8 Notes February 28 and March 2, f(b) f(a) = f (t)dt (1)

Math 32B Discussion Session Week 8 Notes February 28 and March 2, f(b) f(a) = f (t)dt (1) Green s Theorem Mth 3B isussion Session Week 8 Notes Februry 8 nd Mrh, 7 Very shortly fter you lerned how to integrte single-vrible funtions, you lerned the Fundmentl Theorem of lulus the wy most integrtion

More information

10. AREAS BETWEEN CURVES

10. AREAS BETWEEN CURVES . AREAS BETWEEN CURVES.. Ares etween curves So res ove the x-xis re positive nd res elow re negtive, right? Wrong! We lied! Well, when you first lern out integrtion it s convenient fiction tht s true in

More information

Plotting Ordered Pairs Using Integers

Plotting Ordered Pairs Using Integers SAMPLE Plotting Ordered Pirs Using Integers Ple two elsti nds on geoord to form oordinte xes shown on the right to help you solve these prolems.. Wht letter of the lphet does eh set of pirs nme?. (, )

More information

Let's start with an example:

Let's start with an example: Finite Automt Let's strt with n exmple: Here you see leled circles tht re sttes, nd leled rrows tht re trnsitions. One of the sttes is mrked "strt". One of the sttes hs doule circle; this is terminl stte

More information

Counting Paths Between Vertices. Isomorphism of Graphs. Isomorphism of Graphs. Isomorphism of Graphs. Isomorphism of Graphs. Isomorphism of Graphs

Counting Paths Between Vertices. Isomorphism of Graphs. Isomorphism of Graphs. Isomorphism of Graphs. Isomorphism of Graphs. Isomorphism of Graphs Isomorphism of Grphs Definition The simple grphs G 1 = (V 1, E 1 ) n G = (V, E ) re isomorphi if there is ijetion (n oneto-one n onto funtion) f from V 1 to V with the property tht n re jent in G 1 if

More information

p-adic Egyptian Fractions

p-adic Egyptian Fractions p-adic Egyptin Frctions Contents 1 Introduction 1 2 Trditionl Egyptin Frctions nd Greedy Algorithm 2 3 Set-up 3 4 p-greedy Algorithm 5 5 p-egyptin Trditionl 10 6 Conclusion 1 Introduction An Egyptin frction

More information

7.1 Integral as Net Change and 7.2 Areas in the Plane Calculus

7.1 Integral as Net Change and 7.2 Areas in the Plane Calculus 7.1 Integrl s Net Chnge nd 7. Ares in the Plne Clculus 7.1 INTEGRAL AS NET CHANGE Notecrds from 7.1: Displcement vs Totl Distnce, Integrl s Net Chnge We hve lredy seen how the position of n oject cn e

More information

Ch. 2.3 Counting Sample Points. Cardinality of a Set

Ch. 2.3 Counting Sample Points. Cardinality of a Set Ch..3 Counting Smple Points CH 8 Crdinlity of Set Let S e set. If there re extly n distint elements in S, where n is nonnegtive integer, we sy S is finite set nd n is the rdinlity of S. The rdinlity of

More information

Pythagoras Theorem. Pythagoras Theorem. Curriculum Ready ACMMG: 222, 245.

Pythagoras Theorem. Pythagoras Theorem. Curriculum Ready ACMMG: 222, 245. Pythgors Theorem Pythgors Theorem Curriulum Redy ACMMG:, 45 www.mthletis.om Fill in these spes with ny other interesting fts you n find out Pythgors. In the world of Mthemtis, Pythgors is legend. He lived

More information

University of Sioux Falls. MAT204/205 Calculus I/II

University of Sioux Falls. MAT204/205 Calculus I/II University of Sioux Flls MAT204/205 Clulus I/II Conepts ddressed: Clulus Textook: Thoms Clulus, 11 th ed., Weir, Hss, Giordno 1. Use stndrd differentition nd integrtion tehniques. Differentition tehniques

More information

Designing Information Devices and Systems I Spring 2018 Homework 7

Designing Information Devices and Systems I Spring 2018 Homework 7 EECS 16A Designing Informtion Devices nd Systems I Spring 2018 omework 7 This homework is due Mrch 12, 2018, t 23:59. Self-grdes re due Mrch 15, 2018, t 23:59. Sumission Formt Your homework sumission should

More information

QUADRATIC EQUATION. Contents

QUADRATIC EQUATION. Contents QUADRATIC EQUATION Contents Topi Pge No. Theory 0-04 Exerise - 05-09 Exerise - 09-3 Exerise - 3 4-5 Exerise - 4 6 Answer Key 7-8 Syllus Qudrti equtions with rel oeffiients, reltions etween roots nd oeffiients,

More information

Nondeterministic Automata vs Deterministic Automata

Nondeterministic Automata vs Deterministic Automata Nondeterministi Automt vs Deterministi Automt We lerned tht NFA is onvenient model for showing the reltionships mong regulr grmmrs, FA, nd regulr expressions, nd designing them. However, we know tht n

More information

Semantic Analysis. CSCI 3136 Principles of Programming Languages. Faculty of Computer Science Dalhousie University. Winter Reading: Chapter 4

Semantic Analysis. CSCI 3136 Principles of Programming Languages. Faculty of Computer Science Dalhousie University. Winter Reading: Chapter 4 Semnti nlysis SI 16 Priniples of Progrmming Lnguges Fulty of omputer Siene Dlhousie University Winter 2012 Reding: hpter 4 Motivtion Soure progrm (hrter strem) Snner (lexil nlysis) Front end Prse tree

More information

Bridging the gap: GCSE AS Level

Bridging the gap: GCSE AS Level Bridging the gp: GCSE AS Level CONTENTS Chpter Removing rckets pge Chpter Liner equtions Chpter Simultneous equtions 8 Chpter Fctors 0 Chpter Chnge the suject of the formul Chpter 6 Solving qudrtic equtions

More information

Discrete Structures, Test 2 Monday, March 28, 2016 SOLUTIONS, VERSION α

Discrete Structures, Test 2 Monday, March 28, 2016 SOLUTIONS, VERSION α Disrete Strutures, Test 2 Mondy, Mrh 28, 2016 SOLUTIONS, VERSION α α 1. (18 pts) Short nswer. Put your nswer in the ox. No prtil redit. () Consider the reltion R on {,,, d with mtrix digrph of R.. Drw

More information

ILLUSTRATING THE EXTENSION OF A SPECIAL PROPERTY OF CUBIC POLYNOMIALS TO NTH DEGREE POLYNOMIALS

ILLUSTRATING THE EXTENSION OF A SPECIAL PROPERTY OF CUBIC POLYNOMIALS TO NTH DEGREE POLYNOMIALS ILLUSTRATING THE EXTENSION OF A SPECIAL PROPERTY OF CUBIC POLYNOMIALS TO NTH DEGREE POLYNOMIALS Dvid Miller West Virgini University P.O. BOX 6310 30 Armstrong Hll Morgntown, WV 6506 millerd@mth.wvu.edu

More information

Lecture 3. Introduction digital logic. Notes. Notes. Notes. Representations. February Bern University of Applied Sciences.

Lecture 3. Introduction digital logic. Notes. Notes. Notes. Representations. February Bern University of Applied Sciences. Lecture 3 Ferury 6 ern University of pplied ciences ev. f57fc 3. We hve seen tht circuit cn hve multiple (n) inputs, e.g.,, C, We hve lso seen tht circuit cn hve multiple (m) outputs, e.g. X, Y,, ; or

More information

Section 6: Area, Volume, and Average Value

Section 6: Area, Volume, and Average Value Chpter The Integrl Applied Clculus Section 6: Are, Volume, nd Averge Vlue Are We hve lredy used integrls to find the re etween the grph of function nd the horizontl xis. Integrls cn lso e used to find

More information