BF904A; BF904AR; BF904AWR

Transcription

1 BF9; BF9R; BF9WR Rev. 3 November 27 Product data sheet Dear customer, IMPORTNT NOTICE s from October st, 26 Philips Semiconductors has a new trade name - NXP Semiconductors, which will be used in future data sheets together with new contact details. In data sheets where the previous Philips references remain, please use the new links as shown below. use use (Internet) sales.addresses@ use salesaddresses@nxp.com ( ) The copyright notice at the bottom of each page (or elsewhere in the document, depending on the version) - Koninklijke Philips Electronics N.. (year). ll rights reserved - is replaced with: - NXP B.. (year). ll rights reserved. - If you have any questions related to the data sheet, please contact our nearest sales office via or phone (details via salesaddresses@nxp.com). Thank you for your cooperation and understanding, NXP Semiconductors

2 BF9; BF9R; BF9WR FETURES Specially designed for use at 5 supply voltage Short channel transistor with high transfer admittance to input capacitance ratio Low noise gain controlled amplifier up to GHz Superior cross-modulation performance during GC. PINNING PIN DESCRIPTION source 2 drain 3 gate 2 gate handbook, 2 columns 3 2 Top view MSB BF9 marking code: %M7. PPLICTIONS Fig. Simplified outline (SOT3B). HF and UHF applications with 3 to 7 supply voltage such as television tuners and professional communications equipment. handbook, 2 columns 3 halfpage 3 DESCRIPTION Enhancement type field-effect transistors. The transistors consist of an amplifier MOS-FET with source and substrate interconnected and an internal bias circuit to ensure good cross-modulation performance during GC. The BF9, BF9R and BF9WR are encapsulated in the SOT3B, SOT3R and SOT33R plastic packages respectively. BF9R marking code: %M8. Fig.2 2 Top view MSB35 Simplified outline (SOT3R). BF9WR marking code: MH. Fig.3 2 Top view MSB82 Simplified outline (SOT33R). QUICK REFERENCE DT SYMBOL PRMETER CONDITIONS MIN. TYP. MX. UNIT DS drain-source voltage 7 I D drain current 3 m P tot total power dissipation T s C 2 mw y fs forward transfer admittance ms C ig-ss input capacitance at gate pf C rss reverse transfer capacitance f = MHz ff F noise figure f = 8 MHz 2 db T j operating junction temperature 5 C CUTION This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. For further information, refer to Philips specs.: SNW-EQ-68, SNW-FQ-32 and SNW-FQ-32B. Rev. - 3 November 27 2 of 5

3 BF9; BF9R; BF9WR LIMITING LUES In accordance with the bsolute Maximum Rating System (IEC 3). SYMBOL PRMETER CONDITIONS MIN. MX. UNIT DS drain-source voltage 7 I D drain current 3 m I G gate current ± m I G2 gate 2 current ± m P tot total power dissipation T s C; note ; see Fig. 2 mw T stg storage temperature C T j operating junction temperature 5 C Note. T s is the temperature of the soldering point of the source lead. 25 P tot (mw) 2 MGL T s ( C) Fig. Power derating curve. Rev. - 3 November 27 3 of 5

4 BF9; BF9R; BF9WR THERML CHRCTERISTICS SYMBOL PRMETER CONDITIONS LUE UNIT R th j-s thermal resistance from junction to soldering point note 2 K/W Note. Soldering point of the source lead. STTIC CHRCTERISTICS T j =25 C unless otherwise specified. SYMBOL PRMETER CONDITIONS MIN. MX. UNIT (BR)G-SS gate -source breakdown voltage G2-S = DS = ; I G-S = m 6 5 (BR)G2-SS gate 2-source breakdown voltage G-S = DS = ; I G2-S = m 6 5 (F)S-G forward source-gate voltage G2-S = DS = ; I S-G = m.5.5 (F)S-G2 forward source-gate 2 voltage G-S = DS = ; I S-G2 = m.5.5 G-S(th) gate -source threshold voltage G2-S =; DS =5; I D =2µ.3 G2-S(th) gate 2-source threshold voltage G-S = DS =5; I D =2µ.3.2 I DSX drain-source current G2-S =; DS =5; R G = 2 kω; note Note. R G connects gate to GG = 5 ; see Fig m I G-SS gate cut-off current G2-S = DS = ; G-S =5 5 n I G2-SS gate 2 cut-off current G-S = DS = ; G2-S =5 5 n DYNMIC CHRCTERISTICS Common source; T amb =25 C; DS = 5 ; G2-S = ; I D = m; unless otherwise specified. SYMBOL PRMETER CONDITIONS MIN. TYP. MX. UNIT y fs forward transfer admittance pulsed; T j =25 C ms C ig-s input capacitance at gate f = MHz pf C ig2-s input capacitance at gate 2 f = MHz.5 2 pf C os drain-source capacitance f = MHz..7 pf C rs reverse transfer capacitance f = MHz ff F noise figure f = 2 MHz; G S = 2 ms; B S =B Sopt.5 db f = 8 MHz; G S =G Sopt ; B S =B Sopt db Rev. - 3 November 27 of 5

5 BF9; BF9R; BF9WR Y fs (ms) 3 MLD268 handbook, gain halfpage reduction (db) MR o T j ( C) GC () f = 5 MHz. Fig.5 Transfer admittance as a function of the junction temperature; typical values. Fig.6 Typical gain reduction as a function of the GC voltage; see Fig.2. 2 unw (db µ ) MR77 2 I D (m) 5 MLD27 = G2 S gain reduction (db) DS = 5 ; GG = 5 ; f w = 5 MHz. f unw = 6 MHz; T amb =25 C; R G = 2 kω G S () Fig.7 Unwanted voltage for % cross-modulation as a function of gain reduction; typical values; see Fig.2. DS =5. T j =25 C. Fig.8 Transfer characteristics; typical values. Rev. - 3 November 27 5 of 5

6 BF9; BF9R; BF9WR 2 I D (m) 6 G S =..3 MLD269 5 I G (µ) MLD27 G2 S = DS () G S () G2-S =. T j =25 C. Fig.9 Output characteristics; typical values. DS =5. T j =25 C. Fig. Gate current as a function of gate voltage; typical values. y fs (ms) 3 MLD272 G2 S = I D (m) 2 MLD I D (m) I G (µ) DS =5. T j =25 C. DS =5. G2-S =. T j =25 C. Fig. Forward transfer admittance as a function of drain current; typical values. Fig.2 Drain current as a function of gate current; typical values. Rev. - 3 November 27 6 of 5

7 BF9; BF9R; BF9WR 2 I D (m) 8 MLD275 2 I D (m) 5 R G = 7 kω 68 kω MLD27 82 kω kω 2 kω 5 kω 5 8 kω 22 kω GG () GG = DS () DS = 5 ; G2-S = ; T j =25 C. R G = 2 kω (connected to GG ); see Fig.2. Fig.3 Drain current as a function of gate supply voltage (= GG ); typical values. G2-S = ; T j =25 C. R G connected to GG ; see Fig.2. Fig. Drain current as a function of gate (= GG ) and drain supply voltage; typical values. 2 I D (m) 8 MLD276 GG = I G (µ) 3 MLB95 GG = G2 S () 2 6 G2 S () DS = 5 ; T j =25 C. R G = 2 kω (connected to GG ); see Fig.2. Fig.5 Drain current as a function of gate 2 voltage; typical values. DS = 5 ; T j =25 C. R G = 2 kω (connected to GG ); see Fig.2. Fig.6 Gate current as a function of gate 2 voltage; typical values. Rev. - 3 November 27 7 of 5

8 BF9; BF9R; BF9WR 2 MLD277 3 MLD278 3 y is (ms) y rs (µs) ϕrs (deg) 2 ϕrs 2 b is y rs g is 2 f (MHz) 3 2 f (MHz) 3 DS = 5 ; G2 =. I D = m; T amb =25 C. DS = 5 ; G2 =. I D = m; T amb =25 C. Fig.7 Input admittance as a function of frequency; typical values. Fig.8 Reverse transfer admittance and phase as a function of frequency; typical values. 2 MLD279 2 MGL6 y fs (ms) y fs ϕ fs (deg) y os (ms) b os ϕ fs g os 2 f (MHz) f (MHz) 3 DS = 5 ; G2 =. I D = m; T amb =25 C. DS = 5 ; G2 =. I D = m; T amb =25 C. Fig.9 Forward transfer admittance and phase as a function of frequency; typical values. Fig.2 Output admittance as a function of frequency; typical values. Rev. - 3 November 27 8 of 5

9 BF9; BF9R; BF9WR GC R k Ω C.7 nf C3 2 pf R GEN 5 Ω I R2 5 Ω C2.7 nf R G GG L DUT 5 nh C.7 nf DS R L 5 Ω MLD7 Fig.2 Cross-modulation test set-up. Rev. - 3 November 27 9 of 5

10 BF9; BF9R; BF9WR Table Scattering parameters: DS = 5 ; G2-S = ; I D = m; T amb =25 C f (MHz) MGNITUDE (ratio) S S 2 S 2 S 22 NGLE (deg) MGNITUDE (ratio) NGLE (deg) MGNITUDE (ratio) NGLE (deg) MGNITUDE (ratio) NGLE (deg) Table 2 Noise data: DS = 5 ; G2-S = ; I D = m; T amb =25 C f (MHz) F min (db) (ratio) Γ opt (deg) Rn (Ω) Rev. - 3 November 27 of 5

11 BF9; BF9R; BF9WR PCKGE OUTLINES Plastic surface mounted package; leads SOT3B D B E X y v M H E e b p w M B 3 Q 2 c b Lp e detail X 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm..9 max. b p.8.38 b c.5.9 D E..2 e.9 e.7 H E L p.5.5 Q.55.5 v.2 w y.. OUTLINE ERSION REFERENCES IEC JEDEC EIJ EUROPEN PROJECTION ISSUE DTE SOT3B Rev. - 3 November 27 of 5

12 BF9; BF9R; BF9WR Plastic surface mounted package; reverse pinning; leads SOT3R D B E X y v M H E e b p w M B 3 Q 2 c b Lp e detail X 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm..9 max. b p.8.38 b c.5.9 D E..2 e.9 e.7 H E L p Q.5.25 v.2 w y.. OUTLINE ERSION REFERENCES IEC JEDEC EIJ EUROPEN PROJECTION ISSUE DTE SOT3R Rev. - 3 November 27 2 of 5

13 BF9; BF9R; BF9WR Plastic surface mounted package; reverse pinning; leads SOT33R D B E X y H E v M e 3 Q 2 c w M B b p b Lp e detail X 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT max mm...8 b p b c D E e e H E Lp Q v w y. OUTLINE ERSION REFERENCES IEC JEDEC EIJ EUROPEN PROJECTION ISSUE DTE SOT33R Rev. - 3 November 27 3 of 5

14 BF9; BF9R; BF9WR Legal information Data sheet status Document status [][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Disclaimers General Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IEC 63) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. Contact information For additional information, please visit: For sales office addresses, send an to: salesaddresses@nxp.com Rev. - 3 November 27 of 5

15 BF9; BF9R; BF9WR Revision history Revision history Document ID Release date Data sheet status Change notice Supersedes BF9_R_WR_N_ 273 Product data sheet - BF9_R_WR_3 Modifications: Fig. and 2 on page 2; Figure note changed BF9_R_WR_ BF9_R_WR_N_2 ( ) BF9_R_WR_N_ Preliminary specification - BF9_R_WR_N_ ( ) BF9_R_WR_N_ ( ) 9983 Preliminary specification - - Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B ll rights reserved. For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com Date of release: 3 November 27 Document identifier: BF9_R_WR_N_

16 Mouser Electronics uthorized Distributor Click to iew Pricing, Inventory, Delivery & Lifecycle Information: NXP: BF9,25 BF9R,25 BF9WR,5