System Roadmap. Qubits 2018 D-Wave Users Conference Knoxville. Jed Whittaker D-Wave Systems Inc. September 25, 2018

Transcription

1 System Roadmap Qubits 2018 D-Wave Users Conference Knoxville Jed Whittaker D-Wave Systems Inc. September 25, 2018

2 Overview Where are we today? annealing options reverse annealing quantum materials simulation Where are we going? next generation processor - improved connectivity lower noise new Hamiltonian 1 / 22

3 Overview Where are we today? annealing options reverse annealing quantum materials simulation Where are we going? next generation processor - improved connectivity lower noise new Hamiltonian 2 / 22

4 The goal of quantum annealing (QA): model the Hamiltonian [ H S (s) = 1 2 A(s) σ x,i + B(s) i Energy (GHz) A/h(GHz) i s B/h(GHz) ] h i σ z,i + J ij σ z,i σ z,j i<j a Φ 2X Φ 1X Josephson junction Φ 2 Φ 1 "spin-up" circulating current "spin-down" circulating current T. Kadowaki and H. Nishimori, PRE, 58(5), pp , (1998) E. Farhi, et al., Science 292, 472 (2001) W. Kaminsky, S. Lloyd, T. Orlando, arxiv:quant-ph/ , Scalable Superconducting Architecture for Adiabatic Quantum Computation 3 / 22

5 D-Wave 2000Q quantum annealing processor Quantum processing unit = QPU 128,472 Josephson junctions 18,305 composite flux DACs 10,960 QFP shift register stages 4 / 22

6 2000 qubits: Chimera architecture at C16 scale D-Wave One D-Wave Two D-Wave 2X 2000Q Qubits (max) ,152 2,048 Couplers 352 1,472 3, Target Qubit Yield 84% 95%+ 95%+ 97%+ Qubit degree Chimera, degree = 6 5 / 22

7 2000Q: New annealing features Anneal Offsets 12 A(s) dashed, B(s) solid Anneal Pause 6 standard 20 µs annealing pattern Energy (GHz) B(t) (GHz) B(t) (GHz) time (µs) 20 µs anneal with 100 µs pause at s = s time (µs) Give user per-qubit control over transverse field Anneal Quench Specify start and duration of global anneal pause Reverse Anneal Specify when to abruptly quench transverse field A new quantum machine instruction! 6 / 22

8 Reverse anneal enables hybrid algorithms A new Quantum Machine Instruction (QMI) 1. Initialize given classical state 2. Increase transverse field to specified value s* 3. wait for dwell time 4. anneal forward to complete Tunable local search N. Chancellor Modernizing quantum annealing using local searches, New J. Phys. 19, (2017) Reverse Quantum Annealing for Local Refinement of Solutions, D-Wave Whitepaper, 7 / 22

9 Quantum simulation: flux qubit can behave like a quantum Ising spin a Φ 1X "spin-up" circulating current U b Φ 2X Josephson junction Φ 2 Φ 1 H q = 1 2 "spin-down" circulating current [ ɛq σ z + q σ x ] δu 2h Φ 1 H QS = gµ B [ B σ z + B t σ x ] B ll B t where ɛ q = 2 I p q Φ x q = h i σ z 1 2 σ x Parameter QUBIT Quantum Ising Spin bias energy ɛ q /2 gµ B B or h tunneling energy q /2 gµ B B t magnetic moment gµ B Binary information encoded in flux basis: 0 and 1 I p q 8 / 22

10 Quantum simulation of transverse field cubic Ising lattice (R. Harris) H 3D (s) = Γ(s) 2 i σi x + J (s) J ij σi z σz j i,j 3D transverse Ising models embedded in D-Wave QA processor Quantitative agreement with locations of phase transitions: vs. disorder (doping p) & transverse field Γ χafm 10 5 (Φ 1 0 ) s p = 0 p = 0.05 p = 0.1 p = 0.15 p = 0.2 R. Harris, et al., Phase transitions in a programmable quantum spin glass simulator Science (2018) 9 / 22

11 Quantum simulation of topological phase transition (A. King) 0.7 PM critical PM Ordered vortex anti-vortex Γ/J A. King, et al., Observation of topological phenomena in a programmable lattice of 1,800 qubits Nature (2018) T/J mk Upper transition s = 0.30 s = 0.25 KT s = 0.20 PM Order parameter m QMC QA Annealing parameter s 10 / 22

12 Overview Where are we today? annealing options reverse annealing quantum materials simulation Where are we going? next generation processor - improved connectivity lower noise new Hamiltonian 11 / 22

13 Progression of processor scale over time 12 / 22

14 Important processor characteristics number of qubits How large of a problem can be posed? connectivity How feasible is it to solve my problem? noise How precisely can a problem be posed? How well will QA perform? 13 / 22

15 Next generation architecture significantly enhances connectivity Chimera C16 - DW 2000Q Pegasus P6-680 Qubit Prototype I most significant architecture change since first processor D-Wave One I enabled by major technology changes in fabrication stack I have demonstrated P6 prototype 14 / 22

16 Pegasus architecture significantly enhances connectivity Pegasus P6-680 Qubit Prototype Chimera C16 - DW 2000Q Device Count Qubits Couplers max degree C P P / 22

17 Pegasus unit tile Chimera - C4 Pegasus - P1 16 / 22

18 Basic graph embedding statistics C16 P6 P16 Complete Graph 64 (17) 60 (7) 180 (17) Complete Bipartite 64x64 (16) 52x52 (5) 172x172 (15) Cubic Lattice 8x8x8 (4) 5x5x12 (2) 15x15x12 (2) Factoring Circuit 16-bit (16) 10-bit (5) 30-bit (15) Grid with Diagonals 16x16 (6) 15x15 (6) 45x45 (6) (max chain length in blue) 17 / 22

19 Noise and coherence are important for quantum annealing Lower intrinsic device noise will allow: more precise control of annealing parameters more multiqubit tunneling faster calibration figure from Denchev, et al., PRX (2016), What is the Computational Value of Finite-Range Tunneling? 18 / 22

20 Coupling to the environment transition width (µφ0) mK 15mK 20mK 25mK 30mK measure qubit transition widths and temperatures long anneals couple to the environment, short anneals do not qualitative behaviour captured by Bloch-Redfield Model mK 15mK 20mK 25mK 30mK anneal time (µs) transition width (µφ0) anneal time (µs) 19 / 22

21 Continuing research on lower noise materials Examining alternatives conductor material & processing dielectric material & processing 20 / 22

22 New Hamiltonian A(s) H(s) = 2 " # B(s) σx,i + 2 hi σz,i + Jij σz,i σz,j i i i<j 21 / 22

23 New Hamiltonian A(s) H(s) = 2 " # B(s) σx,i + 2 hi σz,i + Jij σz,i σz,j +Jy σy,i σy,j i i i<j i<j 21 / 22

24 Summary D-Wave 2000Q processor Pegasus architecture significantly increases connectivity continued progress on noise & coherence investigating a new Hamiltonian 22 / 22