ECE251 VLSI System Design Spring Homework 1. Jinfeng Liu

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1 ECE251 VLSI System Design Spring 2000 Homework 1 Jinfeng Liu /27/2000

2 Problem 1: Procedure of solutions 1. Determine β n β n = An * C L / t df Ar = 1 2n (1 n) ln (2(1 n) V 0) 0) Vdd(1 n) V [ ] Given t df = 1.5ns, C L = 4pF, V dd = 3.3v, n = 0.1, V0 = 0.5 β n = e Determine W/L β n = µ ε/t ox * (W/L) In example of text book, (µ ε/t ox ) = 88.5 ua/v 2 for ntransistor (1u technology). Assume this value can approximately vary from ua/v 2, then the range of W/L is about To make sure the timing constraint is satisfied, larger (W/L) is chosen. 3. Layout design Since both transistors are quite large, I intend to make them in a relatively compact area. I have W/L = 44.5 for ntransistor and W/L=105.5 for ptransistor. Larger W/L will make shorter delay time, but power consumption is also going higher. Here are the screen shot and postscript file generated by Magic.

3 4. Simulation a. Irsim simulation The circuit is logically correct. (using HP35.PRM file). b. Spice simulation Load capacitor CL = 4PF is added between output and GND. The (W/L) value is extracted as W=89, L=2 for ntransistor and W=209, L=2 for ptransistor. Power consumption and switching transition analysis are made. * HSPICE file created from inv.ext - technology: scmos.lib '/users/kurdahi2/hspice/c10_rev6.1_hsp/hsp_dist/libs/hsp_nom_lib' N.LIB '/users/kurdahi2/hspice/c10_rev6.1_hsp/hsp_dist/libs/hsp_nom_lib' P.option scale=0.2u VCC Vdd GND DC 3.3 Vin in GND PULSE NS 0.1NS 0.1NS 6NS 12NS m0 out in Gnd Gnd n w=89 l=2 + ad=292 pd=102 as=458 ps=194 m1 out in Vdd Vdd p w=209 l=2 + ad=532 pd=222 as=848 ps=374 C0 out Gnd 4pf.TRAN 0.05NS 12NS.PRINT POWER.MEASURE TRAN avg_power AVG POWER from 0ns to 12ns.MEASURE TRAN max_power MAX POWER from 0ns to 12ns.MEASURE tdr TRIG V(in) VAL=1.65 FALL=1 TARG V(out) VAL=1.65 RISE=1.MEASURE tdf TRIG V(in) VAL=1.65 RISE=1 TARG V(out) VAL=1.65 FALL=1.MEASURE TRAN tr TRIG V(out) VAL=0.33 RISE=1 TARG V(out) VAL=2.97 RISE=1.MEASURE TRAN tf TRIG V(out) VAL=2.97 FALL=1 TARG V(out) VAL=0.33 FALL=1.OPTION POST = 2.END ** hspice subcircuit dictionary

4 i. Switching characteristics Spice output for delay: tdr= E-10 targ= E-09 trig= E-09 tdf= E-10 targ= E-09 trig= E-09 tr= E-09 targ= E-09 trig= E-09 tf= E-09 targ= E-09 trig= E-09 Tdrise = ns Tdfall = ns Delay time (Tdrise + Tdfall)/2 = ns Rise time = 1.57 ns Fall time = 1.36 ns The timing requirement is satisfied. ii. Power consumption

5 Spice output: avg_power= E-03 from= E+00 to= E-08 max_power= E-02 at= E-09 from= E+00 to= E-08 Average power = 3.79 mw Peak Power = 33.3 mw The power consumption is quite high because of low resistance. Problem 2 1. Layout design Use W=8, L=2 for ptransistror; W=4, L=2 for ntransistor. Five invertors are chained with the output of the last inverter looped back to input.

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7 2. Spice simulation: a. Spice file is shown. Some capacitors are generated due to the wire capacitance. This will cause extra wire delay that will increase the period of oscillation. Analysis to power consumption is made. * HSPICE file created from osc.ext - technology: scmos.lib '/users/kurdahi2/hspice/c10_rev6.1_hsp/hsp_dist/libs/hsp_nom_lib' N.LIB '/users/kurdahi2/hspice/c10_rev6.1_hsp/hsp_dist/libs/hsp_nom_lib' P.option scale=0.2u VCC Vdd GND DC 3.3.IC V(out)=0 m0 a_2_n39 out Vdd Vdd p w=8 l=2 + ad=40 pd=26 as=200 ps=130 m1 a_18_n39 a_2_n39 Vdd Vdd p w=8 l=2 + ad=40 pd=26 as=0 ps=0 m2 a_34_n39 a_18_n39 Vdd Vdd p w=8 l=2 + ad=40 pd=26 as=0 ps=0 m3 a_50_n39 a_34_n39 Vdd Vdd p w=8 l=2 + ad=40 pd=26 as=0 ps=0 m4 out a_50_n39 Vdd Vdd p w=8 l=2 + ad=40 pd=26 as=0 ps=0 m5 a_2_n39 out Gnd Gnd n w=4 l=2 + ad=20 pd=18 as=100 ps=90 m6 a_18_n39 a_2_n39 Gnd Gnd n w=4 l=2 + ad=20 pd=18 as=0 ps=0 m7 a_34_n39 a_18_n39 Gnd Gnd n w=4 l=2 + ad=20 pd=18 as=0 ps=0 m8 a_50_n39 a_34_n39 Gnd Gnd n w=4 l=2 + ad=20 pd=18 as=0 ps=0 m9 out a_50_n39 Gnd Gnd n w=4 l=2 + ad=20 pd=18 as=0 ps=0 C0 Gnd GND 3.5fF C1 Vdd GND 3.5fF C2 a_50_n39 GND 2.3fF C3 a_34_n39 GND 2.3fF C4 a_18_n39 GND 2.3fF C5 a_2_n39 GND 2.3fF C6 out GND 3.3fF.TRAN 0.01NS 8NS.PRINT POWER.MEASURE TRAN avg_power AVG POWER from 0ns to 8ns.MEASURE TRAN max_power MAX POWER from 0ns to 8ns.OPTION POST = 2.END ** hspice subcircuit dictionary

8 b. Simulation results (1) Oscillation wave form Period = 0.7ns. I also made analysis to the single inverter. The delay time of single inverter is around 0.05ns, which is less than 1/10 of the oscillation period. This is because of the extra delay made by additional wire capacitance. (2) Power consumption Spice output: avg_power= E-03 from= E+00 to= E-09 max_power= E-03 at= E+00 from= E+00 to= E-09 Average Power = 1.02 mw Peak Power = 1.37 mw

9 Comments Problem 1: C L = 4pF is quite large. This will cause longer RC delays of the gate. To compensate this negative effect, R should be made as small as possible. Large channel width W will contribute to smaller R. The ptransistor has W=159 and the ntransistor has W=61. The problem is that the power consumption is likely to rise. This can be seen from the spice result. The solution requires very large transistors. To avoid extra capacitance, I ve tried many different ways to confine large transistors in small size. I was interested in the ring topology for both p-transistor and n-transistor, as shown in the layout. The irsim proves the correct logic, but spice fails since ext2spice translates the channel length L to 1, although it is 2 in layout. This layout is mis-extracted by Magic. Problem 2: The characteristics of the oscillator can be used to measure some attributes of the materials. The period of oscillation is a direct measure of one gate delay, which is determined by some parameters of the material. I tried to make the layout size as compact as possible. For ptransistor, W=8, L=2; for ntransistor, W=4, L=2. The compact layout can reduce the wire capacitance thus reduce the gate delay of each single inverter. Therefore, the period of oscillation has less interference with the wiring. However, since there is still wire capacitance the oscillation period is larger than 10 times to the delay of single inverter. Increasing the channel width W can further shorten the single inverter delay, thus contribute to shorter period time. But it will result in a larger layout size, which is likely to have more wire capacitance. On the other hand, decreasing the channel width W will yield more compact layout, which will reduce the wire delay. However, smaller W will cause larger resistance R of transistors. Since the delay time is in proportion to the product of RC, narrowing down the channel width may not shorten the delay time. Compared to the layout in problem 1, since the channel width is much smaller, the peak power consumption is far less than the condition in problem 1.