EKV based L-DMOS Model update including internal temperatures

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1 ROBUSPIC (IST ) Deliverable D1.2 EKV based L-DMOS Model update including internal temperatures Yogesh Singh Chauhan, Costin Anghel, Francois Krummenacher, Adrian Ionescu and Michel Declercq Ecole Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland Renaud Gillon, Steven Frere and Bart Desoete AMI Semiconductor, Oudenaarde, Belgium Benoit Bakeroot University of Gent, Gent, Belgium Christian Maier Robert BOSCH, Reutlingen, Germany D1.2 EKV based L-DMOS Model update including internal temperatures 1

2 1. Introduction A new compact model for DC and AC circuit simulation of high voltage LDMOS transistor is presented. The modeling strategy is based on the core of the EKV physical MOSFET model for the intrinsic MOS while the drift segment is separately modeled. Selfheating effect is included by an equivalent electro-thermal circuit approach. The model is verified with both TCAD simulations and measured data and very good accuracy is observed for the DC component. The charge based AC compact modeling is valid for a wide range of gate and drain voltage. The special gate-to-source and gate-to-drain capacitance characteristics of LDMOS are accurately predicted. This model provides excellent trade-off between speed, convergence and accuracy, being suitable for circuit simulation in any regime of operation of HV MOSFETs including self-heating and impact ionization effect. 2. A New Compact Model The cross section of the LDMOS device is shown in fig.1. In order to keep the parasitic BJT off, the source and body are tied for these devices. It has been shown in [1] that the intrinsic drain voltage (V K ) always remains at low values for entire bias domain and the intrinsic MOS part can be accurately modeled using low voltage MOSFET model. Based on the intrinsic drain voltage as a unifying concept, we consider our device divided into an intrinsic MOSFET region and a drift region (see fig.2). The intrinsic transistor part is modeled using low voltage EKV model [2], which in comparison with other compact advanced models (such as BSIM or Philips), has the advantage of being physical and continuous in all regions of operation. The model has charge-based description and small number of parameters. Modeling of drift region is carried out using bias dependent resistance, which provides accuracy along with fast convergence. Lch Ldgo Ldfo Ldfp P+ N+ N+ Pbody NTUB NWELL BLN P-epi (a) (b) Fig. 1. Cross section of the L-DMOS architecture (n-channel) (a) schematic representation, (b) TCAD structure with x and y in µm. Fig. 2. Schematic representation corresponding to the modeling of the LDMOS transistor intrinsic MOS and drift part. D1.2 EKV based L-DMOS Model update including internal temperatures 2

3 The total gate charge is the sum of gate charge associated with the intrinsic MOS and the drift region. The MOS gate charge can be expressed as: QG = QK + QS + QB Eq. (1) Where Q K, Q S and Q B are the charges related to intrinsic-drain (V K ), Source and Body node respectively. These charges are obtained as a function of normalized forward current i f and normalized reverse current i r as used in EKV model [2]. All non-ideal charges (fixed, mobile and interface trap charges) are assumed to be positive. As the gate is n+ poly-silicon, the gatesemiconductor work function difference is negative for both n and p type materials and depends on the doping concentration of these zones [3]. These two remarks lead to the clear conclusion that the flat-band voltage (V FB ) for drift zone is negative and the drift part can be always considered in accumulation for positive gate bias. The total accumulation charge Q Drift is calculated by integrating normalized accumulation charge density q Drift over drift length. Thus total gate charge can be written as: QG = QK + QS + QB + QDrift Eq. (2) 3. Results This model was calibrated on the simulated and measured characteristics of FND40 (a 40V device from I2T100 technology with width W=40µm, channel length L=1.2µm, drift length 3-5µm and oxide thickness t ox =42nm) provided by AMI Semiconductor. 3.1 Model results against numerical simulation for DC characteristics V D =0.5V V D =0.1V (a) D1.2 EKV based L-DMOS Model update including internal temperatures 3

4 V D =0.5V 1.00E E-07 V D =0.1V 1.00E E (b) V D =0.5V g m (A/V) V D =0.1V (c) D1.2 EKV based L-DMOS Model update including internal temperatures 4

5 1.00E-02 V D =0.5V g m( A/V) 1.00E E-10 V D =0.1V 1.00E E-18 (d) Fig. 3. Transfer characteristics for V D = V, T=27 C, W=40µm, model (red) vs. simulation (black): a) and (b) I D vs. V G in lin-lin and log-lin scales, (c) and (d) g m vs. V G in lin-lin and log-lin scales V D = 5V V D = 1V (a) D1.2 EKV based L-DMOS Model update including internal temperatures 5

6 0.01 V D = 5V 1E-05 V D = 1V 1E-08 1E-11 1E-14 (b) V D = 5V g m (A/V) V D = 1V 0 (c) D1.2 EKV based L-DMOS Model update including internal temperatures 6

7 1 V D = 5V g m (A/V) E-08 V D = 1V 1E-12 1E-16 (d) Fig. 4. Transfer characteristics for V D = 1 5V, T=27 C, W=40µm, model (red) vs. simulation (black): a) and (b) I D vs. V G in lin-lin and log-lin scales, (c) and (d) g m vs. V G in lin-lin and log-lin scales V G = 13V V G = 1V (a) D1.2 EKV based L-DMOS Model update including internal temperatures 7

8 V G = 13V g ds (A/V) V G = 1V (b) V D (V) Fig. 5. Output characteristics for V G = 1 13V, T=27 C, W=40µm, model (red) vs. simulation (black): a) I D vs. V D, (b) g ds vs. V D. 4.2 Model results against measurements for DC characteristics 2.0E-03 V D = 0.5V 1.5E E E E+00 V D = 0.1V (a) D1.2 EKV based L-DMOS Model update including internal temperatures 8

9 1.0E-01 V D = E E-09 V D = 0.1V 1.0E-13 (b) 6.0E-04 V D = 0.5V g m (A/V) 4.0E E E+00 V D = (c) D1.2 EKV based L-DMOS Model update including internal temperatures 9

10 1.0E-03 V D =0.5V g m (A/V) 1.0E E-11 V D =0.1V 1.0E-15 (d) Fig. 6. Transfer characteristics for V D = V, T=27 C, W=40µm, model (red) vs. measurement (black): a) and (b) I D vs. V G in lin-lin and log-lin scales, (c) and (d) g m vs. V G in lin-lin and log-lin scales. 1.2E-02 V D = 5V 8.0E E E+00 V D = 1V (a) D1.2 EKV based L-DMOS Model update including internal temperatures 10

11 1.0E-01 V D = 5V 1.0E E-09 V D = 1V 1.0E-13 (b) 1.2E-03 V D = 5V g m(s) 8.0E E E+00 V D = 1V (c) D1.2 EKV based L-DMOS Model update including internal temperatures 11

12 1.0E-02 V D = 5V g m(s) 1.0E E-10 V D = 1V 1.0E-14 (d) Fig. 7. Transfer characteristics for V D = 1 5V, T=27 C, W=40µm, model (red) vs. measurement (black): a) and (b) I D vs. V G in lin-lin and log-lin scales, (c) and (d) g m vs. V G in lin-lin and log-lin scales. 1.2E-02 V G = 13V 8.0E E E+00 V G = 3V V D (V) (a) D1.2 EKV based L-DMOS Model update including internal temperatures 12

13 4.0E E-03 g ds (A/V) 2.0E-03 V G = 13V 1.0E E+00 V G = 3V V D (V) (b) 1.0E-03 VG=13V g ds (A/V) 1.0E E-07 VG=3V 1.0E (c) V D (V) Fig. 8. Output characteristics for V G = 1 13V, T=27 C, W=40µm, model (red) vs. measurement (black): a) I D vs. V D, (b) and (c) g ds vs. V D in lin-lin and log-lin scales. D1.2 EKV based L-DMOS Model update including internal temperatures 13

14 3.3 Model results for AC characteristics Model versus Simulation 60 V D = 0V V D = 1V V D = 2V C gd (ff) V D = 5V V D = 10V 0 Fig. 9. Gate-to-Drain Capacitance (C gd ) vs. V G (red - model and black - simulation data) C gd (ff) 20 V G =13V V D (V) Fig. 10. Gate-to-Drain Capacitance (C gd ) vs. V D (red - model and black - simulation data) VD=10V C gs (ff) VD=5V VD=2V VD=0V Fig. 11. Gate-to-Source Capacitance (C gs ) vs. V G (red - model and black - simulation data). D1.2 EKV based L-DMOS Model update including internal temperatures 14

15 3.3.2 Model versus Measurement 60 V D = 3V C gd (ff) V D = 5V 0 V D = 20V Fig. 12. Gate-to-Drain Capacitance (C gd ) vs. V G (red - model and black - measurement data). D1.2 EKV based L-DMOS Model update including internal temperatures 15

16 3.4 Model accuracy: achievements versus targets According to the initial ROBUSPIC accuracy targets, the developed model has been evaluated in terms of accuracy over all the operation regimes, and essentially in linear, quasilinear and saturation region of operation. The typical errors obtained for the corresponding characteristics shown in figures 3-12 are presented in table 1. It is remarkable that this model is able to provide RMS errors that are typically lower than 10% over all operation regions for DC part and the maximum error obtained is close to 25%. Extremely accurate results are obtained for g m (about 10% RMS), which demonstrate the fact that the value of the intrinsic channel mobility is physical and accurate. Table 1. Maximum and RMS error obtained using the analytical model. Self-heating and Impact ionization effect not included. Region Parameter Target LDMOS Max error LDMOS RMS Error I D V G (V D =0.1V-0.5V) I D V G (V D =1V-5V) I D V G (V D =10V-50V) I D Better than 10% g m Better than 20% I D Better than 10% g m Better than 20% I D Better than 10% g m Better than 20% I D V D I D Better than 10% g ds Better than 20% 200* 92.09* C gd V G C gd Better than 20% C gs V G C gs Better than 20% * Values strongly affected by the SHE Of a special concern is the output conductance, g ds, which, accordingly to table 1, presents increased errors. In order to explain why this difference appears one should compare simulation with measurement. On Fig. 8a, we took the characteristics corresponding to V G =13V and we made a zoom between V D =12.8V and 13.8V (Fig. 13). It is interesting to note that the difference between the simulated and measured currents gives a maximum error less than 5% for the presented curves. The output conductance calculated on the measured D1.2 EKV based L-DMOS Model update including internal temperatures 16

17 current (black dashed curve) is negative as the current is affected by the self-heating effect. The simulated current presents a positive output conductance (red dashed curve). This sign difference (negative-positive) between the simulated and measured output conductances is the source of this increased error on the output conductance. Even if the self-heating effect is taken into account (as it will be presented in the next section), this task on accuracy (errors) is still very difficult to achieve. ID(A) 1.20E E E E E E E E E E E-05 gds(s) 1.14E E VG(V) Fig. 13. Output characteristics V G =13V measurement (black) vs. simulation (red). Left-hand axis current, right-hand axis output conductance. 4. Modeling of Special Effects 4.1 Modeling of Impact Ionization Current When the drain bias across LDMOS increases, the electric field in the drift region also increases as a function drain bias. In this high field zone, the longitudinal electric field E y varies linearly and reaches its peak value at the drain junction. The Impact Ionization current (or avalanche current) is given by: Iavl = ( M 1). IDS Eq. (3) Where I DS is the drain-to-source current and M is called as Multiplication factor. Fig. 14 shows that the impact ionization effect is modeled well and provides very good results on simulated output characteristics and does not create any ill convergence V G = 13V V G = 1V V D (V) Fig. 14. Output characteristics (I D vs. V D ) including impact ionization current, model (red) vs. simulation (black) D1.2 EKV based L-DMOS Model update including internal temperatures 17

18 4.2 Modeling of the Self-Heating Effect A special target in this project is related to the simulation of the self-heating effect. This effect appears when high levels of power are attained in the device. The dissipated heat leads to the increase of the internal temperature of the device. The internal temperature increase influences the characteristics of the device by affecting mainly the mobility, the threshold voltage and the velocity saturation. In the literature, this effect was mainly studied on the SOI devices. Basically the proposed models are distributed or non-distributed models. As it is expected, better accuracy was obtained on distributed models, which offer a larger flexibility for the current simulation. Still, the clear advantage of the non-distributed models over the distributed ones remains the parameter extraction procedure, which relates the physics of the devices with the simulation and offers a simple, efficient representation of the problem. Figure 15 presents the equivalent sub-circuit used for the self-heating representation. This already classical representation can be used for the combined DC/AC simulation of the device in some critical regimes (other than analog operation). Moreover, we have already demonstrated that this representation is suitable for further improvements of the model, in which the thermal parasitic components depend on the internal temperature of the device. T(f)-T 0 P AC P D R th C th Z th > ~2MHz f Fig. 15. (a) Representation of the parasitic electro-thermal circuit for SHE simulation, (b) Frequency response of the electro-thermal circuit. In steady state conditions the temperature difference (due to SHE) for an injected power and at a given external temperature is written as: ( ) ( ) T = RTH T PD = RTH T VD ID Eq. (4) where P is the injected electrical power. In agreement with Walkey s report [4], we propose to consider in eq. (4) the thermal resistance dependence on temperature linearly approximated by [5]: [ + α(t T )] R TH (Ti ) = R THNOM (Te ) 1 i e Eq. (5) where T e, T i are the external and internal temperatures, respectively and is also considered a linear function of the external temperature T: e R THNOM(T e) = RTHNOM _ 298K 1 +α( Te 298K). One should note that in eq. (5), the temperature increase, T= Ti Te, at known external temperature T e is essentially given by SHE (related to the injected electrical power, P), and, consequently, R THNOM could be considered as the nominal thermal resistance at zero injected power (and given external temperature, T e ). The proposed formalism for describing R TH is needed for our extraction. Another key assumption for the extraction of the thermal resistance is to consider the mobility as the parameter most affected by the SHE [6]. The effect of temperature on the threshold voltage, V T, could reasonably be eliminated by using D1.2 EKV based L-DMOS Model update including internal temperatures 18

19 measurements of the output characteristics at VG V T(T e) = constant. Consequently, at each given external temperature, T e, V T has been extracted from the intercept with the horizontal axis of the linear I D / gm vs. V G plot [7]. It follows that the drain current is expressed as: ( 1+ T / T ) k I D = I D0 e Eq. (6) where I D0 is the SHE-free current and k is the coefficient of the low field mobility reduction with temperature (a value of k = 2.1 has been extracted for our HV device 1 using the slope of I / g V at low V D [7]). By combining eqs. (4), (5) and (6) we obtain: D m G = = α Eq. (7) T T ( ) 1/ k e I R D0 /ID 1 THNOMPD Eq. (7) suggests that ( 1/R THNOM ) is the slope of the linear dependence of ( 1/ T) on ( D ) 1/P. Fig. 16 depicts typical linear plots validating this modeling and extraction procedure from room temperature up to 150 C on a 100V DMOSFET (W=250µm) provided by AMIS. 1/ T (K -1 ) V G V T = 5.9V R THNOM=7.47 (K/W) T e=298k (25 C) K (150 C) /Slope = R THNOM /P (W -1 ) Fig / T versus 1/P D with the device (wafer) external temperature, T e, as parameter (using a temperature step of 25 C, and based on measurements with [V G -V T (T e )]= 5.9V). For the simulation purpose, we used for the first trail only the classical representation of the electro-thermal circuit with fixed thermal resistance and capacitance. This representation will be improved with the linear dependence of the thermal resistance R TH in order to improve the model performances function of the external temperature. To assure the convergence stability for this developing phase of the model, only the mobility was considered to be affected by the thermal effects. We postponed also the implementation of thermal influence on the saturation velocity and threshold voltage in order to assure ill-free convergence of this prototype. 1 One should note that in HV DMOSFETs this coefficient is typically slightly higher that in low voltage MOSFETs, where its value is close to 1.5. D1.2 EKV based L-DMOS Model update including internal temperatures 19

20 The simulations performed for room temperature show a clear improvement of the model performances for the output characteristics. The negative current slope was correctly simulated at high gate voltage values, while for lower gate voltages no affection of the current was obtained, which in fact is confirmed by the real behavior of the device (Fig. 17). 12 ID (ma) V D (V) Fig. 17. Output characteristics (I D vs. V D ) including self-heating effect implementation for V G = 3 13V, T=27 C, W=40µm, model (red) vs. measurement (black). Table 2 presents the errors obtained on the output characteristics simulated using the electro-thermal circuit. The errors were diminished on the output characteristics in terms of current. It can be observed that even if the self-heating effect is correctly simulated, high errors are still present for the simulation of the output conductance. The problem originates form the changing slope of the current on the output characteristics. On the linear regime, the output conductance is positive. The current affected by SHE effect leads to a negative output conductance. If impact ionization occurs the current rises once again leading to the positive output conductance. It is very difficult to mach the change of the sign of the output conductance between the simulated with the experimental data (Fig. 18). However, a reduction of 20% in RMS error for the output conductance was obtained when the SHE was included in the simulation (see Table 1 and 2). Fig. 19 shows the output characteristics using analytical model including both selfheating and impact ionization effect. D1.2 EKV based L-DMOS Model update including internal temperatures 20

21 Table 2. Maximum and RMS error obtained using the analytical model including Selfheating and Impact ionization effect Region Parameter Target LDMOS Max error LDMOS RMS Error I D V G (V D =0.1V-0.5V) I D Better than 10% g m Better than % I D V G (V D =1V-5V) I D Better than 10% g m Better than % I D V G (V D =10V-50V) I D Better than 10% g m Better than % I D V D (without SH* and II* effect) I D g ds Better than 10% Better than % I D V D (with SH* and II* effect) I D g m Better than 10% Better than % C gd V G C gd Better than 20% C gs V G C gs Better than 20% *SH- Self Heating, II- Impact Ionization. D1.2 EKV based L-DMOS Model update including internal temperatures 21

22 ID(A) 1.162E E E E E E E E E E E E E E E E E E E E VG(V) gds(s) Fig. 18. Output characteristics V G =13V measurement (black) vs. simulation (red). Left-hand axis current, right-hand axis output conductance V G = 13V V G = 3V V D (V) Fig. 19. Output characteristics (I D vs. V D ) including self-heating effect and impact ionization current for V G = 3 13V, T=27 C, W=40µm, model (red) vs. measurement (black). D1.2 EKV based L-DMOS Model update including internal temperatures 22

23 5. Temperature Dependence of Parameters Following intrinsic MOS (EKV) parameters are affected by temperature [8]: VTO( T ) = VTO TCV.( T T ) T KP( T ) = KP. T nom BEX nom T UCRIT ( T ) = UCRIT. Tnom BEX T T T PHI( T ) = PHI. 3. Vt.ln Eg ( Tnom). + Eg ( T ) Tnom Tnom Tnom 6. Scalability of the Model against Physical Parameters Scalability of the model against physical parameters drift length and device width was tested. Results are presented for two different devices having different voltage capability. 6.1 Drift Length The scalability against drift length was tested on numerical simulation data of FND60 (a 60V device from I2T100 technology) provided by AMI Semiconductor. Fig. 20 to fig. 22 shows the results for transfer and output characteristics. 3.0E-05 V D = 0.5V 2.0E E-05 V D = 0.1V 0.0E+00 (a) D1.2 EKV based L-DMOS Model update including internal temperatures 23

24 V D = 0.5V 1E-06 V D = 0.1V 1E-10 1E-14 1E-18 (b) 1.2E-05 V D = 0.5V 9.0E-06 g m (A/V) 6.0E E E+00 V D = 0.1V V G (V) (c) D1.2 EKV based L-DMOS Model update including internal temperatures 24

25 1.0E-05 V D = 0.5V 1.0E-08 V D = 0.1V g m (A/V) 1.0E E E-17 V G (V) (d) Fig. 20. Transfer characteristics for V D = V, T=27 C, W=40µm, model (red) vs. simulation (black): a) and (b) I D vs. V G in lin-lin and log-lin scales, (c) and (d) g m vs. V G in lin-lin and log-lin scales. 1.6E-04 V D = 5V 1.2E E E-05 V D = 1V 0.0E+00 (a) D1.2 EKV based L-DMOS Model update including internal temperatures 25

26 1.00E-02 V D = 5V 1.00E-06 V D = 1V 1.00E E E-18 (b) 3.0E-05 V D = 5V 2.0E-05 g m (A/V) 1.0E-05 V D = 1V 0.0E+00 (c) D1.2 EKV based L-DMOS Model update including internal temperatures 26

27 1.0E-05 V D = 5V 1.0E-08 V D = 1V g m (A/V) 1.0E E E-17 (d) Fig. 21. Transfer characteristics for V D = 1 5V, T=27 C, W=40µm, model (red) vs. simulation (black): a) and (b) I D vs. V G in lin-lin and log-lin scales, (c) and (d) g m vs. V G in lin-lin and log-lin scales. 3.0E-04 V G = 13V 2.0E E E+00 V G = 1V V D (V) D1.2 EKV based L-DMOS Model update including internal temperatures 27

28 (a) 6.0E-05 g ds (A/V) 4.0E E-05 V G = 13V 0.0E+00 V G = 1V (b) V D (V) g ds (A/V) 1.0E E E-08 V G = 13V 1.0E-10 V G = 3V (c) V D (V) D1.2 EKV based L-DMOS Model update including internal temperatures 28

29 Fig. 22. Output characteristics for V G = 1 13V, T=27 C, W=40µm, model (red) vs. simulation (black): a) I D vs. V D, (b) and (c) g ds vs. V D in lin-lin and log-lin scales. 6.2 Device Width (BOSCH Contribution) The scalability of the model against device width was tested on measurement data for three different devices by BOSCH. The measurement data were obtained for a minimum, a medium and a large width device, with several gate stripes, for a 40V LDMOS device in a smart power process used by Bosch. Fig. 23 and 24 show the results for transfer and output characteristics. (a) (b) D1.2 EKV based L-DMOS Model update including internal temperatures 29

30 (c) Fig. 23. Transfer characteristics for a 40V LDMOS device, model (blue) vs. measurement (red): I D vs. V G for a) minimum width, (b) medium width and (c) maximum width. (a) D1.2 EKV based L-DMOS Model update including internal temperatures 30

31 (b) (c) Fig. 24. Output characteristics for a 40V LDMOS device, model (blue) vs. measurement (red): I D vs. V D for a) minimum width, (b) medium width and (c) maximum width. D1.2 EKV based L-DMOS Model update including internal temperatures 31

32 References: [1] C. Anghel, N. Hefyene, A. M. Ionescu, M. Vermandel, B. Bakeroot, J. Doutreloigne, R. Gillon, S. Frere, C. Maier, Y. Mourier, "Investigations and Physical Modelling of Saturation Effects in Lateral DMOS Transistor Architectures Based on the Concept of Intrinsic Drain Voltage," presented at 31st European Solid-State Device Research Conference, [2] C. Enz, F. Krummenacher, E. Vittoz, "An analytical MOS transistor model valid in all regions of Operation and dedicated to low-voltage and low-current applications," Analog Integrated Circuits and Signal Processsing, pp , [3] Y. Tsividis, Operation and Modeling of the MOS Transistor, 2nd ed: McGraw-Hill, [4] D. J. Walkey, T. J. Smy, T. Macelwee, M. Maliepaard, "Compact representation of temperature and power dependence of thermal resistance in Si, Inp and GaAs substrate devices using linear models," Solid State Electronics, vol. 46, pp , [5] C. Anghel, R. Gillon, A. M. Ionescu, "Self-heating characterization and extraction method for thermal resistance and capacitance in HV MOSFETs," IEEE Electron Device Letters, vol. 25, pp , [6] W. Redman-White, M. S. L. Lee, B. M. Tenbroek, M. J. Uren and R. J. T. Bunyan, "Direct extraction of MOSFET dynamic thermal characteristics from standard transistor structures using small signal measurements," Electronics Letters, vol. 29, pp , [7] G. Ghibaudo, "New method for the extraction of MOSFET parameters," Electronics Letters, vol. 24, pp , [8] D1.2 EKV based L-DMOS Model update including internal temperatures 32

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