A Novel Approach to the Layer Number-Controlled and Grain Size- Controlled Growth of High Quality Graphene for Nanoelectronics

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1 Supporting Information A Novel Approach to the Layer Number-Controlled and Grain Size- Controlled Growth of High Quality Graphene for Nanoelectronics Tej B. Limbu 1,2, Jean C. Hernández 3, Frank Mendoza 1, Rajesh K. Katiyar 1, Joshua James Razink 4, Vladimir I. Makarov 2, Brad R. Weiner 1,5, Gerardo Morell 1,2 1 Institute for Functional Nanomaterials, San Juan, Puerto Rico, 00931, USA 2 Dept. of Physics, University of Puerto Rico, Río Piedras, San Juan, PR , USA 3 Dept. of Biology, University of Puerto Rico, Río Piedras, San Juan, PR , USA 4 Center for Advanced Materials Characterization, University of Oregon, Eugene, OR 97401, USA 5 Dept. of Chemistry, University of Puerto Rico, Río Piedras, San Juan, PR, , USA Section 1. Figure S1 shows the schematics of the HFCVD reactor that we employed for graphene growth. It consists of a Mo substrate holder on top of a BN heater that can be heated to a maximum temperature of 1100 o C. The filaments consist of four 0.5-mm diameter Re wires suspended in parallel at 8.0 mm above the substrate with the help of a Mo holder. The substrate holder-heater assembly is on a retractable base that allows to adjust the distance between the filaments and the substrate. A gas shower in the shape of U lies above the filaments from where the precursor or carrier gases or the mixture are released into the reaction chamber. *Corresponding authors: (Brad R. Weiner) & (Tej B. Limbu) S-1

2 Figure S1. A schematic representation of the HFCVD reactor showing its main components: filaments, substrate heater, copper substrate, and gas shower. Methane molecules are partially dissociated at the hot filaments prior to interacting with the substrate. Section 2. Copper foil annealing We annealed the copper foil in the HFCVD reactor prior to graphene deposition. The copper foil was placed on the substrate heater supported with a wire mesh of diameter 0.5 mm. Hydrogen and N 2 gases were flowed into the chamber at the flow rates of 80 and 20 sccm, respectively maintaining the total chamber pressure of 35 Torr. When the pressure reached, the substrate heater was ramped at 35 o C/min to reach the target temperature of 1000 o C. The temperature was maintained at 1000 o C for 40 minutes and finally cooled naturally to room temperature while the gases were flowing. The annealing process is summarized by the first portion of Figure S2. S-2

3 Annealing step Deposition step Temperature ( o C) 1000 o C 40 min minutes Room T Evacuation & H 2 filing Time (min) Figure S2. A schematic representation of the sequential steps followed for copper substrate annealing and graphene deposition in the HFCVD reactor. Section 3. Figure S3. (a) Low magnification HRTEM image of suspended tblg on TEM grid. (b) Histogram of the BLG twist angles determined from FFTs of HRTEM images and SAED patterns collected from different grains. S-3

4 Section 4. Fabrication of graphene-based field effect transistor For the electrical characterization of graphene, back-gated graphene-based field effect transistor (FET) devices were fabricated on SiO 2 /Si by employing photolithography. The device fabrication process started with spin coating of lift off resist (LOR) (LOR 3A, MicroChem Corp.) on graphene/sio 2 /Si (Figure S4a) for 45 seconds followed by baking at 150 o C on a hot plate for 5 minutes (Figure S4b). Then, the LOR coated samples were spin-coated with a positive photoresist (PR) (S1813, MicroChem Corp.) for 40 seconds followed by baking at 100 o C for 45 seconds (Figure S4b). The samples were then placed on a mask aligner (OAI Hybralign series 200), a photomask of desired features was aligned, and exposed to UV radiation of intensity ~350 / for 25 minutes. The UV exposed samples were developed in developer (MF- 319, MicroChem Corp.) for 45 seconds, washed in DI water, and dried with nitrogen blow. The developer dissolves the photoresist and LOR in the areas where UV was exposed through photomask (Figure S4c). About 70 nm thick gold (Au) layer is deposited on the PR/LOR/graphene/SiO 2 /Si assembly by thermal evaporation (Vacuum Evaporator VE10, Mikros Inc.) (Figure S4d). The samples were dipped into dimethyl sulfoxide (DMSO) for about 2 hours to dissolve the photoresist and LOR, and Au pattern of desired shape was obtained on graphene/sio 2 /Si (Figure S4e). In order to remove unwanted graphene from the FET device, a second step lithography was performed. The samples with Au electrodes were spin coated with photoresist, and baked as in the previous step (Figure S4f). The samples were aligned in the mask aligner with the mask which consisted of a counter structure. The counter feature consisted of a rectangular shaped opaque region (chrome-coated) of suitable area on the bare glass photomask. During UV exposure of the resist-coated samples, all the region was exposed except the rectangular area. After development, the photoresist covered only a small rectangular region (size same as in the photomask) at the desired area of the graphene/sio 2 /Si containing Au electrodes (Figure S4g). Finally, the unprotected region of the graphene was etched out by oxygen plasma to obtain graphene based back gated FET device (Figure S4h). S-4

5 Figure S4. A schematic representation of the steps employed for the fabrication of graphene based FET device by photolithography. S-5

6 Section 5. Figure S5. HRTEM images of (a) monolayer, and (b) twisted bilayer graphene with wellstitched grain boundaries Section 6. Figure S6. D band evolution as a function of substrate temperature for (a) monolayer, (b) bilayer (25 o twist angle), and (c) few-layer graphene. S-6

7 Section 7. Graphene growth on SiO 2 /Si We grew graphene on SiO 2 /Si substrate in the HFCVD reactor by using copper foil as a source of copper vapor. A piece of SiO 2 /Si was first cleaned by ultrasonicating in acetone and isopropanol solution separately for 10 minutes each, and finally rinsed with DI water and blown with nitrogen gas. A piece of copper bigger in size than SiO 2 /Si was cleaned and annealed as usual (see the main text or Section 2, supporting information). After completing the annealing process, the heater was cooled down to room temperature, and the chamber opened. The cleaned SiO 2 /Si was immediately placed on top of the annealed copper as shown in Figure S7a. Then the chamber was evacuated to a pressure of 25 mtorr and filled with a mixture of hydrogen and methane at a ratio of 16:1 until the total pressure reached 35 Torr. The substrate was heated at a rate of 35 o C/min to 975 o C of growth temperature. When it reached the target temperature, the filaments were turned on to reach the temperature of 1600 o C. Then hydrogen gas was completely stopped and methane flow rate was kept constant at 2 sccm, and the growth continued for 80 minutes. We note that the graphene growth conditions when SiO 2 /Si substrates are employed differ from those for copper substrates. We tried to grow graphene on SiO 2 /Si with the same growth conditions as those for copper, but they did not lead to the formation of graphene due to insufficient concentration of methane. After completion of growth process, we tried two different cooling methods: (1) when filaments and heater were turned off, the methane flow was stopped and the system was allowed to cool to room temperature; and (2) methane flow was stopped and 100 sccm of N 2 gas was flowed until the temperature of heater decreased to room temperature. The cooling conditions did not alter the growth of graphene significantly. A typical Raman spectrum collected from the as grown graphene on SiO 2 /Si is shown in Figure S7b. It shows the G and 2D bands characteristic of graphene crystal at 1588 cm -1 and 2684 cm -1, respectively. The D band with high intensity appears at 1345 cm -1, which is indicative of significant defect density in the grown graphene. We believe that the quality of graphene grown on SiO 2 /Si can be increased by optimizing the growth parameters, which however, is beyond the scope of this work. The inset of Figure S7b shows a photograph of as grown graphene on SiO 2 /Si which loses its shiny and smooth surface due to the formation of graphene and cooper contamination. A closer look at the optical image of graphene/ SiO 2 /Si (Figure S7c) shows the rough nature of the surface of SiO 2 /Si. Figure S7d and S7e show S-7

8 the energy dispersive spectrum (EDS) of the as grown graphene on SiO 2 /Si obtained in two different cooling conditions mentioned above. The quantitative analysis shows a significant reduction on the copper contamination of the sample (from 0.74 At% to under detection limit) when cooling was carried out at 100 sccm of N 2 gas. The flow of N 2 gas flushes out a significant amount of the copper vapor out of the chamber. A high magnification SEM image of the graphene/sio 2 /Si obtained when cooling was carried out with N 2 is shown in Figure S7f. The image clearly shows copper nanoparticles of size ~100 nm. The particles consisted of a high At% of copper in the EDS (not shown here). This shows that copper vapor is produced when the copper foil is heated during the growth process, and subsequently condenses during the cooling process. However, copper nanoparticles may also form during the growth process due to the deposition of copper on the SiO 2 /Si substrate. Figure S7. (a) A schematic of the graphene growth on SiO 2 /Si in the HFCVD reactor. (b) Raman spectrum collected from graphene grown on SiO 2 /Si, showing D, G and 2D bands. The inset shows a photograph of graphene/sio 2 /Si. (c) Optical image of graphene/sio 2 /Si. (d) EDS collected from graphene/sio 2 /Si. There was no gas flow after the deposition ended. (e) EDS collected from graphene/sio 2 /Si. 100 sccm of N 2 gas was flowed after the deposition ended. (f) S-8

9 A high magnification SEM image of graphene/sio 2 /Si from the process mentioned in (d), showing copper nanoparticles. Section 8. Figure S8. A photograph of the HFCVD reactor during graphene deposition on copper (left). The photograph of the heater and filament holder after deposition (right) depicts the copper stain on the heater surface, and copper coatings on the filament holder rods. S-9