Heavy ion radiation damage simulations for CMOS image sensors

Transcription

1 Heavy ion radiation damage simulations for CMOS image sensors Henok Mebrahtu a, Wei Gao a, Paul J. Thomas b*, William E. Kieser c, Richard I. Hornsey a a Department of Computer Science, York University, Toronto, Ontario, Canada b Topaz Technology Incorporated, Toronto, Canada c IsoTrace Laboratory, University of Toronto, Toronto, Ontario, Canada ABSTRACT Damage in CMOS image sensors caused by heavy ions with moderate energy (~10MeV) are discussed through the effects on transistors and photodiodes. SRIM (stopping and range of ions in matter) simulation results of heavy ion radiation damage to CMOS image sensors implemented with standard 0.35µm and 0.18µm technologies are presented. Total ionizing dose, displacement damage and single event damage are described in the context of the simulation. It is shown that heavy ions with an energy in the order of 10 MeV cause significant total ionizing dose and displacement damage around the active region in 0.35µm technology, but reduced effects in 0.18µm technology. The peak of displacement damage moves into the substrate with increasing ion energy. The effect of layer structure in the 0.18 and 0.35 micron technologies on heavy ion damage is also described. Keywords: CMOS image sensor, total dose, displacement damage, single event effect, heavy ion irradiation 1. INTRODUCTION Image sensors have broad applications in space, including robotic vision, optical navigation and tracking for landers and explorers, space craft visual telemetry, cameras for space and earth observatory satellites etc. CCD and CMOS based sensors (like CMOS APS image sensors) are the main technologies employed for digital imaging. CMOS technology has some practical advantages over its counterpart CCD technology such as lower operating power, higher radiation tolerance, lower clock voltages, integration functions into one chip etc., though CCD is used to produce better quality images. Recent developments in CMOS active pixel sensor (APS), however, have improved the performance of CMOS imagers. These advantages have led to widespread use of CMOS based image sensors and cameras and thus has led to space deployment of such devices. CMOS APS are very sensitive analog electronic devices. The photo-generated current is on the order of a few picoamperes. Thus, these devices are inherently sensitive to various radiation sources prevalent in space. Radiation effects are known to create ionization dose, displacement and single event effects damage in semiconductor materials and circuits (see Fig. 3). Extensive reviews of the radiation damage of CMOS microelectronic circuits can be found in 1-7. Previous work has also been done on radiation-induced damage to CMOS active pixel sensors 8. Total dose and displacement damage studies have also been reported on for radiation-hardened CMOS APS 9. These studies have focused on radiation damage studies, mainly using Co-60, energetic protons, heavy ions with very high energy (for single event effect studies) on the pixel level. Little is known on heavy ion radiation damage of CMOS APS with moderate energy (tens of MeV). This is particularly important because these ions can actually stay within the structure of the semiconductor device, unlike those of higher incident energies. To understand the behavior of a CMOS image sensor pixel under heavy ion irradiation, an understanding of the behavior of each constituent component is of fundamental importance. Transistors and photodiodes are two basic components in a CMOS APS image pixel (see Fig. 1a). Different processing technologies will result in different device sizes and layer thicknesses of the devices. Understanding how heavy ions interact with materials of the device, such as * paul.thomas-topaz@rogers.com

2 energy loss along the ion penetrating depth, ion stopping range in the device, and nonionization profile, can help us to predict the damage caused by the heavy ions. In our work, we used the SRIM simulation to study the interaction of heavy ions with two device structures corresponding to the transistor and photodiode fabricated with standard 0.35µm and 0.18µm technologies. Energy loss, ion range, and displacement damage are addressed in our simulation. In section 2, we will briefly describe the operation of a CMOS APS pixel under normal and radiation environments. Section 3 gives an overview of radiation effects in CMOS microelectronic circuits. Detailed layer structures for 0.35µm and 0.18µm process are presented in section 4. SRIM simulations are described in section 5, followed by a discussion of future work. 2. CMOS IMAGE SENSOR Transistors and photodiodes are the basic building blocks of a CMOS active pixel sensor (APS). A typical configuration of these transistors and a photodiode in a CMOS APS pixel is shown in Fig. 1a. It consists of a reset, a source follower, and row select transistors and a photodiode. A timing diagram is shown in Fig. 1b. The operating principle of this pixel is as follows. The photodiode operates in reverse-biased mode with parasitic capacitance coming from the photodiode itself, reset and source follower transistors sitting beside it. This reverse-biased junction is charged to a predetermined value by applying an external voltage to the reset transistor. This charge accumulation increases the built-in potential within the depletion region resulting in wider depletion region and a lower capacitance. After the capacitor is charged, the reset transistor is turned off. Photons enter the photodiode through the upper coating. While photons of certain wavelengths are absorbed in the upper layers, other photons reach the depletion region. As a photon hits the depletion region of this reverse-biased p-n junction, the integration process starts. In the integration phase, the photon generates electron-hole pairs in the depletion region. The generated electron-hole pairs are swept across the junction by the electric field within the depletion region to constitute a photocurrent. This photocurrent will discharge the photodiode capacitance. Thus, the amount of discharge will be proportional to the intensity of photons entering the device. The output of the photodiode capacitor is then obtained by applying a pulse signal at the select transistor. In this image sensor, the junction area of the photodiode defines its sensitivity while the thickness of its bulk substrate determines the speed. Fig. 1a. A typical architecture of a CMOS APS pixel. Fig. 1b. CMOS APS pixel timing diagram. When a CMOS image sensor is exposed to heavy ion radiation, prevalent in the space environment, its electrical characteristics will be affected, which is illustrated in Fig. 2. For the transistor, heavy ions can cause ionization both in the oxide layer and the silicon itself. Ionization in the oxide layer can induce positive hole-traps which can increase the leakage current in the channel. Ionization in the silicon can generate excess electron hole pairs which might be captured by a sensitive node to flip the state of that node. Displacement damage in the silicon also can affect the leakage current and the device speed. For the photodiode, excess electron-hole pairs induced by the ionization in the silicon can

3 increase the dark current dramatically. The effect of electrical or optical degradation of the individual transistor and/or the photodiode will culminate in the degradation of the electrical and optical parameters of the pixel. Fig. 1b also shows the degradation of photo-signal due to photodiode and transistor leakage current. The following section will describe in detail radiation effects in CMOS microelectronic circuits caused by heavy ions. Fig. 2. Heavy ion interaction with (a) transistor (b) photodiode. 3. RADIATION EFFECTS The effect of radiation damage on semiconductor devices and circuits can be described as total ionization dose, single event effect and displacement damage effects (Fig. 3). A brief description of these damages is provided below. Fig. 3. Diagram of heavy ion damages effects. 3.1 Ionizing dose damage The cumulative damage incurred in semiconductor devices due to exposure to ionizing radiation is referred to as total dose effect 2. Ionization energy loss in silicon dioxide generates electron-hole pairs which have intrinsically different mobilities 10, 11. A fraction of the generated electron-hole pairs undergo recombination while the remaining electrons quickly drift to interfaces in the case of an applied field 12. The low mobility of holes and the presence of interface traps near SiO 2 /Si layers results in the trapping of holes within the silicon dioxide layer 13. These trap sites acquire a positive charge state after capturing a hole. These positive oxide traps in the gate-substrate insulation layer of MOS transistors and capacitors shift the threshold voltage of the devices while also increasing leakage current. The amount of this shift

4 is empirically computed to vary with the square of oxide thickness 13. Positive oxide traps in the field oxide can also result in parasitic current leakage between adjacent electrical components in a semiconductor die. Current submicron technology has very thin gate oxides, generally less than 10nm, which reduces the effect of gate-insulator trap dramatically, and so leaves the effect of field oxide trapping dominant. Ionizing radiation damage also introduces processes that weaken the passivation of Si surfaces resulting in an increased interface trap density and electrical exposure of electronic states within the silicon interface The strain and lattice mismatch at the Si/SiO 2 interface inherently introduces continuous electronic energy levels within the interface which are compensated during device processing 17. However, ionizing radiation damage exposes these electronic states. Unlike oxide traps, the charge state of interface traps depends on the Fermi level within the device This type of damage appears within the surface of the active region. In addition to any threshold voltage shift it can cause for MOS transistors and capacitors, it also affects charge mobility. 3.2 Displacement Damage Displacement damage refers to those non-ionization energy loss mechanisms that introduces lattice defects in semiconductor materials and devices 3, 21. These lattice defects are initiated by ejection of atoms from their equilibrium position by incident energetic ions, electrons, protons, neutrons or by energetic secondary atoms or electrons originating from other processes. These result in the creation of vacancies and interstitial pairs, where an atom is displaced from its original site and deposited at a nonlattice position. Replacement collisions can also appear when the original position of the knocked out atom is taken by the displacing ion. These defects disturb the periodicity of the crystalline semiconductor structure introducing new localized energy levels into the forbidden energy band gap. Changes caused by these effects include: enhancing the thermal-generation of electron-hole pairs through the intermediate energy level; affecting the recombination rate of carriers; serving as temporary trap centers for carriers; introducing compensation effects for donors and acceptors; serving as a ground for tunneling of carriers; and increasing the scattering effect for carriers. These affect electrical parameters such as leakage current, conductivity, and mobility of carriers Damage due to a high energy ion (single event effects) A highly energetic ion generates excessive electron-hole pairs that can cause a temporary (soft errors such as singleevent latch-up, snapback, functional interrupt, multiple upset) or permanent (hard errors such as single event burnout, gate rupture) damage. This may result in temporary circuit disruption, logic change or permanent failure of the device 4-6. For single event upset to take place, the energy deposited by the energetic ion must exceed a threshold value of the particular device. 4. CHIP CHARACTERIZATION The layer profile used for our simulation is extracted from a data sheet of typical 0.35 and 0.18 micron technologies. A 0.35 micron fabrication technology uses 4 metal and passivation layers on top of the active region as shown in Fig. 4 (a). On the other hand, 0.18 micron technology uses 6 metal and passivation layers on top of its active region (see Fig 4 (b)). The horizontal dimension is extrapolated for simplicity for effects being accounted later in our analysis. The detailed layer dimension information used here is provided in Table 1. As shown in these figures, although the feature size of the 0.18µm technology is smaller than for the 0.35µm, the upper layer of the 0.18µm technology is around 10 microns thick which is thicker than 7.7µm the material layer over the active region in the 0.35 micron technology. On the other hand, the individual thicknesses of metal, poly-silicon and dielectric layers are smaller in the 0.18µm technologies. In both technologies, aluminum, silicon dioxide (or Fluorine Silicon Glass), and silicon are used as metal, dielectric and active regions layers; the exact composition of the passivation layer is regarded as proprietary by the foundries. Thus, in our analysis, we used silicon dioxide (SiO 2 ) as a substitute for all the passivation layers. The number of metal layers above a particular active area of a transistor may vary over the area of the transistor. Our simulation was carried out by taking consideration of such variations. In the worst case, a heavy ion can pass through all these metal layers before reaching the active region. While in the other extreme, it may pass directly to the active region without hitting any metal layer on its way. In intermediate cases, the heavy ion can encounter one to three or one to six metal layers for the 0.35 and 0.18 micron technologies respectively. For the photodiode, the active area is covered with

5 antireflective substances and a small aluminum contact is applied to the front surface of the device. Therefore, almost no metal layer is found over its active area. Moreover, unlike a transistor where the thickness of the layers is fixed for particular technology, the thickness of the photodiode coating is optimized for a specific optical wavelength. (a) (b) Fig. 4. Layer profile of (a) 0.35 µm technology and (b) 0.18 µm technology. Layer Thickness(um) Distance to Active Composition (nominal) (um)(nominal) Passivation SiO 2 + Si 3 N 4 Metal Aluminum M4-M3 Insulator 1 5 SiO 2, FSG * Metal Aluminum M3-M2 Insulator SiO 2, FSG Metal Aluminum M2-M1 Insulator SiO 2, FSG Metal Aluminum M1-Active Insulator 1 SiO 2, FSG *: Fluorine Silicon Glass (a) Layer Thickness(um) Distance to Active Composition (nominal) (um)(nominal) Passivation SiO 2 + Si 3 N 4 Metal Aluminum M6-M5 Insulator SiO 2, FSG Metal Aluminum M5-M4 Insulator SiO 2, FSG Metal Aluminum M4-M3 Insulator SiO 2, FSG Metal Aluminum M3-M2 Insulator SiO 2, FSG Metal Aluminum M2-M1 Insulator SiO 2, FSG Metal Aluminum M1-Active Insulator 0.8 SiO 2, FSG (b) Table 1. Layer dimensions in (a) 0.35 µm technology (b) 0.18 µm technology.

6 5. SRIM SIMULATIONS We simulate the ionization damage inflicted by heavy ions on MOS transistor and photodiode layer structures using SRIM codes. SRIM codes developed by J. F. Ziegler and J. P. Biersack are widely used to calculate the stopping power and range of ions in matter by using a quantum mechanical treatment of the ion-atom collision 22. In its collision treatment, SRIM considers Coulombic and nonrelativistic interactions. The calculations use statistical algorithms for efficient computations and the codes can easily be run on standard workstations. In our simulation, we have used the stopping power version SRIM The stopping power of ions using SRIM-2003 codes have been correlated against vast experimental data with ion energies ranging 1-10,000keV for light ions and 1-100,000keV for heavy ions, with an estimated error of 4.6% 22. SRIM codes include a comprehensive Monte Carlo program called TRIM (Transport of Ions in Matter) which provides us detail treatment of ion damage cascades and the ion distribution within the target. This can give us a quantitative estimate of the damage on the layer structure of the transistor or photodiode. SRIM codes are freely available and can be downloaded from the reference cited above. The layer structures shown in Fig. 4 are simulated under the bombardment of the 13 C +4, 14 N +5, 16 O +6, 19 F +7, 35 Cl +7 and 126 I +7 heavy ion species that can readily be found at ISOTrace laboratory of the University of Toronto. ISOTrace is an accelerator mass spectrometry facility employing a 2MV accelerator for a variety of ion species, which is used primarily for dating and trace element analysis. The results of the simulations are summarized in Table 2 for the two cases where the heavy ion passes through all the available metal layers and no metal layer at all. These scenarios can serve as a boundary cases for the ion penetration ranges due to the different combination of metals it can encounter along its path. Ion range (um) Ion Charge 0.35 micron 0.18 micron Ion Energy state (MeV) 0-Metal 4-Metal 0-Metal 7-Metal layers layers layers layers 12 C N P O F Cl I Table 2. Ion species used for simulation. The energy of the ion species available at ISOTrace depends on the attainable charge state of the ion and on the terminal voltage of the accelerator according to Equation 1. The values of ion energy given in Table 2 are attained at terminal voltage of 2MV which is the upper operating voltage of the facility. Thus, higher charge state ions can be accelerated to higher ion energy. E = 0.02MeV + ( Q + 1) V (1) where E is ion energy in ev, Q is charge state of the ion and V is terminal voltage of the accelerator in Volts. Heavy ions that can penetrate deep to the active region of a semiconductor device and deliver enough energy that will inflict damage to the electrical parameters of the device. Thus, we found F to be a good candidate for our testing. The simulation shows that the 16 MeV F +7 ions penetrate to a depth of 8.78µm (Fig. 5.) and 8.87µm through no metal layer structures in 0.35µm and 0.18µm technologies, respectively. With this energy, the peak of the F +7 ions distribution can penetrate into the silicon in the 0.35µm technology, while it is just above the silicon surface in 0.18µm technology. In this case, however, the tail of the distribution still enters the silicon substrate.

7 (a) (b) Fig. 5. Ion range distribution of 16 MeV F +7 ions with in (a) 0.35 micron and (b) 0.18 micron process layer structures. The vulnerable parts of a semiconductor device to ionizing dose damage are the dielectric layers 1, 2. Excess electrons created within the metal layers quickly dissipate due to high conductivity of the metal. Ionizing radiation damage on the gate oxide, in the case of MOS transistors and capacitors, and the field oxide layers are particularly important because of their proximity effect to the active region. In our simulation with 16 MeV F +7 ions on 0.35 micron technology layer structure, most of this energy is deposited in the metal and dielectric layers above the active region with the Bragg peak appearing roughly in metal layer 2 as shown in Fig 6. When the ion reaches the dielectric and field oxide regions at a depth of around 7.80µm (for the 0.35 micron technology), slightly more than 80 ev/å per ion is dissipated as ionization energy loss. Thus, one fluorine ion of the stated energy passing these areas deliver about 4.1 x 10-5 rad (Si) to the structure, which can be readily obtained from Equation 2. In the 0.18 micron technology however, only a negligible amount is lost in a similar process. de D = Φ (2) dx where D is dose in rad(si), de/dx is linear energy transfer in ev/å, Φ is ion flux per cm 2 and the constant 6.9 x 10 7 is a conversion factor to rad(si). Heavy ions are predicted to cause significant displacement damage to semiconductor devices because of their higher momentum. The displacement damage, target vacancies and replacement collisions, caused by 16 MeV Fluorine ions in 0.35 micron structure are shown in Fig. 7 and Fig. 8 respectively. The non-ionization energy loss of the heavy ion increases as its energy is decreased. Thus, the extent of the displacement damage is observed to dominate around the final tracks of the heavy ions where the ion s energy is mostly lost through previous ionizing energy interactions. The effect of displacement damage is significant when it appears in the active region of the devices where there is carrier transport. From the simulation, at the top layer of the active region, around 0.05 vacancies/ion/å are created. Most of the vacancy-interstitial pairs are believed to recombine while few of them will form stable complexes resulting in localized generation-recombination centers. The relatively stable replacement damage in this region is found to be slightly larger than replacements/ion/å. This is expected to affect the mobility of the carrier transport while the former damages minority carrier lifetime. For MOS transistors and photodiodes, which rely on majority carrier transport, mobility degradation will be more significant.

8 Fig. 6. Ionization energy losses of 16 MeV F +7 ions in the 0.35 micron process structure. Fig. 7. Target vacancies for 16 MeV Fluorine ion damage in 0.35 micron technology. Fig 8. Replacement collisions for 16 MeV Fluorine ion damage in 0.35 micron technology. Our simulation for ionization energy loses with highly energetic heavy ions in the order of 100 MeV is shown in Fig 9, as a comparison with the lower energies of interest here. This shows that the heavy ions penetrate through the device. This is different from the simulation result with ions of the order of 10 MeV where the heavy ion stays in the device structure. Heavy ions at this energy also show little non-ionizing energy loss. Fig. 9 show that the energy deposited in the active region of the 0.35 micron technology is in the order of 10 2 ev/å or 10 3 MeV cm 2 /g (normalized against density of silicon). This energy transfer (LET) corresponds to a charge generation in the order of 10 9 ion pairs. If this charge generation appears in a sensitive part of the device it can create a noticeable upset. However, these single

9 energetic ions will create negligible total dose effects because most of these carriers recombine due to short electronhole separation 23. Fig 9. Ionization energy loss by 100MeV fluorine ion in 0.35 micron structure. According to the ion penetrating profiles, ion energy loss data, and displacement damage distributions in the 0.35µm and the 0.18µm technologies, we can predict that, with a moderate energy (in the order of 10MeV), heavy ions can cause significant total ionization dose and displacement damage in both transistors and photodiodes in the 0.35µm technology. A more serious problem might be caused by ions implanted in the silicon, which may change the doping density and lattice structure in the substrate and active areas, such as drain, source and channel area in the transistor, and n + area in the photodiode. As such, the electrical characteristics of these devices can be affected to some extent in leakage current, dark current, threshold voltage, device speed, etc. Additional defects and traps are also expected to degrade the noise performance of the devices. Heavy ions with such moderate energy induces less total ionization dose and displacement damage in the silicon for the 0.18µm technology, but it will also cause damage to the insulator and silicon interface area, which could change the interface state dramatically and lead to a degradation in the transistor and photodiode characteristics. 6. DESIGN OF EXPERIMENT These simulation results are to be correlated with our design of experimental work at ISOTrace Laboratories. These experiments will be performed on standard 0.35 micron MOS transistors, photodiodes and CMOS APS chips under a vacuum environment. These devices will be mounted on a PCB board with electrical feedthrough. The electrical response of the chips will be monitored before, during and after irradiation with and without applied bias. In our experimental setup, the issues of beam alignment, fluctuation and distribution are expected to be significant. The diameter of the ion beam of the accelerator ranges from 1-3 mm during focused and defocused modes respectively. The chips mounted on a PCB board will be maneuvered vertically toward the ion beam line through a manipulator attached to the board. The total area of the chips range from 4mm 0.66mm to 3.2mm 0.13mm though the area of the actual transistors is much smaller. Given the smallness of the beam diameter, correct calibration of the manipulator will be important to ensure the desired spot of the device is exposed. The horizontal tilt of the board towards the ion beam will also be important with regards to this issue.

10 The intensity of ion beam source may also fluctuate during testing. The acceleration voltage of the accelerator and the ions species chosen will affect the stability of the ion intensity. These fluctuations will have a significant impact on the dose delivery measurement calculations. Monitoring the beam intensity during the test and statistical characterization of the beam intensity will be important. An approximate Gaussian ion distribution is assumed in the heavy ion beam. The degree of spread of the Gaussian will be dependent on the focus of ion beam. A defocused beam will provide slightly uniform exposure to the device under test at the cost of reduced beam intensity to a specific area with in the semiconductor chip. Hence, measuring the total intensity of the beam and translating it to the amount of beam intensity delivered to a particular area of the chip will be vital. 7. CONCLUSION Our simulation work shows that heavy ions with moderate energy are expected to cause significant damage to the layer structure of the device resulting in total dose and displacement damage. The damage inflicted is enhanced by the fact that ions of this energy remain within the device structure. The thickness of the layers on top of the active region of different processing technologies have some effect on the range of ions. This may result in variation of the damage caused by ions for different processing technologies. However, the variation in the upper thicknesses of the 0.35 and 0.18 micron processing technologies has little effect on highly energetic ions, though one 0.18 micron technology is expected to be more susceptible to this type of damage because of its smaller feature size. ACKNOWLEDGEMENTS This work was supported by the Centre for Research in Earth and Space Technology (CresTech) and Topaz Technology Inc. We would like to gratefully acknowledge the technical assistance from IsoTrace Lab at University of Toronto, including the valuable discussions with Mr. X.L. Zhao and the use of their facilities. We also wish to thank Ms. Winnie Wong and Mr. Edward. Shen who helped prepare this manuscript. REFERENCES 1. H. L. Hughes and J. M. Benedetto, "Radiation effects and hardening of MOS technology: devices and circuits," Nuclear Science, IEEE Transactions on, vol. 50, pp , T. R. Oldham and F. B. McLean, "Total ionizing dose effects in MOS oxides and devices," Nuclear Science, IEEE Transactions on, vol. 50, pp , J. R. Srour, C. J. Marshall, and P. W. Marshall, "Review of displacement damage effects in silicon devices," Nuclear Science, IEEE Transactions on, vol. 50, pp , F. W. Sexton, "Destructive single-event effects in semiconductor devices and ICs," Nuclear Science, IEEE Transactions on, vol. 50, pp , P. E. Dodd and L. W. Massengill, "Basic mechanisms and modeling of single-event upset in digital microelectronics," Nuclear Science, IEEE Transactions on, vol. 50, pp , D. R. Alexander, "Transient ionizing radiation effects in devices and circuits," Nuclear Science, IEEE Transactions on, vol. 50, pp , A. H. Johnston, "Radiation effects in light-emitting and laser diodes," Nuclear Science, IEEE Transactions on, vol. 50, pp , G. R. Hopkinson, "Radiation effects in a CMOS active pixel sensor," Nuclear Science, IEEE Transactions on, vol. 47, pp , Bogaerts, B. Dierickx, G. Meynants, and D. Uwaerts, "Total dose and displacement damage effects in a radiationhardened CMOS APS," Electron Devices, IEEE Transactions on, vol. 50, pp , J. R. S. a. K. Y. C. O. L. Curtis Jr., "Hole and electron transport in SiO2 films," Journal of Applied Physics, vol. 45, pp , 1974.

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