Roll-to-roll manufacture of organic transistors for low cost circuits

Transcription

1 Roll-to-roll manufacture of organic transistors for low cost circuits Hazel Assender Dr Gamal Abbas, Ziqian Ding Department of Materials University of Oxford DALMATIAN TECHNOLOGY 21 st Sept

2 Acknowledgements Bangor Prof Martin Taylor Aled Williams Eifion Patchett Oxford Dr Kanad Mallik Leeds Prof Long Lin Dr Weidong He Manchester Prof Steve Yeates Dr John Morrison 21 st Sept

3 Flagship project Can we manufacture transistors/simple circuits from organic materials using R2R vacuum evaporation processes? Need to consider: 1) Process parameters in R2R environment building and testing transistors 2) Circuit design tailored for the properties achievable with this manufacturing route 3) Materials (semiconductor and gate insulator layer) developed for this manufacturing route 4) Patterning processes 5) Robustness of final devices 21 st Sept

4 Roll-to-roll processing Oxford vacuum web coater Webspeed up to 5 ms -1 Web width 350 mm 21 st Sept

5 The story so far. Source and Drain (Metal) L Org. Semiconductor Gate W Possible interlayer Insulator (acrylic) Possible surface modification Substrate (e.g. PET) 0 V S-D (V) S-D (na) -5 I -10 0V -10V -20V -30V -40V 21 st Sept

6 Materials developments Moved from glass to PEN substrates Moved from Au to Al gate electrode New masks: shorter S/D length, multiple transistors Tried new semiconductor, DNTT Anticipated better stability Still high mobility Tried insulator acrylate with higher permittivity Thinner layer deposition More polarizable Pentacenes S S DiNapthoThienoThiophene DNTT 21 st Sept

7 Depositing the insulator In-line process High speed i. Evaporate monomer (liquid) ii. Condenses onto substrate (web) as a liquid (flat) iii. Polymerize (cure) in-situ 21 st Sept

8 FTIR indicates full cure IV curves of e-beam cured device E-beam cure Poor saturation, greater hysteresis, poor stability (A) D I D (µa) I V D (V) V -20V -30V -40V I (A) D (µa) D You can solve these issues by annealing Anneal at 150 C for 1 hour I V D =-60V D =-40V V G (V) I on /I off = 1.3x10 3 V th = 10V µ = 0.1cm 2 /Vs NB At a web speed of 50m/min, this annealing time requires a web path length of 3km! 21 st Sept

9 Plasma cure Cures in a single pass of the plasma as the polymer is deposited (although several passes of deposition are made for small-scale experiments) I D (ma) V I on /I off =3.2x V G (V) (I D ) 1/2 (µa 1/2 ) I D (ma) V- drak I on /I off =1.1x V G (V) (I D ) 1/2 (µa 1/2 ) E-beam-cured TRPGDA Plasma-cured TRPGDA 21 st Sept

10 Device Lifetimes (I D ) 1/2 (µa 1/2 ) V d =-50V 3 I on /I off =2.1X10 1st scan 10th scan V G (V) I D (µa) Intensity (a.u) (001) (002) (003) (004) (005) θ (degrees) I D (µa) V -20V -30V -40V -50V V D (V) OFETs with plasma-cured dielectric show a reasonably stable performance in air over 10 cycles 21 st Sept

11 Shelf-life stability I D (A) st week (I ) 1/2 D (µa) 1/ V G (V) st week weeks 15-weeks V G (V) (I D ) 1/2 (µa) 1/2 1 st Week 15 th Week I on /I off 2.0x x10 2 V th (V) µ (cm 2 /Vs) st Sept

12 Interfacial modification Self-assembled monolayers are required in printed organic transistors Modify the insulator surface to become more hydrophobic A hydrophobic (PS) layer gives improved pentacene morphology & devices with PS without PS without PS Scale: 1µm = with PS Less effect is seen with fresh pentacene material st Sept

13 Surface modification Improved pentacene morphology gives better devices Greater mobility, lower off-current 21 st Sept

14 Testing in Vacuum See a lower off-current and higher mobility Device Performance (devices with PS layer characterised in vacuum) I on /I off up to 10 7, Mobility 0.4cm 2 /Vs Very small operational degradation at moderate voltage 0 Id(µA) Transfer and IV curves of pentacene on SB3 dielectric on PEN substrate Investigate encapsulation methods 21 st Sept

15 Device encapsulation Well-established vacuum deposition methods for gas barrier layers Used for food packaging e.g. acrylate insulator/smoothing layer followed by Al or AlOx Could be fully-integrated into the process Al, acrylate barrier layer L DNTT or pentacene Gate (Al) Substrate (PEN) W Source and Drain (Au) PS interlayer Insulator (acrylic) Al, acrylate barrier layer 21 st Sept

16 Progress so far.. 1) Process parameters in R2R environment building and testing transistors Shorter S/D length Plastic substrates Al gate electrode Improved curing method Surface modification layer Hysteresis measurements In-vacuum testing 21 st Sept

17 Progress so far 2) Circuit design tailored for the properties achievable with this manufacturing route Transistor modelling underway based on device measurements 3) Materials (semiconductor and gate insulator layer) developed for this manufacturing route New SC synthesised, more under development Tried new insulator material 4) Patterning processes Favoured options for SC and insulator layers under development 5) Robustness of final devices Planning encapsulation experiments 21 st Sept