A Layout Dependent Full-Chip Copper Electroplating Topography Model

Transcription

1 A Layout Dpndnt Full-Chip Coppr Elctroplating Topography Modl Jianfng Luo, Qing u, Charl Chiang and Jamil Kawa Advancd Tchnology Group, ynopy Inc., Mountain Viw, CA, UA Abtract In thi papr, a layout dpndnt full-chip lctroplating (ECP) topography modl i dvlopd bad on th additiv natur of th phyic of th ECP proc. Two layout attribut: layout dnity, and fatur primtr um ar ud to comput th pot-ecp topography. Undr a unifid mchanim, two output variabl rprnting th final topography: th array hight, and th tp hight ar modld imultanouly. Uing th propod modl long-rang ffct of th ECP proc can b incorporatd aily a wll. Th imulation rult of our modl wr vrifid with tt tructur xprimntal data publihd in th litratur and ar prntd in thi papr. Th rult how that th rror ar l than 5%. Thi modl i not limitd to th rgular tt tructur; it can alo b ud for any practical dign. Th rult of uch partial application ar hown hr a wll. Our propod ECP modl can b ud to modl ytmatic variation caud by an ECP proc or by a chmical mchanical planarization (CMP) proc. Th potntial application of thi modl includ: layout dign valuation for catatrophic failur prvntion; yildawar dign (dign for manufacturability), and variationawar timing analyi. Indx: Cu ECP, Cu CMP, Full-Chip Modl, Layout Dnity, Primtr, Dign for Manufacturing/Yild 1. Introduction Elctroplating (ECP) and chmical mchanical planarization (CMP) proc hav gaind broad application in coppr (Cu) intrconnct pattrn gnration in th back nd proc of ub- 130nm tchnology nod [1]. Cu i pattrnd uing a proc known a damacn proc. During th Cu damacn proc, trnch and hol ar firt tchd in th oxid matrial. An ECP proc i applid to dpoit th Cu onto th whol wafr filling up th trnch. It i followd by a CMP proc in which xc ovrflowing Cu i rmovd from th oxid urfac laving Cu in th intndd trnch and hol; forming intrconnct wir and via. Dpnding on whthr via and wir ar pattrnd paratly or imultanouly, th Cu pattrning proc i calld ingl damacn proc or dual damacn proc, Fig. 1. Hard mak M2 Cu Wir via M1 Cu wir Oxid Barrir Figur 1. Coppr damacn proc architctur Dual Damacn ingl Damacn Th Cu and oxid thickn aftr th damacn proc i not uniform acro th whol chip. Intad, ytmatic Cu and oxid thickn variation ar obrvd. Th ytmatic variation ar found to b layout dpndnt. For xampl, whn Cu wir width i changd from 0.9µm to 100µm, a variation > 100nm in th Cu thickn i obrvd [2]. Thi thickn variation i around 20% for th nominal wir thickn of 550nm. A fatur iz cal down, th ytmatic variation ar gaining mor ignificanc. Modling of th pot-cmp Cu and oxid thickn variation in th dp ubmicron ra i critical for th following thr raon. Firt i th tringnt dpth of focu (DOF) rquirmnt of th lithography proc. With th lithography wavlngth tuck at 193nm and not kping up with tchnology caling, th DOF budgt of th lithography tool ha bn rducd to vral hundrd nanomtr (200~400nm). Thi tringnt DOF rquirmnt dictat that th CMP proc gnrat a urfac with thickn variation l than 100nm. Thu it i crucial that on b abl to prdict oxid and mtal thickn variation aftr CMP with topography modling and imulation. cond i th nd to compar and valuat th impact of diffrnt yild improvmnt mthod. For xampl, in ordr to valuat and compar th topography uniformity improvmnt rulting from diffrnt dummy-fill pattrn, a topography modl i ndd to imulat th rulting thickn variation of ach pattrn. Third i th nd to analyz th impact of th pot-cmp thickn variation on timing. Cu and oxid thickn variation rult in wir ritanc and capacitanc variation; which in turn impact th timing of a path in a chip [3, 4]. Topography modling can hlp th dignr in valuating intrconnct paraitic variation. To modl th pot-cmp Cu and oxid thickn variation accuratly, a modl to prdict th pot-ecp topography i firt ndd. Th pot-ecp topography trongly dpnd on layout pattrn, a hown in Fig. 2. On of th firt ECP modl to how thi dpndncy i th on propod by Park [5]. In that modl, th two variabl that rprnt th topography: array hight H and tp hight, ar modld by two parat polynomial. Th two variabl H and ar hown in Fig. 2. Thy will b formally dfind in ction 3. Th two polynomial ar xtractd and calibratd with maurd data from tt tructur. Th modl i vry accurat for rprnting th tt tructur that ar ud for th calibration [5]. Howvr, thr ar vral potntial problm with thi modl. Firt, without conidring th phyic involvd in th ECP proc, th intraction btwn th array hight and th tp hight i miing. Thrfor, two parat polynomial hav to b ud to modl th variabl. A numbr of calibration paramtr, 5 for th array hight and 5 for th tp hight, hav to b ud. A lack of phyical inight into th calibration paramtr may potntially lad to ovr-fitting. cond, th mpirical modl in [5] for topography i formulatd a a function of wir width and pacing. It i ufficint for rgular layout pattrn in tt tructur bcau th valu for th wir width and pacing ar uually th am. Howvr, for practical dign, in th am layout window, th objct hav diffrnt wir width and pacing. Thrfor, uing a ingl t of width and pacing valu to rprnt th whol layout window would gratly dgrad th accuracy of th modl. Third, in th modl in [5], th impact of layout pattrn on topography i quit local. Howvr, an intraction ditanc of 20~50µm ha bn obrvd from xprimnt [6-7]. Thi impli that th calculation of topography X/05/$ IEEE. 133

2 imply bad on th wir width and pacing right at th fatur location may not b accurat in th firt plac. Thrfor, th concpt of intraction lngth and wightd dnity function ar ndd to account for th long rang intraction in th ECP proc. Howvr, incorporating tho two concpt into th modl in [5] i difficult. To addr th abov problm, a phyic-bad layout dpndnt ECP topography modl i propod in thi papr. Th ky ida i that th volum of Cu dpoitd i proportional to th urfac ara, which i dfind a th um of th trnch bottom ara, th trnch top ara, and th trnch idwall ara. Th ky advantag of our modl ar a follow. (i) Undr a unifid mchanim, th array hight and tp hight can b obtaind imultanouly. In addition, thr ar only four calibration paramtr in th modl, much fwr than th tn calibration paramtr rquird in th mpirical modl in [5]. Th phyical ignificanc of th calibration paramtr in our modl i clarr and thrfor th rik of ovr-fitting i lowr. (ii) Th layout attribut, layout dnity, and primtr um - intad of th wir width and pacing - ar ud in our modl to rflct th dpndncy of th topography on th layout. Th layout attribut ar applicabl to any arbitrary layout pattrn in a practical dign. (iii) Th whol chip i mhd into a numbr of mall til. Th topography modl i dirctly built around th til intad of around ach mall fatur. Th intraction lngth can b incorporatd into th modl aily to conidr th long-rang intraction in ECP proc. : tp hight H: array hight Fild H H H H H 0 Oxid Top urfac 2 - = Cu. Th Cu ion dpltd from th chmical olution will b rplnihd from th olid Cu anod. Figur 3. An lctroplating ytm [5] A major challng for th convntional ECP proc in th ub-micron ra i to fill up th high-apct-ratio ub-micron trnch with no void. A void i dfind a a hol inid a Cu or a filling matrial. It may cau an opn circuit. Th primary raon for void formation i a fatr dpoition rat at th nck of th trnch than at it bottom. Thrfor, void formation may b avoidd by appropriatly adjuting th local dpoition rat. Th currnt tat of art Cu ECP proc to prvnt void formation i a bottom-up fill proc whr th dpoition tart at th bottom of th trnch and mov upward. To achiv uch a bottom fill bhavior, additiv chmical known a acclrator, uppror, and lvl ar addd to th plating olution. Thy ar adorbd on th wafr urfac to ithr acclrat or uppr th local dpoition rat. Acclrator uppror C= Chlorid ion L= Lvlr t= 0 c Wafr immrd in plating bath. Additiv not yt adorbd on Cu d t= 2 c Wafr immrd in plating olution prior to currnt flow. Additiv adorbd on Cu d. Fin Wir Fin pac Larg Wir Larg pac Fin Wir Larg pac Larg Wir Fin pac t=10 c t= 20 c Figur 2. A typical topography aftr ECP proc [5] Th rmaindr of th papr i organizd a follow: In ction 2, fundamntal of th ECP proc ar dicud. An ECP topography modl i propod in ction 3. ction 4 prnt th algorithm for full chip ECP imulation. In ction 5, imulation rult ar compard againt xprimntal data from tt tructur to dmontrat it accuracy. Th imulation rult of our modl for a ral dign ar alo hown in thi ction. Finally, concluion ar mad in ction Fundamntal of th Elctroplating Proc Fig. 3 how a implifid drawing of a Cu ECP ytm [5]. A wafr coatd with a thin lctrically conductiv layr of d Cu i immrd in chmical olution containing Cu ion. An xtrnal powr ourc i thn connctd btwn th d Cu on th wafr urfac and th olid Cu, which act a a cathod and an anod rpctivly. Th Cu ion in th olution ract with th lctron to form Cu on th wafr whr th currnt i pad through. Thi can b dcribd by th following quation: Cu 2+ + Conformal plating tartd In fatur: acclrating pci accumulat nar ba, diplacing l trongly adorbd additiv. Fill i complt. Cu ovr fatur ha an adorbd xc of acclrating pci Rapid growth nar ba occur a acclrator pci continu to accumulat (build up) du to dcra of urfac ara inid fatur. t= 30 c t= 60 c Dpoition following fill with lvlr or dorption of acclrator prnt. t= 60 c Dpoition following fill without lvlr or dorption of acclrator. Figur 4. Additiv adorption bhavior during ECP [11] 134

3 Thr ar variou thori that try to xplain th rol and intraction of acclrator, uppror and lvl in th bottomup fill bhavior. On of th mot uccful thori i an additiv accumulation thory propod by Rin t al. [11]. Th illutration of additiv bhavior bad on thi thory i hown in Fig. 4 for a ingl trnch and can b dcribd a follow: Onc a wafr with a d layr dpoitd i immrd in th plating olution, bath additiv will b aborbd on th Cu d urfac, and an quilibrium lvl of additiv i on all urfac of th wafr, including both th id wall and th top and bottom of th trnch (t= 2c. in Fig. 4). Du to th quilibrium lvl of chmical additiv, onc th currnt i applid on th olution bath, a conformal plating proc will tart firt (t=10c. in Fig. 4). Aftr a crtain amount of tim (t= 20c. in Fig. 4), th acclrator, which can nithr b incorporatd into th dpoitd Cu urfac, nor b dorbd into th plating olution, tart to mov to th bottom of th trnch. Th uppror will b diplacd by th acclrating pci du to thir wakr adorbing ability. Thi lad to a high concntration of acclrator on th bottom of th trnch. Thrfor th dpoition rat on bottom i fatr than on th idwall and nck, making th dpoition void fr. Thi fundamntal xplanation of th uprfill mchanim ha bn provd to b uccful and i adoptd by vral mor complicatd numrical modl [12-14]. On of th ky ida in th abov modl i that thr i no conumption of acclrator during ECP. Th dpoition rat incra with th amount of th acclrator in th trnch, which i dtrmind by not only th ara of th trnch bottom but alo by th ara of th trnch idwall. For finr trnch with th am idwall ara, a fatr dpoition rat i xpctd du to a highr concntration of acclrator. Thi ida will b applid in th formulation of our topography modl in nxt ction. 3. Pot-ECP Topography Modling 3.1 Trminology and notation dfinition Thr ar vral important trm that w will b uing rpatdly in prnting our modl formulation. Thy ntially rprnt th input and output of our modl. Th two output variabl that rprnt th final topography ar th array hight H, and th tp hight. A hown in Fig. 2 and 5, th array hight H i dfind a th thickn of Cu abov th oxid aftr dpoition; th tp hight i dfind a th diffrnc of Cu hight btwn th Cu abov th oxid and th Cu abov th trnch in th oxid. Whn th hight of Cu abov th oxid i largr than th hight of Cu abov th trnch, th tp hight i a poitiv valu. Othrwi, it i a ngativ valu. Throughout thi papr, w u fatur trnch to rprnt trnch in th oxid. Thy will vntually b th wir and via aftr th CMP proc. Thrfor, thir width ar th am a th wir width. Th dpth of th fatur trnch i dnotd a T, Fig. 5. Whn th tp hight in th Cu topography i poitiv, a trnch rgion i formd in th Cu abov th fatur trnch, a in Fig. 5 (1). It i rfrrd to a a coppr trnch. Whn th tp hight i ngativ, a bump rgion i formd in th Cu abov th fatur trnch, a in Fig. 5 (2). It i rfrrd to a a coppr bump. Th propod modl rli on thr layout paramtr a it input. Thy ar th primtr um L, th fatur dnity ρ, and th topography dnity ρ d. Th primtr um L i dfind a th um of th primtr of all th layout objct in a layout window. For th layout window hown in Fig. 6, L = 2(L 1 +L 2 +L 3 +L 4 +L 5 + L 6 +L 7 +L 8 ) + L 9 +L L 11 + L 12. Not that for th objct croing th window boundari, only th portion of th primtr that i inid th window hould b includd. Th raon for it will b givn in ction 3.3. Th fatur dnity ρ i dfind a th ara of all th layout objct (or fatur trnch) dividd by th total ara of th dign. It i alo rfrrd to a mtal dnity or layout dnity. Th topography dnity ρ d i dfind a th ratio of th ara of th lowr rgion of th dpoitd Cu to th ovrall Cu ara aftr ECP. A mor dtaild dfinition of ρ d for th thr topography ca in Fig. 5 will b givn in nxt ubction. Bid th abov paramtr, w dfin a proc paramtr: fild coppr thickn H 0. It i rfrrd to a th Cu thickn ovr a big mpty ara on th chip whr thr i no Cu wir. H Oxid δ Cu T H δ (1) (2) (3) Figur 5. Thr kind of pot-ecp topographi of a wir 3.2 Thr ca of dpoition topographi Thr ar primarily thr diffrnt topographi that rult aftr an ECP proc. For implicity of th prntation, Fig. 5 (1)-(3) how th thr topographi for a ingl wir only. Howvr, th following dicuion ar applicabl to multi-wir a wll. In ca (1), th Cu abov th oxid i highr than that abov th trnch. Thr i a poitiv tp hight. In addition, th Cu trnch width i mallr than th fatur trnch width in th oxid by amount δ, a hown in Fig. 5 (1). Thi ca i calld conformal fill. In ca (2), th width of th Cu abov th fatur trnch i widr than th fatur trnch width by amount δ. Thi i th diffrntiating proprty for ca (2). Th tp hight can b ithr poitiv or ngativ in thi ca, a to b dicud latr. Fig. 5 (2) only illutrat th ca of a ngativ tp hight for implicity. Thi ca i calld upr fill. In ca (3), th Cu urfac i flat aftr dpoition. =0 in thi ca. Figur 6. An arbitrary layout in window with iz DxD T H T 135

4 Th valuation of topography dnity ρ d for th thr ca can b drivd by dfinition a follow: ρ d = ρ ca (1); ρ d = 1 ρ ca (2), < 0; (1) ρ d = ρ ca (2), > 0; ρ d = 1 ca (3), = 0. whr ρ i rfrrd to a th hrunk dnity for ca (1), and can b calculatd a th fatur dnity aftr hrinking all th layout fatur by an amount of δ ; ρ i rfrrd to a th xpandd dnity for ca (2), and can b calculatd a th fatur dnity aftr xpanding all th layout fatur by an amount of δ. Th dnity variabl ar ndd whn w formulat th dpoitd coppr volum in nxt ction. 3.3 Topography modling for th thr ca In thi ction, w formulat th topography a a function of layout variabl. Thi i don through valuating th volum of Cu aftr dpoition, which can b valuatd from two diffrnt prpctiv. On i from an additiv phyic prpctiv, th othr from a topography gomtry on. Firt, w formulat th dpoitd Cu volum bad on th additiv phyic. On fundamntal concpt in our ECP topography modl i that th volum of Cu dpoitd i proportional to th amount of acclrator on th wafr urfac. Mathmatically, V=αC, (2) whr V i th volum of Cu, α i a proportionality cofficint, and C i th amount of acclrator on th wafr urfac. Bad on th additiv acclration modl th amount of th acclrator C i proportional to th urfac ara A, which i dfind a th um of th oxid ara, th trnch bottom ara, and th trnch idwall ara. Thrfor, C= β A (3) whr β i a proportionality cofficint. For an arbitrary layout in a window with iz DxD a hown in Fig. 6, th urfac ara A can b formulatd a A = T L+ D 2, (4) whr T i th fatur trnch dpth. Not that L i th primtr um including only th portion of th fatur primtr that ar inid th window, bcau only thi portion corrpond to th id wall falling in th window DxD. Conidring that th original concntration of th acclrator aborbd on th idwall may b mallr than that on th top and bottom of th trnch, an ffctiv urfac ara A-ff can b dfind a A-ff = T L+ D 2, (5) whr T i th ffctiv trnch dpth, and T < T. From Equation (2)-(5), an quation for th dpoitd Cu volum V can b obtaind a V = αβ A-ff = αβ(t L+ D 2 ). (6) In ordr to valuat th cofficint α and β, conidr th ca whr thr i no fatur in a givn window. inc L=0, V = αβ D 2. (7) In addition, whn thr ar no fatur in th window, th Cu urfac aftr dpoition i flat. Th Cu thickn i qual to th fild thickn H 0, which can b maurd dirctly from ilicon. Thrfor, V = H 0 D 2. (8) Combining Eq. (7) and (8) yild αβ=h 0, and Eq. (6) can b rwrittn a V = H 0 (T L+ D 2 ). (9) Equation (9) formulat th Cu volum a a function of layout paramtr L and D. Thi quation appli to all thr ca dcribd in Fig. 5 in th lat ubction. Now w will go through ach of th thr topographi to formulat th dpoitd Cu volum bad on th gomtry of ach ca. A. Ca (1) For ca (1), from a topography gomtry prpctiv, th volum of Cu can b formulatd a V = HD 2 - D 2 ρ +TD 2 ρ, (10) whr ρ and ρ ar dfind in ction 3.1 and 3.2. Combining th two formula (9) and (10) for th dpoitd Cu volum, w hav H 0 (T L + D 2 ) = HD 2 - D 2 ρ + T D 2 ρ. (11) Thr ar two unknown variabl in th abov quation, on i th tp hight and th othr i Cu array hight H. Anothr quation i ndd. From th mchanim of Cu volution [11], inc th acclrator in th trnch ar accumulatd on th trnch bottom and can not flow out of th trnch, th growth of th Cu on th oxid urfac that hrink th trnch i olly du to th acclrator aborbd on th oxid, a hown in Fig. 7. Thrfor, th Cu volum on th oxid i formulatd a H 0 D 2 (1-ρ) = HD 2 (1-ρ ). (12) Th volum on th lft id of th abov quation i from th additiv phyic prpctiv and that on th right id i from th gomtry prpctiv. Thrfor, th array hight H can b obtaind a H = H 0 (1-ρ)/(1-ρ ) (13) ubtitution of Eq. (13) into Eq. (11) yild th tp hight a = H 0 (1-ρ)/[(1-ρ ) ρ ] + Tρ/ρ - H 0 T L/(D 2 ρ )- H 0 /ρ (14) Th topography dnity ρ d i qual to ρ in thi ca. B. Ca (2) For ca (2), from th topography gomtry prpctiv, th volum of th Cu can b formulatd a V = HD 2 - D 2 ρ + TD 2 ρ, (15) whr ρ and ρ ar th dfind in ction 3.1 and 3.2. Combining th two formula (9) and (15) for th dpoitd Cu volum, w obtain H 0 (T L + D 2 ) = HD 2 - D 2 ρ + TD 2 ρ. (16) Eq. (16) i on quation for th two unknown variabl: array hight and tp hight. W obtain th othr quation from th topography volution mchanim. In thi ca of upr fill a hown in Fig. 8, only th oxid in th rang of xpanion amount δ i affctd by th acclrator in th trnch. For th oxid out of that rang, th thickn of Cu dpoitd i not affctd. Thrfor it i th am a th Cu fild thickn H 0. Thi lad to th array hight H a H = H 0. (17) ubtituting Eq. (17) into Eq. (16) yild th tp hight a = Tρ/ρ -H 0 T L/(D 2 ρ ). (18) Not that th tp hight in thi ca could b ithr poitiv or ngativ. Poitiv tp hight indicat that th Cu abov th fatur trnch form a trnch, with width largr than th width of th fatur trnch. On th othr hand, ngativ tp hight indicat that th Cu abov th fatur trnch form a bump, with width largr than th width of th fatur trnch. Th 136

5 diffrntiating proprty of thi ca i that th trnch or bump of Cu ar widr than th wir. Th xpandd amount δ i alway obrvd a hown in Fig. 5(2). Dpnding on th tp hight th topography dnity ρ d i ithr ρ or 1- ρ a hown in Eq. (1). Whn th tp hight =0, that lad to th pcial ca of upr fill a will b dcribd in ca (3). Ca (3) impli th whol window i in th rang of th xpandd amount δ. Thrfor th ntir oxid urfac i affctd by th acclrator in th trnch and H i not qual to H 0 any mor. Thi implication will b ud for th ca lction in th nxt ction. Acclrator Figur 7. Th volution of topography in ca (1) Acclrator δ (1) (2) (3) Figur 8. Th volution of topography in ca (2) C. Ca (3) For ca (3), by dfinition, th tp hight = 0. (19) inc from a topography gomtry prpctiv, th volum of dpoitd Cu i formulatd a V = HD 2 + TD 2 ρ. (20) Combining th two quation (9) and (20) for th Cu volum, w hav th following quation H 0 (T L + D 2 ) = HD 2 + TD 2 ρ. Thrfor, th formula for th array hight i obtaind by H = H 0 + H 0 (T L/D 2 ) - Tρ. (21) inc th tp hight =0, th topography dnity ρ d =1. Not in th abov formulation that th trm L/D 2 can b takn a th avrag primtr of window DxD. Thi trm, imilar to th layout dnity ρ, rflct th dnity of primtr in th window. Th advantag of uing thi trm i that th window iz D do not xplicitly how up in th formulation. W dnot it by L avg and will u it in latr ction for convninc. 4. Full Chip imulation Algorithm To valuat th topography acro a whol chip, th chip i dividd into a numbr of til. Each til corrpond to a window of iz DxD a hown in Fig. 6. Auming that th hrinking and xpanding amount δ and δ ar obtaind by xprimntal calibration, th layout dnity ρ, th hrunk dnity ρ, th xpandd dnity ρ, and th avrag fatur primtr L avg in ach til can b xtractd from th layout. Th paramtr can b ubtitutd into th modl formulation in lat ubction to obtain th chip topography. Thr ar two rmaining iu that nd to b addrd for full chip imulation. On i th ca lction algorithm bad on layout pattrn; th othr i th δ (1) (2) δ Cu oxid H=H 0 Cu oxid xtnion of til-cal modling to chip-cal modling by taking th intraction lngth into conidration. 4.1 Ca lction Givn th layout paramtr of a dign and th calibratd proc paramtr, w nd an algorithm to dtrmin which of th thr ca hown in Fig. 5 hould b applid to a particular til to comput array hight H and tp hight. Bcau of th volution proc of topography, th acclrator in th trnch do not affct th Cu growth on th oxid in th arly tag. Thrfor, ca (1), th conformal fill ca, hould alway occur firt. Th tp hight calculatd thraftr hould b largr than 0. Howvr, if for th givn layout pattrn, th calculation of from ca (1) modl turn out to b mallr than 0, it indicat that thr ar too many acclrator for thi particular til to tay in ca (1). Thrfor ithr ca (2) or ca (3) hould occur. In that ituation, th xpandd topography dnity ρ hould b ud to dtrmin whthr ca (2) or ca (3) occur. If ρ < 1, only part of th oxid in th til i affctd by th acclrator in th trnch. Thrfor, ca (2) occur. If ρ = 1, th whol til i affctd by abov dicuion how that th hrunk amount δ, th xpanion proc paramtr to dtrmin which ca a til fall in. Th thr paramtr ar th fitting paramtr for th modl and ndd to b calibratd from xprimntal data. Th framwork of th ca lction algorithm i hown in Fig. 9. Not that th implmntation of th algorithm nd to conidr th xtrm ca a wll. For xampl, whn ρ = 0 or ρ = 0, it man that th topography aftr dpoition i flat. Thrfor it hould dirctly lad u to ca (3) in th ca lction algorithm. Dign Mh chip into til Layout xtraction acro th whol chip for ach til Proc paramtr Layout paramtr in til i (i= 1: N) Finih? i=i+1 Y Rport vry til topography acro th whol chip Aum ca 1 and calculat topography tp Hight >0? Figur 9. Framwork of th full-chip ECP topography imulator Bfor furthr dicuion, it i worthwhil to tak a look at th dpndncy of th ca lction on th layout pattrn. W dicu th following 4 layout pattrn: (A). wid wir and wid pacing, (B) wid wir and fin pacing, (C) fin wir and wid pacing (or iolatd fin wir), (D) fin wir and fin pacing. Not that whn fin or wid wir width and fin or wid pacing ar rfrrd to, it man that th width and pacing ar far mallr or largr than th hrunk or xpandd amount in th topography. No ρ =1? No No Y Y Ca 1 for til i Ca 3 for til i Ca 2 for til i 137

6 A. Wid Wir and Wid pacing Whn th wir i wid, th avrag primtr L avg in DxD i mall. Phyically thi man th contribution of th idwall to th growth of th Cu in th trnch i not ignificant and th growth of th Cu in th trnch i mainly du to th additiv on th trnch bottom. Thrfor, th Cu thickn in th trnch i approximatly qual to th fild Cu thickn. At th urfac of th oxid, th additiv contribut to th growth of both th Cu on th trnch oxid urfac and that hrink (at) into th trnch. Whn th pacing i larg, th amount of Cu hrinking into th trnch i ngligibl, Fig. 7. Hnc, th additiv contribut mainly to th growth of th Cu on th oxid, i.., th Cu thickn on th oxid i approximatly qual to th fild Cu thickn a wll. Th tp hight in thi ituation i approximatly qual to th original fatur trnch dpth T. Thi impli a conformal fill. Thrfor, for wid wir and wid pacing ca (1) of th topography alway occur. B. Wid Wir and Fin pacing Whn th pacing i fin, th hrunk amount of Cu into th trnch i not ngligibl in comparion with th pacing, Fig. 7. Thrfor, th additiv on th top of th oxid contribut to th growth of both Cu on th oxid and that hrink into th trnch. Thi cau th trnch Cu thickn mallr than th fild Cu thickn. inc th thickn of Cu in th wid trnch i approximatly qual to th fild Cu thickn a in layout pattrn (A), th tp hight i mallr than th original trnch dpth. Howvr, th Cu in th trnch will nvr grow highr than that on th top of th oxid. Onc th hight of Cu in th trnch i qual to that on th oxid, th additiv in th trnch will pill out to th oxid and ithr ca (2) or (3) will occur. Bcau th pacing i fin, th whol oxid urfac i covrd by th additiv from th trnch and thrfor ca (3) occur. In an xtrm ca whr th pacing i qual to zro, ca (3) occur from th bginning of dpoition. Thrfor, for a wid wir and fin pacing pattrn, two ca may occur. Whn th pacing i vry fin, ca (3) occur. Whn th fin pacing i rlativly widr, ca (1) occur. C. Fin Wir and Wid pacing Whn th wir i fin, th avrag primtr L avg i larg. Th contribution of th additiv on th id wall to th growth of Cu in th trnch i ignificant compard to that on th trnch bottom. Mathmatically, th tp hight calculatd uing Eq. (14) i mallr than zro. Thrfor, th additiv will pill out at om tag during th dpoition. inc th pacing i larg, th additiv pilld out can not covr th whol oxid urfac. Hnc ca (2) in Fig. 5(2) occur for th iolatd fin wir. D. Fin Wir and Fin pacing Whn th wir i fin, imilar to that in layout pattrn (C), th additiv will pill out of th trnch at om tag during th dpoition. Howvr, inc pacing i fin, th whol oxid urfac i covrd by th additiv pilld out. Thrfor ca (3) occur, a hown in Fig. 5(3). Fig. 2 how typical topographi corrponding to th abov four layout pattrn. From th abov dicuion of th thr pot-ecp topographi, it i clar that th final topography dpnd on layout pattrn intad of imply on th layout dnity. For xampl, a layout pattrn with fin wir and fin pacing and a layout pattrn with wid wir and wid pacing can hav th am layout dnity. But th formr pattrn lad to a conformal topography a in ca (1) and th lattr on lad to a upr-fill topography a in ca (2) or (3). Th primtr play an important rol in ECP topography. Thi indicat that th final topography aftr CMP i not olly a function of th layout dnity. Th dnity bad dummy filling or lotting i not ufficint for Cu CMP. A pattrndrivn dummy filling or lotting algorithm conidring both th layout dnity and th layout fatur primtr i ndd. 4.2 Til iz and Intraction Lngth Anothr iu for chip-cal imulation i th lction of th til iz. Th iz of th til i primarily dtrmind by th intraction lngth of th ECP proc. A til iz that i mallr than th intraction lngth i prfrrd for mor accurat rult. Howvr, th whol chip imulation tim i longr whn th til iz i mallr. Bad on xprimntal data from Park [5], Yang t al. [6] and Towr t al. [7], it i timatd that th intraction lngth of th ECP proc i in th rang of vral micromtr to 50µm. In thi papr, a til iz of 10µm i chon. It i mallr than th til iz ud in CMP imulation, which i uually around 20~40µm du to th rlativly larg intraction lngth in CMP (100~200µm for Cu CMP, 500µm~2mm for oxid CMP). Th convolution of th layout dnity and fatur primtr um in ach til with a pr-dfind wight dnity function can b applid to incorporat th influnc of nighboring til in th rang of th intraction lngth, a that in CMP imulation [8-10]. 5. imulation Rult 5.1 Exprimntal Vrification Exprimntal data on th tt tructur in [5] wa ud to vrify th modl propod in thi papr. Th fild Cu dpoition thickn H 0 i 1.55µm and th trnch dpth T i 0.55µm. Th Cu topographi ovr th tructur with rgular wir width and pacing panning from 0.25µm to 100µm ar maurd uing high rolution profilomtr. Fig. 10 how th topographi maurd with th fild Cu thickn a rfrnc. Th GDII fil for th tt tructur i not availabl to u. Howvr, onc th lin width L W and pacing L ar known, th layout paramtr for th tt tructur can b drivd a: ρ = L /( L + L ), L avg W W = 2 /( L W + L ), 1 whn δ L / 2, ρ = ( LW + 2δ ) /( LW + L ) whn δ < L / 2, 0 whn δ LW / 2, ρ = ( LW 2δ ) /( LW + L ) whn δ < LW / 2. ubtituting th layout paramtr into th modl, w can imulat th array hight H and tp hight. In Fig. 11 th triangl point how th corrlation btwn xprimntal data and th imulation data from our modl. Th corrlation clarly how that th imulation rult fit th xprimntal data wll. Th avrag rror ar 3.23% for th array hight and 4.6% for th tp hight. imulation data obtaind by implmnting th modl in [5] i alo plottd in Fig. 11 for comparion. It corrlation with th xprimntal data i illutratd by th quar point. Th two ubplot in Fig. 11 clarly how that our modl can fit th xprimntal data bttr than th mpirical modl in [5], pcially for tp hight, Fig. 11(b). Th valu of th thr calibration paramtr ar: δ =750nm, δ =133nm, and T =130nm. 138

7 Th valu ar quit raonabl conidring thir phyical maning. Compard with th actual fatur trnch dpth T of 550nm, T =130nm impli that th concntration of th acclrator on th id wall i 130/550= 0.23= 23% of that on th top and bottom of th trnch. δ =750nm indicat that th acclrator in th trnch prad 750nm from ach id of th trnch aftr thy pill out of th trnch. δ =133nm impli that th initial thickn incra on th id wall bfor acclrator moving from th wall to th trnch bottom i 133nm. Thi mall valu mak n conidring th hort tim that th acclrator ar aborbd on th wall. L w /L 0.25um/0.25um 0.3um/0.3um 0.35um/0.35um 0.5um/0.5um 0.7um/0.7um 1um/1um Cu thickn qual to th fild thickn hould b obrvd at lat on th cntr of th oxid. It i obrvd that for th 20µm/20µm wir width/pacing tructur th Cu thickn on th oxid i mallr than th fild Cu thickn, Fig. 10. Hnc, th intraction lngth hould b largr than 20µm. For a imilar raon, th intraction lngth hould b mallr than 50µm inc th Cu thickn on th oxid of th 50µm/50µm tt tructur i qual to th fild Cu thickn alrady, Fig. 10. Thrfor, for 50µm/50µm and 100µm/100µm tructur, th wir width and pacing hould b conidrd to b indpndnt of ach othr. Thi indicat that in th imulation ρ = 1, ρ = 1, ρ= 1, L avg = 0 hould b applid to th til that ar totally covrd by th wid wir, and ρ = 0, ρ = 0, ρ= 0, L avg = 0 hould b applid to th til that ar totally covrd by th pacing. Thi yild a 1.55µm Cu thickn on th oxid pacing and a 1.55µm Cu thickn in th trnch. Th tp hight i 0.55µm, which i th am a th trnch dpth, implying a conformal fill. 2.2 Our Modl Park' Modl 2 2um/2um 5um/5um 10um/10um imulation (um) Park' Modl R 2 =0.981 RM= 55.6nm Err= 3.59% Our Modl R 2 =0.984 RM= 50.1nm Err= 3.23% um/20um 50um/50um 100um/100um Trac Lngth (µm) Exprimnt (um) Park' Modl R 2 =0.947 RM= 47.2nm Err= 8.6% (a) L w /L 0.35um/0.35um 0.7um/0.35um 0.9um/0.35um imulation (um) Our Modl R 2 =0.984 RM= 25.5nm Err= 4.6% 0.1 Our Modl Park' Modl 0.5um/4.5um 1.5um/3.5um 2.5um/2.5um Exprimnt (um) (b) Figur 11. Exprimntal v. imulation rult for (a) H and (b) 3.5um/1.5um 4.5um/0.5um Trac Lngth (µm) Figur 10. Exprimntal pot-ecp Cu topography from [5] Th intraction lngth cannot b dirctly obtaind from thi t of xprimntal data imply bcau th fact that in abov tt tructur, th valu of wir width and pacing ar idntical in a long rang, which i much largr than th actual intraction lngth. Howvr, th intraction lngth rang can b timatd from th xprimntal rult to b btwn 20µm and 50µm. Th raon i that if th intraction lngth i mallr than 20µm, a 5.2 imulation Rult for a Ral Dign On of th main advantag of our ECP modl i that it i not an mpirical modl built on rgular tt tructur. Thrfor, our modl can b applid dirctly to any ral dign, and not limitd by any layout pattrn. imulation on a ral chip (2.45mm 2.35mm) with ix mtal layr wr prformd uing calibration paramtr obtaind from th lat ction. Th CPU (Linux, Intl XEON 2.20GHz, 2.06G) tim including both layout xtraction and topography imulation tim i l than 2 minut for ach layr. W how imulation rult on mtal thr a on rprntativ xampl. To avoid any confuion du to th ngativ tp hight in ca (2), w introduc th urfac hight H and abolut tp hight a in th imulation. Whn th tp hight i poitiv, thy ar qual to th array hight and tp hight rpctivly. Th only 139

8 diffrnc i in ca (2) whr th tp hight i ngativ. In thi ituation, th urfac hight H i qual to H- and th abolut tp hight a i qual to -. Th a i alway poitiv and H i alway th hight hight in th til. Thr ar two purpo for th imulation, on i to tt th applicability of our modl to a ral chip, th othr i to tt th nitivity of th modl to th intraction lngth. Fig. 12 how th imulation rult of th urfac hight H and abolut tp hight a with thr diffrnt intraction lngth 10µm, 30µm and 50µm. Fig. 12 how that raonabl imulation rult wr obtaind. Th H rang from 1.0 to 2.4µm, with 1.0 µm corrponding to th kirt of th chip and 2.4µm corrponding to th cntr of th chip. Thi mak n bcau th kirt i pattrnd with fin pacing and wid wir, whra th cntr of th chip i pattrnd with fin pacing and fin wir. Th a rang from 0 to 0.9µm, with 0µm corrponding to mpty ara on th four cornr of th chip and 0.9µm corrponding to th cntr of th chip. Thi i raonabl bcau on th mpty ara, a flat Cu urfac with fild Cu thickn H 0 i xpctd. For th layout pattrn with fin pacing and wir in th cntr of th chip, th abolut tp hight incra with th array hight, hnc a largr tp hight i obtaind. Th imulation rult in Fig. 12 alo how th nitiviti of th topography to th chang of intraction lngth. Whn th intraction lngth incra from 10µm to 50µm, th urfac hight variation dcra from 1.4µm to 1.2µm; th tp hight variation dcra from 0.9µm to 0.7µm. Thrfor, an accurat calibration of th intraction lngth i ndd for accurat imulation. 6. Concluion In thi papr, a full-chip ECP topography modl i dvlopd. Th ky advantag of our ECP modl ovr an mpirical modl ar: i) It i built bad on additiv phyic in th ECP dpoition proc with much fwr proc paramtr to calibrat. ii) It i a unifid modl for th valuation of array hight and tp hight. Th intraction btwn th two variabl ar prrvd. iii) It can b applid to arbitrary layout pattrn in practical dign. It i not limitd to jut rgular tt tructur. iv) Th incorporation of th intraction lngth into th modl i ay and nabl fficint full chip ECP imulation. Thi modl can b ud for full-chip ECP and CMP topography imulation to hlp valuat a layout for catatrophic failur prvntion, yild-awar dign and variation awar timing analyi. It can alo b applid for th pattrn-drivn modl-bad dummy filling and lotting. 7. Rfrnc [1]. Wolf, ilicon Procing for VLI Era, Vol. 4: Dp ubmicron Proc Tchnology, Lattic Pr, unt Bach, CA, UA, [2] Z. tavrva, D. Zidlr, M. Plotnr, G. Grahoff and K. Drchr, Chmical-mchanical polihing of coppr for intrconnct formation, Microlctronic Enginring, Vol. 33, pp , [3] L. H, A. B. Kahng, K. Tam and J. Xiong, "Dign of IC intrconnct with accurat modling of CMP," Intrnational ocity for Optical Enginring (PIE) ympoium on Microlithograhpy, [4] V. Mhrotra, "Modling th ffct of ytmatic proc variation on circuit prformanc," Ph. D. Dirtation, Dpt. of EEC, MIT, Cambridg, MA, UA, [5] T. H. Park, Charactrization and modling of pattrn dpndnci in coppr intrconnct for intgratd circuit, Ph.D. Dirtation, Dpt. of EEC, MIT, Cambridg, MA, UA, [6] M. X. Yang, D. Mao, C. Yu t. al, ub-100nm intrconnct uing multitp plating, olid tat Tchnology, Oct., [7] J. Towr, A. Maznv, M. Gotin and K. Otubo, Maurmnt of lctroplatd coppr ovrburdn for advancd proc dvlopmnt and control, Advanc in Chmical Mchanical Polihing, Matrial Rarch ocity 2004 pring Mting, an Francico, CA, UA, [8] D. O. Ouma, "Modling of chmical mchanical polihing for dilctric planarization," Ph. D. Dirtation, Dpt. of EEC, MIT, Cambridg, MA, UA, [9] J. Luo and D. A. Dornfld, Intgratd Modling of Chmical Mchanical Planarization for ub-micron IC Fabrication: from Particl cal to Fatur, Di and Wafr cal, pringr-vrlag, Brlin, Grmany, [10] T. E. Gbondo-Tugbawa, "Chip-cal modling of pattrn dpndnci in coppr chmical mchanical polihing proc," Ph.D. Dirtation, Dpt. of EEC, Cambridg, MIT, MA, UA, [11] J. Rid,. Mayr, E. Broadbnt, E. Klawuhn and K. Ahtiani, Factor influncing damacn fatur fill uing coppr PVD and lctroplating, olid tat Tchnology, July, [12] T. P. Moffat, D. Whlr, W. H. Hubr and D. Joll, uprconformal lctrodpoition of coppr, Elctrochmical and olid-tat Lttr, Vol. 4, pp. C26-C29, [13] D. Joll, D. Whlr, W. H. Hubr, J. E. Bonvich and T. P. Moffat, A impl quation for prdicting uprconformal lctrodpoition in ubmicromtr trnch, Journal of th Elctrochmical ocity, Vol. 148, pp. C767-C773, [14] Y. H. Im, M. O. Bloomfild,. n and T.. Cal, Modling pattrn dnity dpndnt bump formation in coppr lctrochmical dpoition, Elctrochmical and olid tat Lttr, Vol. 6, pp. C42- C46, (a.1) urfac hight (b.1) urfac hight (c.1) urfac hight (a.2) abolut tp hight (intraction lngth = 10µm) (b.2) abolut tp hight (intraction lngth = 30µm) (c.2) abolut tp hight (intraction lngth = 50µm) Figur 12. imulation of urfac hight and abolut tp hight undr diffrnt intraction lngth 140